[llvm] [SCEV] Rework IncrementWrapFlags (PR #219559)
Ramkumar Ramachandra via llvm-commits
llvm-commits at lists.llvm.org
Wed Sep 30 01:05:10 PDT 2026
https://github.com/artagnon updated https://github.com/llvm/llvm-project/pull/219559
>From 3740d9a53bc11017a91d523a4ff1a935e834417b Mon Sep 17 00:00:00 2001
From: Ramkumar Ramachandra <artagnon at tenstorrent.com>
Date: Fri, 28 Aug 2026 13:22:45 +0100
Subject: [PATCH] [SCEV] Rework IncrementWrapFlags
Re-think IncrementWrapFlags from the ground up. The fundamental insight
here is that what currently exists as nssw is fundamentally impossible
to eliminate via analysis: there is already elaborate machinery to prove
nsw, and we would only produce nssw when this fails; attempting to
eliminate it with cheaper analyses is futile.
The purpose of IncrementWrapFlags is to have SCEVExpander generate
runtime checks when our elaborate machinery for proving nuw/nsw fails:
so, we instead speculate that a weaker properties nusw and nsuw could
hold, and insert runtime-checks. This entire setup would generate poor
code if we speculated a property that's either provably true or false.
As a result, we have exactly three cases:
- nusw (existing case): useless when the start of the AR is provably
negative. We can attempt to eliminate this case with analysis, and
emit runtime-checks for it as-is treating the start as signed and the
step as unsigned, if it survives until expansion.
- nsuw (new case): useless when the step of the AR is provably negative.
We can attempt to eliminate this case with analysis, and
emit runtime-checks for it as-is treating the start as unsigned and
the step as signed, if it survives until expansion.
- irreducible (replaces nssw): a fundamentally irreducible fallback
case, for which runtime-checks are emitted as-is treating both the
start and step as signed.
Implication proofs: https://alive2.llvm.org/ce/z/7qe3GS
Expansion proof: https://alive2.llvm.org/ce/z/dcok4D
---
llvm/include/llvm/Analysis/ScalarEvolution.h | 49 +++++---
.../Utils/ScalarEvolutionExpander.h | 3 +-
llvm/lib/Analysis/ScalarEvolution.cpp | 108 ++++++++----------
.../Utils/ScalarEvolutionExpander.cpp | 42 ++++---
.../inbounds-gep-in-predicated-blocks.ll | 15 +--
...invariant-dep-with-backedge-taken-count.ll | 2 +-
...e-implied.ll => nsuw-predicate-implied.ll} | 24 ++--
.../LoopAccessAnalysis/symbolic-stride.ll | 34 +++---
.../wrapping-pointer-versioning.ll | 6 +-
.../ScalarEvolution/exit-count-non-strict.ll | 20 ++--
.../ScalarEvolution/finite-trip-count.ll | 6 +-
.../Analysis/ScalarEvolution/ne-overflow.ll | 18 +--
.../test/Analysis/ScalarEvolution/pr117133.ll | 6 +-
.../ScalarEvolution/predicated-trip-count.ll | 11 +-
.../trip-count-implied-addrec.ll | 6 +-
.../LoopVectorize/AArch64/bounded-load.ll | 4 +-
.../LoopVectorize/AArch64/induction-costs.ll | 2 +-
.../RISCV/riscv-vector-reverse.ll | 8 +-
.../runtime-check-dependent-on-stride.ll | 2 +-
.../LoopVectorize/RISCV/strided-accesses.ll | 8 +-
.../LoopVectorize/X86/multi-exit-cost.ll | 4 +-
.../Transforms/LoopVectorize/X86/pr35432.ll | 2 +-
.../LoopVectorize/bounded-load-multi-exit.ll | 4 +-
...irst-order-recurrence-dead-instructions.ll | 58 ++--------
.../Transforms/LoopVectorize/induction.ll | 38 +++---
.../pr30654-phiscev-sext-trunc.ll | 13 ++-
llvm/test/Transforms/LoopVectorize/pr33706.ll | 2 +-
.../runtime-checks-difference.ll | 12 +-
.../LoopVectorize/scev-check-unknown-prof.ll | 30 +++--
.../wrapping-pointer-versioning.ll | 6 +-
30 files changed, 258 insertions(+), 285 deletions(-)
rename llvm/test/Analysis/LoopAccessAnalysis/{nssw-predicate-implied.ll => nsuw-predicate-implied.ll} (96%)
diff --git a/llvm/include/llvm/Analysis/ScalarEvolution.h b/llvm/include/llvm/Analysis/ScalarEvolution.h
index 4d9f0247ef640..91021933a9bcd 100644
--- a/llvm/include/llvm/Analysis/ScalarEvolution.h
+++ b/llvm/include/llvm/Analysis/ScalarEvolution.h
@@ -479,7 +479,7 @@ class LLVM_ABI SCEVComparePredicate final : public SCEVPredicate {
};
/// This class represents an assumption made on an AddRec expression. Given an
-/// affine AddRec expression {a,+,b}, we assume that it has the nssw or nusw
+/// affine AddRec expression {a,+,b}, we assume that it has the nsuw or nusw
/// flags (defined below) in the first X iterations of the loop, where X is a
/// SCEV expression returned by getPredicatedBackedgeTakenCount).
///
@@ -490,11 +490,18 @@ class LLVM_ABI SCEVComparePredicate final : public SCEVPredicate {
/// have more than X iterations.
class LLVM_ABI SCEVWrapPredicate final : public SCEVPredicate {
public:
- /// Similar to SCEVFlags, but with slightly different semantics
- /// for FlagNUSW. The increment is considered to be signed, and a + b
- /// (where b is the increment) is considered to wrap if:
+ /// IncrementNUSW and IncrementNSUW are the two primary reduced-case increment
+ /// wrap-flags. They are useful to reason about in AddRec expressions of the
+ /// form {Start, +, Step}.
+ ///
+ /// For NUSW, the increment is considered to be signed,
+ /// and a + b (where b is the increment) is considered to wrap if:
/// zext(a + b) != zext(a) + sext(b)
///
+ /// For NSUW, the increment is considered to be unsigned,
+ /// and a + b (where b is the increment) is considered to wrap if:
+ /// sext(a + b) != sext(a) + zext(b)
+ ///
/// If Signed is a function that takes an n-bit tuple and maps to the
/// integer domain as the tuples value interpreted as twos complement,
/// and Unsigned a function that takes an n-bit tuple and maps to the
@@ -503,21 +510,29 @@ class LLVM_ABI SCEVWrapPredicate final : public SCEVPredicate {
///
/// 0 <= Unsigned(a) + Signed(b) < 2^n
///
- /// The IncrementNSSW flag has identical semantics with SCEV::FlagNSW.
- ///
- /// Note that the IncrementNUSW flag is not commutative: if base + inc
- /// has IncrementNUSW, then inc + base doesn't neccessarily have this
- /// property. The reason for this is that this is used for sign/zero
- /// extending affine AddRec SCEV expressions when a SCEVWrapPredicate is
- /// assumed. A {base,+,inc} expression is already non-commutative with
- /// regards to base and inc, since it is interpreted as:
+ /// Note that NUSW/NSUW are not commutative: if base + inc has one of the
+ /// flags, then inc + base doesn't neccessarily have this property. The reason
+ /// for this is that this is used for sign/zero extending affine AddRec SCEV
+ /// expressions when a SCEVWrapPredicate is assumed. A {base,+,inc} expression
+ /// is already non-commutative with regards to base and inc, since it is
+ /// interpreted as:
/// (((base + inc) + inc) + inc) ...
+ ///
+ /// NUSW can be thought of as weaker variant of NUW, and is useless if the LHS
+ /// of the increment is provably negative. Since we only add these to AddRecs
+ /// under (zero|sign)-extending operations, our speculative zero-extend of the
+ /// LHS would not fit in the narrower type. Similarly, NSUW can be thought of
+ /// as a weaker variant of NSW, and is only useful when the RHS of the
+ /// increment is not provably negative. When the appropriate operand is
+ /// provably negative, we simply fall back to sign-extending both operands,
+ /// and mark this case as Irreducible.
enum IncrementWrapFlags {
- IncrementAnyWrap = 0, // No guarantee.
- IncrementNUSW = (1 << 0), // No unsigned with signed increment wrap.
- IncrementNSSW = (1 << 1), // No signed with signed increment wrap
- // (equivalent with SCEV::NSW)
- IncrementNoWrapMask = (1 << 2) - 1
+ IncrementAnyWrap = 0, // No guarantee.
+ IncrementNUSW = (1 << 0), // No unsigned with signed increment wrap.
+ IncrementNSUW = (1 << 1), // No signed with unsigned increment wrap.
+ IncrementIrreducible = (1 << 2), // No signed with signed increment wrap.
+ IncrementNoWrapMask = (1 << 3) - 1,
+ LLVM_MARK_AS_BITMASK_ENUM(/*LargestValue=*/IncrementNoWrapMask)
};
/// Convenient IncrementWrapFlags manipulation methods.
diff --git a/llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h b/llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
index d068037310835..e202323124bc1 100644
--- a/llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
+++ b/llvm/include/llvm/Transforms/Utils/ScalarEvolutionExpander.h
@@ -359,7 +359,8 @@ class SCEVExpander : public SCEVUseVisitor<SCEVExpander, Value *> {
/// Generates code that evaluates if the \p AR expression will overflow.
LLVM_ABI Value *generateOverflowCheck(const SCEVAddRecExpr *AR,
- Instruction *Loc, bool Signed);
+ Instruction *Loc, bool IsStartSigned,
+ bool IsStepSigned);
/// A specialized variant of expandCodeForPredicate, handling the case when
/// we are expanding code for a SCEVWrapPredicate.
diff --git a/llvm/lib/Analysis/ScalarEvolution.cpp b/llvm/lib/Analysis/ScalarEvolution.cpp
index 5b8e30985ee7f..b8867f4bafa8b 100644
--- a/llvm/lib/Analysis/ScalarEvolution.cpp
+++ b/llvm/lib/Analysis/ScalarEvolution.cpp
@@ -5558,7 +5558,7 @@ ScalarEvolution::createAddRecFromPHIWithCastsImpl(const SCEVUnknown *SymbolicPHI
// add P1.
if (const auto *AR = dyn_cast<SCEVAddRecExpr>(PHISCEV)) {
SCEVWrapPredicate::IncrementWrapFlags AddedFlags =
- Signed ? SCEVWrapPredicate::IncrementNSSW
+ Signed ? SCEVWrapPredicate::IncrementNSUW
: SCEVWrapPredicate::IncrementNUSW;
const SCEVPredicate *AddRecPred = getWrapPredicate(AR, AddedFlags);
Predicates.push_back(AddRecPred);
@@ -5600,9 +5600,8 @@ ScalarEvolution::createAddRecFromPHIWithCastsImpl(const SCEVUnknown *SymbolicPHI
return std::nullopt;
}
- // The Step is always Signed (because the overflow checks are either
- // NSSW or NUSW)
- const SCEV *AccumExtended = getExtendedExpr(Accum, /*CreateSignExtend=*/true);
+ // The Step is unsigned in the case of nsuw, and signed in the case of nusw.
+ const SCEV *AccumExtended = getExtendedExpr(Accum, !Signed);
if (PredIsKnownFalse(Accum, AccumExtended)) {
LLVM_DEBUG(dbgs() << "P3 is compile-time false\n";);
return std::nullopt;
@@ -15300,13 +15299,20 @@ class SCEVPredicateRewriter : public SCEVRewriteVisitor<SCEVPredicateRewriter> {
const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(Operand);
if (AR && AR->getLoop() == L && AR->isAffine()) {
// This couldn't be folded because the operand didn't have the nuw
- // flag. Add the nusw flag as an assumption that we could make.
+ // flag. Add the nusw flag, falling back to irreducible, as an assumption
+ // that we could make.
const SCEV *Step = AR->getStepRecurrence(SE);
Type *Ty = Expr->getType();
- if (addOverflowAssumption(AR, SCEVWrapPredicate::IncrementNUSW))
+ if (!SE.isKnownNegative(AR->getStart()) &&
+ addOverflowAssumption(AR, SCEVWrapPredicate::IncrementNUSW)) {
return SE.getAddRecExpr(SE.getZeroExtendExpr(AR->getStart(), Ty),
SE.getSignExtendExpr(Step, Ty), L,
AR->getNoWrapFlags());
+ }
+ if (addOverflowAssumption(AR, SCEVWrapPredicate::IncrementIrreducible))
+ return SE.getAddRecExpr(SE.getSignExtendExpr(AR->getStart(), Ty),
+ SE.getSignExtendExpr(Step, Ty), L,
+ AR->getNoWrapFlags());
}
return SE.getZeroExtendExpr(Operand, Expr->getType());
}
@@ -15316,10 +15322,17 @@ class SCEVPredicateRewriter : public SCEVRewriteVisitor<SCEVPredicateRewriter> {
const SCEVAddRecExpr *AR = dyn_cast<SCEVAddRecExpr>(Operand);
if (AR && AR->getLoop() == L && AR->isAffine()) {
// This couldn't be folded because the operand didn't have the nsw
- // flag. Add the nssw flag as an assumption that we could make.
+ // flag. Add the nsuw flag, falling back to irreducible, as an assumption
+ // that we could make.
const SCEV *Step = AR->getStepRecurrence(SE);
Type *Ty = Expr->getType();
- if (addOverflowAssumption(AR, SCEVWrapPredicate::IncrementNSSW))
+ if (!SE.isKnownNegative(Step) &&
+ addOverflowAssumption(AR, SCEVWrapPredicate::IncrementNSUW)) {
+ return SE.getAddRecExpr(SE.getSignExtendExpr(AR->getStart(), Ty),
+ SE.getZeroExtendExpr(Step, Ty), L,
+ AR->getNoWrapFlags());
+ }
+ if (addOverflowAssumption(AR, SCEVWrapPredicate::IncrementIrreducible))
return SE.getAddRecExpr(SE.getSignExtendExpr(AR->getStart(), Ty),
SE.getSignExtendExpr(Step, Ty), L,
AR->getNoWrapFlags());
@@ -15393,39 +15406,13 @@ const SCEVAddRecExpr *ScalarEvolution::convertSCEVToAddRecWithPredicates(
SmallVectorImpl<const SCEVPredicate *> &Preds) {
SmallVector<const SCEVPredicate *> TransformPreds;
S = SCEVPredicateRewriter::rewrite(S, L, *this, &TransformPreds, nullptr);
- auto *AddRec = dyn_cast<SCEVAddRecExpr>(S);
-
- if (!AddRec)
- return nullptr;
-
- // Check if any of the transformed predicates is known to be false. In that
- // case, it doesn't make sense to convert to a predicated AddRec, as the
- // versioned loop will never execute.
- for (const SCEVPredicate *Pred : TransformPreds) {
- auto *WrapPred = dyn_cast<SCEVWrapPredicate>(Pred);
- if (!WrapPred || WrapPred->getFlags() != SCEVWrapPredicate::IncrementNSSW)
- continue;
-
- const SCEVAddRecExpr *AddRecToCheck = WrapPred->getExpr();
- const SCEV *ExitCount = getBackedgeTakenCount(AddRecToCheck->getLoop());
- if (isa<SCEVCouldNotCompute>(ExitCount))
- continue;
-
- const SCEV *Step = AddRecToCheck->getStepRecurrence(*this);
- if (!Step->isOne())
- continue;
-
- ExitCount = getTruncateOrSignExtend(ExitCount, Step->getType());
- const SCEV *Add = getAddExpr(AddRecToCheck->getStart(), ExitCount);
- if (isKnownPredicate(CmpInst::ICMP_SLT, Add, AddRecToCheck->getStart()))
- return nullptr;
+ if (auto *AddRec = dyn_cast<SCEVAddRecExpr>(S)) {
+ // Since the transformation was successful, we can now transfer the SCEV
+ // predicates.
+ append_range(Preds, TransformPreds);
+ return AddRec;
}
-
- // Since the transformation was successful, we can now transfer the SCEV
- // predicates.
- Preds.append(TransformPreds.begin(), TransformPreds.end());
-
- return AddRec;
+ return nullptr;
}
/// SCEV predicates
@@ -15481,8 +15468,7 @@ bool SCEVWrapPredicate::implies(const SCEVPredicate *N,
if (Op->AR == AR)
return true;
- if (Flags != SCEVWrapPredicate::IncrementNSSW &&
- Flags != SCEVWrapPredicate::IncrementNUSW)
+ if (Flags == SCEVWrapPredicate::IncrementAnyWrap)
return false;
const SCEV *Start = AR->getStart();
@@ -15494,31 +15480,35 @@ bool SCEVWrapPredicate::implies(const SCEVPredicate *N,
if (Start->getType()->isPointerTy() && Start->getType() != OpStart->getType())
return false;
- // NUSW/NSSW on a wider-type AddRec does not imply the same on a
+ // NUSW/NSUW on a wider-type AddRec does not imply the same on a
// narrower-type AddRec.
if (SE.getTypeSizeInBits(AR->getType()) >
SE.getTypeSizeInBits(Op->AR->getType()))
return false;
+ bool IsStepSigned = is_contained({SCEVWrapPredicate::IncrementNUSW,
+ SCEVWrapPredicate::IncrementIrreducible},
+ Flags);
const SCEV *Step = AR->getStepRecurrence(SE);
const SCEV *OpStep = Op->AR->getStepRecurrence(SE);
- if (!SE.isKnownPositive(Step) || !SE.isKnownPositive(OpStep))
+ if (IsStepSigned &&
+ (!SE.isKnownNonNegative(Step) || !SE.isKnownNonNegative(OpStep)))
return false;
- // If both steps are positive, this implies N, if N's start and step are
- // ULE/SLE (for NSUW/NSSW) than this'.
+ bool IsStartSigned = is_contained({SCEVWrapPredicate::IncrementNSUW,
+ SCEVWrapPredicate::IncrementIrreducible},
+ Flags);
Type *WiderTy = SE.getWiderType(Step->getType(), OpStep->getType());
Step = SE.getNoopOrZeroExtend(Step, WiderTy);
- OpStep = SE.getNoopOrZeroExtend(OpStep, WiderTy);
+ Start = IsStartSigned ? SE.getNoopOrSignExtend(Start, WiderTy)
+ : SE.getNoopOrZeroExtend(Start, WiderTy);
- bool IsNUW = Flags == SCEVWrapPredicate::IncrementNUSW;
- OpStart = IsNUW ? SE.getNoopOrZeroExtend(OpStart, WiderTy)
- : SE.getNoopOrSignExtend(OpStart, WiderTy);
- Start = IsNUW ? SE.getNoopOrZeroExtend(Start, WiderTy)
- : SE.getNoopOrSignExtend(Start, WiderTy);
- CmpInst::Predicate Pred = IsNUW ? CmpInst::ICMP_ULE : CmpInst::ICMP_SLE;
- return SE.isKnownPredicate(Pred, OpStep, Step) &&
- SE.isKnownPredicate(Pred, OpStart, Start);
+ return SE.isKnownPredicate(IsStartSigned ? CmpInst::ICMP_SLE
+ : CmpInst::ICMP_ULE,
+ OpStart, Start) &&
+ SE.isKnownPredicate(IsStepSigned ? CmpInst::ICMP_SLE
+ : CmpInst::ICMP_ULE,
+ OpStep, Step);
}
bool SCEVWrapPredicate::isAlwaysTrue() const {
@@ -15526,7 +15516,7 @@ bool SCEVWrapPredicate::isAlwaysTrue() const {
IncrementWrapFlags IFlags = Flags;
if (ScalarEvolution::setFlags(ScevFlags, SCEV::FlagNSW) == ScevFlags)
- IFlags = clearFlags(IFlags, IncrementNSSW);
+ IFlags = clearFlags(IFlags, IncrementIrreducible);
return IFlags == IncrementAnyWrap;
}
@@ -15535,8 +15525,10 @@ void SCEVWrapPredicate::print(raw_ostream &OS, unsigned Depth) const {
OS.indent(Depth) << *getExpr() << " Added Flags: ";
if (SCEVWrapPredicate::IncrementNUSW & getFlags())
OS << "<nusw>";
- if (SCEVWrapPredicate::IncrementNSSW & getFlags())
- OS << "<nssw>";
+ if (SCEVWrapPredicate::IncrementNSUW & getFlags())
+ OS << "<nsuw>";
+ if (SCEVWrapPredicate::IncrementIrreducible & getFlags())
+ OS << "<irr>";
OS << "\n";
}
diff --git a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
index d8ad13994ca2a..32e4f99661748 100644
--- a/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
+++ b/llvm/lib/Transforms/Utils/ScalarEvolutionExpander.cpp
@@ -2302,7 +2302,8 @@ Value *SCEVExpander::expandComparePredicate(const SCEVComparePredicate *Pred,
}
Value *SCEVExpander::generateOverflowCheck(const SCEVAddRecExpr *AR,
- Instruction *Loc, bool Signed) {
+ Instruction *Loc, bool IsStartSigned,
+ bool IsStepSigned) {
assert(AR->isAffine() && "Cannot generate RT check for "
"non-affine expression");
@@ -2320,7 +2321,7 @@ Value *SCEVExpander::generateOverflowCheck(const SCEVAddRecExpr *AR,
unsigned SrcBits = SE.getTypeSizeInBits(ExitCount->getType());
unsigned DstBits = SE.getTypeSizeInBits(ARTy);
- // The expression {Start,+,Step} has nusw/nssw if
+ // The expression {Start,+,Step} has nusw/nusw if
// Step < 0, Start - |Step| * Backedge <= Start
// Step >= 0, Start + |Step| * Backedge > Start
// and |Step| * Backedge doesn't unsigned overflow.
@@ -2395,10 +2396,12 @@ Value *SCEVExpander::generateOverflowCheck(const SCEVAddRecExpr *AR,
Value *EndCheck = nullptr;
if (NeedPosCheck)
EndCheck = EndCompareLT = Builder.CreateICmp(
- Signed ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT, Add, StartValue);
+ IsStartSigned ? ICmpInst::ICMP_SLT : ICmpInst::ICMP_ULT, Add,
+ StartValue);
if (NeedNegCheck)
EndCheck = EndCompareGT = Builder.CreateICmp(
- Signed ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT, Sub, StartValue);
+ IsStepSigned ? ICmpInst::ICMP_SGT : ICmpInst::ICMP_UGT, Sub,
+ StartValue);
if (NeedPosCheck && NeedNegCheck) {
// Select the answer based on the sign of Step.
EndCheck = Builder.CreateSelectWithUnknownProfile(
@@ -2428,24 +2431,35 @@ Value *SCEVExpander::generateOverflowCheck(const SCEVAddRecExpr *AR,
Value *SCEVExpander::expandWrapPredicate(const SCEVWrapPredicate *Pred,
Instruction *IP) {
const auto *A = cast<SCEVAddRecExpr>(Pred->getExpr());
- Value *NSSWCheck = nullptr, *NUSWCheck = nullptr;
+ Value *NSUWCheck = nullptr, *NUSWCheck = nullptr;
- // Add a check for NUSW
+ // Add a check for NUSW.
if (Pred->getFlags() & SCEVWrapPredicate::IncrementNUSW)
- NUSWCheck = generateOverflowCheck(A, IP, false);
+ NUSWCheck = generateOverflowCheck(A, IP, /*IsStartSigned=*/false,
+ /*IsStepSigned=*/true);
- // Add a check for NSSW
- if (Pred->getFlags() & SCEVWrapPredicate::IncrementNSSW)
- NSSWCheck = generateOverflowCheck(A, IP, true);
+ // Add a check for NSUW.
+ if (Pred->getFlags() & SCEVWrapPredicate::IncrementNSUW)
+ NSUWCheck = generateOverflowCheck(A, IP, /*IsStartSigned=*/true,
+ /*IsStepSigned=*/false);
- if (NUSWCheck && NSSWCheck)
- return Builder.CreateOr(NUSWCheck, NSSWCheck);
+ // Add a check for Irreducible.
+ if (Pred->getFlags() & SCEVWrapPredicate::IncrementIrreducible) {
+ assert(!(Pred->getFlags() & (SCEVWrapPredicate::IncrementNUSW |
+ SCEVWrapPredicate::IncrementNSUW)) &&
+ "Irreducible wrap-flag expected to be set independently");
+ return generateOverflowCheck(A, IP, /*IsStartSigned=*/true,
+ /*IsStepSigned=*/true);
+ }
+
+ if (NUSWCheck && NSUWCheck)
+ return Builder.CreateOr(NUSWCheck, NSUWCheck);
if (NUSWCheck)
return NUSWCheck;
- if (NSSWCheck)
- return NSSWCheck;
+ if (NSUWCheck)
+ return NSUWCheck;
return ConstantInt::getFalse(IP->getContext());
}
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/inbounds-gep-in-predicated-blocks.ll b/llvm/test/Analysis/LoopAccessAnalysis/inbounds-gep-in-predicated-blocks.ll
index aeaf59c7aea44..ecd5e2538ddd5 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/inbounds-gep-in-predicated-blocks.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/inbounds-gep-in-predicated-blocks.ll
@@ -168,28 +168,23 @@ exit:
define i32 @test_nusw_gep_with_load_user_outside_loop(ptr %A) {
; CHECK-LABEL: 'test_nusw_gep_with_load_user_outside_loop'
; CHECK-NEXT: loop.header:
-; CHECK-NEXT: Report: unsafe dependent memory operations in loop. Use #pragma clang loop distribute(enable) to allow loop distribution to attempt to isolate the offending operations into a separate loop
-; CHECK-NEXT: Unknown data dependence.
+; CHECK-NEXT: Memory dependences are safe
; CHECK-NEXT: Dependences:
-; CHECK-NEXT: Unknown:
-; CHECK-NEXT: store i32 0, ptr %A, align 4 ->
-; CHECK-NEXT: store i32 0, ptr %gep, align 4
-; CHECK-EMPTY:
; CHECK-NEXT: Run-time memory checks:
; CHECK-NEXT: Grouped accesses:
; CHECK-NEXT: Group GRP0:
-; CHECK-NEXT: (Low: (-392 + %A) High: (8 + %A))
-; CHECK-NEXT: Member: {(4 + %A),+,-4}<nw><%loop.header>
+; CHECK-NEXT: (Low: (-400 + %A) High: (4 + %A))
+; CHECK-NEXT: Member: {(-4 + %A),+,-4}<nw><%loop.header>
; CHECK-NEXT: Member: %A
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {true,+,true}<%loop.header> Added Flags: <nusw>
+; CHECK-NEXT: {true,+,true}<%loop.header> Added Flags: <irr>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep = getelementptr nusw i32, ptr %A, i64 %and:
; CHECK-NEXT: ((4 * (zext i1 {true,+,true}<%loop.header> to i64))<nuw><nsw> + %A)
-; CHECK-NEXT: --> {(4 + %A),+,-4}<nw><%loop.header>
+; CHECK-NEXT: --> {(-4 + %A),+,-4}<nw><%loop.header>
;
entry:
br label %loop.header
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/loop-invariant-dep-with-backedge-taken-count.ll b/llvm/test/Analysis/LoopAccessAnalysis/loop-invariant-dep-with-backedge-taken-count.ll
index 8328591a3c7f4..f9f0eb7b52b6a 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/loop-invariant-dep-with-backedge-taken-count.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/loop-invariant-dep-with-backedge-taken-count.ll
@@ -190,7 +190,7 @@ define void @test_btc_is_unknown_value(ptr %a, i32 %N) {
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,1}<nuw><%loop> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,1}<nuw><%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep = getelementptr i32, ptr %a, i32 %iv:
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll b/llvm/test/Analysis/LoopAccessAnalysis/nsuw-predicate-implied.ll
similarity index 96%
rename from llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
rename to llvm/test/Analysis/LoopAccessAnalysis/nsuw-predicate-implied.ll
index 2cd487f71f068..32bd73b291668 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/nssw-predicate-implied.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/nsuw-predicate-implied.ll
@@ -25,7 +25,7 @@ define void @wrap_check_iv.3_implies_iv.2(i32 noundef %N, ptr %dst, ptr %src) {
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
@@ -80,7 +80,7 @@ define void @wrap_check_iv.3_implies_iv.2_different_start(i32 noundef %N, ptr %d
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {2,+,2}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {2,+,2}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
@@ -135,7 +135,7 @@ define void @wrap_check_iv.3_implies_iv.2_predicates_added_in_different_order(i3
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.iv.3 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.3:
@@ -189,8 +189,8 @@ define void @wrap_check_iv.3_does_not_implies_iv.2_due_to_start(i32 noundef %N,
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nssw>
-; CHECK-NEXT: {10,+,2}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,3}<%loop> Added Flags: <nsuw>
+; CHECK-NEXT: {10,+,2}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
@@ -244,8 +244,8 @@ define void @wrap_check_iv.3_does_not_imply_iv.2_due_to_start_negative(i32 nound
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {-1,+,3}<%loop> Added Flags: <nssw>
-; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {-1,+,3}<%loop> Added Flags: <nsuw>
+; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
@@ -299,8 +299,8 @@ define void @wrap_check_iv.3_does_not_imply_iv.2_due_to_negative_step(i32 nounde
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,-1}<%loop> Added Flags: <nssw>
-; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,-1}<%loop> Added Flags: <irr>
+; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.iv.2 = getelementptr inbounds i32, ptr %src, i64 %ext.iv.2:
@@ -357,8 +357,8 @@ define void @wider_i32_nssw_does_not_imply_narrower_i8_nssw(ptr %dst, ptr %src,
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
; CHECK-NEXT: Equal predicate: (zext i1 (trunc i32 %N to i1) to i32) == 0
-; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
-; CHECK-NEXT: {0,+,1}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nsuw>
+; CHECK-NEXT: {0,+,1}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.dst = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.1:
@@ -411,7 +411,7 @@ define void @narrower_i8_nssw_implies_wider_i32_nssw(ptr %dst, ptr %src, i32 %N)
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.dst = getelementptr inbounds i32, ptr %dst, i64 %ext.iv.1:
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/symbolic-stride.ll b/llvm/test/Analysis/LoopAccessAnalysis/symbolic-stride.ll
index f4aff75582c02..6585bd60f1320 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/symbolic-stride.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/symbolic-stride.ll
@@ -470,17 +470,17 @@ define void @unknown_stride_equalto_tc(i32 %N, ptr %A, ptr %B, i32 %j) {
; CHECK-NEXT: (Low: %A High: (4 + %A))
; CHECK-NEXT: Member: %A
; CHECK-NEXT: Group GRP1:
-; CHECK-NEXT: (Low: (((2 * (sext i32 %j to i64))<nsw> + %B) umin ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + %N) to i64) * (sext i32 %N to i64)) + %B)) High: (2 + (((2 * (sext i32 %j to i64))<nsw> + %B) umax ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + %N) to i64) * (sext i32 %N to i64)) + %B))))
-; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i32 %N to i64))<nsw>}<%loop>
+; CHECK-NEXT: (Low: ((2 * (sext i32 %j to i64))<nsw> + %B) High: (2 + (2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + %N) to i64) * (zext i32 %N to i64)) + %B))
+; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i32 %N to i64))<nuw><nsw>}<%loop>
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {%j,+,%N}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {%j,+,%N}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %arrayidx = getelementptr inbounds i16, ptr %B, i32 %add:
; CHECK-NEXT: ((2 * (sext i32 {%j,+,%N}<%loop> to i64))<nsw> + %B)
-; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i32 %N to i64))<nsw>}<%loop>
+; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i32 %N to i64))<nuw><nsw>}<%loop>
;
entry:
%cmp = icmp eq i32 %N, 0
@@ -526,7 +526,7 @@ define void @unknown_stride_equalto_zext_tc(i16 zeroext %N, ptr %A, ptr %B, i32
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {%j,+,(zext i16 %N to i32)}<nw><%loop> Added Flags: <nssw>
+; CHECK-NEXT: {%j,+,(zext i16 %N to i32)}<nw><%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %arrayidx = getelementptr inbounds i16, ptr %B, i32 %add:
@@ -572,17 +572,17 @@ define void @unknown_stride_equalto_sext_tc(i16 %N, ptr %A, ptr %B, i32 %j) {
; CHECK-NEXT: (Low: %A High: (4 + %A))
; CHECK-NEXT: Member: %A
; CHECK-NEXT: Group GRP1:
-; CHECK-NEXT: (Low: (((2 * (sext i32 %j to i64))<nsw> + %B) umin ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + (sext i16 %N to i32))<nsw> to i64) * (sext i16 %N to i64)) + %B)) High: (2 + (((2 * (sext i32 %j to i64))<nsw> + %B) umax ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + (sext i16 %N to i32))<nsw> to i64) * (sext i16 %N to i64)) + %B))))
-; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i16 %N to i64))<nsw>}<nw><%loop>
+; CHECK-NEXT: (Low: ((2 * (sext i32 %j to i64))<nsw> + %B) High: (2 + (2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (sext i16 %N to i32) to i64) * (zext i32 (-1 + (sext i16 %N to i32))<nsw> to i64)) + %B))
+; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i32 (sext i16 %N to i32) to i64))<nuw><nsw>}<%loop>
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {%j,+,(sext i16 %N to i32)}<nw><%loop> Added Flags: <nssw>
+; CHECK-NEXT: {%j,+,(sext i16 %N to i32)}<nw><%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %arrayidx = getelementptr inbounds i16, ptr %B, i32 %add:
; CHECK-NEXT: ((2 * (sext i32 {%j,+,(sext i16 %N to i32)}<nw><%loop> to i64))<nsw> + %B)
-; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i16 %N to i64))<nsw>}<nw><%loop>
+; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i32 (sext i16 %N to i32) to i64))<nuw><nsw>}<%loop>
;
entry:
%N.ext = sext i16 %N to i32
@@ -623,17 +623,17 @@ define void @unknown_stride_equalto_trunc_tc(i64 %N, ptr %A, ptr %B, i32 %j) {
; CHECK-NEXT: (Low: %A High: (4 + %A))
; CHECK-NEXT: Member: %A
; CHECK-NEXT: Group GRP1:
-; CHECK-NEXT: (Low: (((2 * (sext i32 %j to i64))<nsw> + %B) umin ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + (trunc i64 %N to i32)) to i64) * (sext i32 (trunc i64 %N to i32) to i64)) + %B)) High: (2 + (((2 * (sext i32 %j to i64))<nsw> + %B) umax ((2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (-1 + (trunc i64 %N to i32)) to i64) * (sext i32 (trunc i64 %N to i32) to i64)) + %B))))
-; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i32 (trunc i64 %N to i32) to i64))<nsw>}<%loop>
+; CHECK-NEXT: (Low: ((2 * (sext i32 %j to i64))<nsw> + %B) High: (2 + (2 * (sext i32 %j to i64))<nsw> + (2 * (zext i32 (trunc i64 %N to i32) to i64) * (zext i32 (-1 + (trunc i64 %N to i32)) to i64)) + %B))
+; CHECK-NEXT: Member: {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i32 (trunc i64 %N to i32) to i64))<nuw><nsw>}<%loop>
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {%j,+,(trunc i64 %N to i32)}<nw><%loop> Added Flags: <nssw>
+; CHECK-NEXT: {%j,+,(trunc i64 %N to i32)}<nw><%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %arrayidx = getelementptr inbounds i16, ptr %B, i32 %add:
; CHECK-NEXT: ((2 * (sext i32 {%j,+,(trunc i64 %N to i32)}<nw><%loop> to i64))<nsw> + %B)
-; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (sext i32 (trunc i64 %N to i32) to i64))<nsw>}<%loop>
+; CHECK-NEXT: --> {((2 * (sext i32 %j to i64))<nsw> + %B),+,(2 * (zext i32 (trunc i64 %N to i32) to i64))<nuw><nsw>}<%loop>
;
entry:
%N.trunc = trunc i64 %N to i32
@@ -883,20 +883,20 @@ define void @single_stride_scaled_inside_and_outside_cast(ptr %A, i32 %N, i32 %s
; CHECK-NEXT: Run-time memory checks:
; CHECK-NEXT: Grouped accesses:
; CHECK-NEXT: Group GRP0:
-; CHECK-NEXT: (Low: (((4 * (zext i32 (-1 + %N) to i64) * (sext i32 (16 * %stride) to i64)) + %A) umin %A) High: (4 + (((4 * (zext i32 (-1 + %N) to i64) * (sext i32 (16 * %stride) to i64)) + %A) umax %A)))
-; CHECK-NEXT: Member: {%A,+,(4 * (sext i32 (16 * %stride) to i64))<nsw>}<%loop>
+; CHECK-NEXT: (Low: %A High: (4 + (4 * (zext i32 (-1 + %N) to i64) * (zext i32 (16 * %stride) to i64)) + %A))
+; CHECK-NEXT: Member: {%A,+,(4 * (zext i32 (16 * %stride) to i64))<nuw><nsw>}<%loop>
; CHECK-NEXT: Group GRP1:
; CHECK-NEXT: (Low: (4 + %A)<nuw> High: (8 + (4 * (zext i32 (-1 + %N) to i64))<nuw><nsw> + %A))
; CHECK-NEXT: Member: {(4 + %A)<nuw>,+,4}<nuw><%loop>
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,(16 * %stride)}<%loop> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,(16 * %stride)}<%loop> Added Flags: <nsuw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %gep.A = getelementptr inbounds i32, ptr %A, i64 %mul.ext:
; CHECK-NEXT: ((4 * (sext i32 {0,+,(16 * %stride)}<%loop> to i64))<nsw> + %A)
-; CHECK-NEXT: --> {%A,+,(4 * (sext i32 (16 * %stride) to i64))<nsw>}<%loop>
+; CHECK-NEXT: --> {%A,+,(4 * (zext i32 (16 * %stride) to i64))<nuw><nsw>}<%loop>
;
entry:
%s16 = mul i32 %stride, 16
diff --git a/llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll b/llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll
index 71c20bc2b2a82..7f530ac3a4477 100644
--- a/llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll
+++ b/llvm/test/Analysis/LoopAccessAnalysis/wrapping-pointer-versioning.ll
@@ -175,7 +175,7 @@ define void @f3(ptr noalias %a, ptr noalias %b, i64 %N) {
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: {%a,+,4}<%for.body> Added Flags: <nusw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
@@ -232,7 +232,7 @@ define void @f4(ptr noalias %a, ptr noalias %b, i64 %N) {
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {(2 * (trunc i64 %N to i32)),+,-2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {(2 * (trunc i64 %N to i32)),+,-2}<%for.body> Added Flags: <irr>
; CHECK-NEXT: {((2 * (sext i32 (2 * (trunc i64 %N to i32)) to i64))<nsw> + %a),+,-4}<%for.body> Added Flags: <nusw>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
@@ -292,7 +292,7 @@ define void @f5(ptr noalias %a, ptr noalias %b, i64 %N) {
; CHECK-EMPTY:
; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop.
; CHECK-NEXT: SCEV assumptions:
-; CHECK-NEXT: {(2 * (trunc i64 %N to i32)),+,-2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {(2 * (trunc i64 %N to i32)),+,-2}<%for.body> Added Flags: <irr>
; CHECK-EMPTY:
; CHECK-NEXT: Expressions re-written:
; CHECK-NEXT: [PSE] %arrayidxA = getelementptr inbounds i16, ptr %a, i32 %mul:
diff --git a/llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll b/llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll
index 023f51265d08e..cf1b0c218280d 100644
--- a/llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll
+++ b/llvm/test/Analysis/ScalarEvolution/exit-count-non-strict.ll
@@ -445,28 +445,28 @@ define void @le_from_int_min_no_nuw_nsw(i32 %M, i32 %N) {
; CHECK-NEXT: Determining loop execution counts for: @le_from_int_min_no_nuw_nsw
; CHECK-NEXT: Loop %loop: <multiple exits> Unpredictable backedge-taken count.
; CHECK-NEXT: exit count for loop: ***COULDNOTCOMPUTE***
-; CHECK-NEXT: predicated exit count for loop: (-2147483648 + (2147483648 umax (1 + (zext i32 %M to i64))<nuw><nsw>))<nsw>
+; CHECK-NEXT: predicated exit count for loop: i64 0
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <nusw>
+; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <irr>
; CHECK-EMPTY:
; CHECK-NEXT: exit count for latch: (-2147483648 + %N)
; CHECK-NEXT: Loop %loop: constant max backedge-taken count is i32 -1
; CHECK-NEXT: Loop %loop: symbolic max backedge-taken count is (-2147483648 + %N)
; CHECK-NEXT: symbolic max exit count for loop: ***COULDNOTCOMPUTE***
-; CHECK-NEXT: predicated symbolic max exit count for loop: (-2147483648 + (2147483648 umax (1 + (zext i32 %M to i64))<nuw><nsw>))<nsw>
+; CHECK-NEXT: predicated symbolic max exit count for loop: i64 0
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <nusw>
+; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <irr>
; CHECK-EMPTY:
; CHECK-NEXT: symbolic max exit count for latch: (-2147483648 + %N)
-; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is ((-2147483648 + (2147483648 umax (1 + (zext i32 %M to i64))<nuw><nsw>))<nsw> umin_seq (zext i32 (-2147483648 + %N) to i64))
+; CHECK-NEXT: Loop %loop: Predicated backedge-taken count is i64 0
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <nusw>
-; CHECK-NEXT: Loop %loop: Predicated constant max backedge-taken count is i64 2147483648
+; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <irr>
+; CHECK-NEXT: Loop %loop: Predicated constant max backedge-taken count is i64 0
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <nusw>
-; CHECK-NEXT: Loop %loop: Predicated symbolic max backedge-taken count is ((-2147483648 + (2147483648 umax (1 + (zext i32 %M to i64))<nuw><nsw>))<nsw> umin_seq (zext i32 (-2147483648 + %N) to i64))
+; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <irr>
+; CHECK-NEXT: Loop %loop: Predicated symbolic max backedge-taken count is i64 0
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <nusw>
+; CHECK-NEXT: {-2147483648,+,1}<nsw><%loop> Added Flags: <irr>
;
entry:
br label %loop
diff --git a/llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll b/llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll
index a1538fd78ba17..d51f4e66fd88e 100644
--- a/llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll
+++ b/llvm/test/Analysis/ScalarEvolution/finite-trip-count.ll
@@ -58,13 +58,13 @@ define void @sle_pre_inc_infinite(i32 %len) {
; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count.
; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (0 smax (1 + (sext i32 %len to i64))<nsw>)
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,1}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,1}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Loop %for.body: Predicated constant max backedge-taken count is i64 2147483648
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,1}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,1}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Loop %for.body: Predicated symbolic max backedge-taken count is (0 smax (1 + (sext i32 %len to i64))<nsw>)
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,1}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,1}<%for.body> Added Flags: <nsuw>
;
entry:
br label %for.body
diff --git a/llvm/test/Analysis/ScalarEvolution/ne-overflow.ll b/llvm/test/Analysis/ScalarEvolution/ne-overflow.ll
index bb97005e8faf4..d2e06d78fe7e9 100644
--- a/llvm/test/Analysis/ScalarEvolution/ne-overflow.ll
+++ b/llvm/test/Analysis/ScalarEvolution/ne-overflow.ll
@@ -319,15 +319,15 @@ define void @test_sext(i64 %N) mustprogress {
; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count.
; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (%N /u 2)
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Equal predicate: (zext i1 (trunc i64 %N to i1) to i64) == 0
; CHECK-NEXT: Loop %for.body: Predicated constant max backedge-taken count is i64 9223372036854775807
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Equal predicate: (zext i1 (trunc i64 %N to i1) to i64) == 0
; CHECK-NEXT: Loop %for.body: Predicated symbolic max backedge-taken count is (%N /u 2)
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Equal predicate: (zext i1 (trunc i64 %N to i1) to i64) == 0
;
entry:
@@ -352,17 +352,17 @@ define void @test_zext_of_sext(i64 %N) mustprogress {
; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count.
; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (%N /u 2)
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nusw>
; CHECK-NEXT: Equal predicate: (zext i1 (trunc i64 %N to i1) to i64) == 0
; CHECK-NEXT: Loop %for.body: Predicated constant max backedge-taken count is i64 9223372036854775807
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nusw>
; CHECK-NEXT: Equal predicate: (zext i1 (trunc i64 %N to i1) to i64) == 0
; CHECK-NEXT: Loop %for.body: Predicated symbolic max backedge-taken count is (%N /u 2)
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nusw>
; CHECK-NEXT: Equal predicate: (zext i1 (trunc i64 %N to i1) to i64) == 0
;
@@ -423,15 +423,15 @@ define void @test_sext_offset(i64 %N) mustprogress {
; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count.
; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is ((-21 + %N) /u 2)
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Equal predicate: (zext i1 (true + (trunc i64 %N to i1)) to i64) == 0
; CHECK-NEXT: Loop %for.body: Predicated constant max backedge-taken count is i64 9223372036854775807
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Equal predicate: (zext i1 (true + (trunc i64 %N to i1)) to i64) == 0
; CHECK-NEXT: Loop %for.body: Predicated symbolic max backedge-taken count is ((-21 + %N) /u 2)
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,2}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Equal predicate: (zext i1 (true + (trunc i64 %N to i1)) to i64) == 0
;
entry:
diff --git a/llvm/test/Analysis/ScalarEvolution/pr117133.ll b/llvm/test/Analysis/ScalarEvolution/pr117133.ll
index 3aadc18d6157c..85dd138cea624 100644
--- a/llvm/test/Analysis/ScalarEvolution/pr117133.ll
+++ b/llvm/test/Analysis/ScalarEvolution/pr117133.ll
@@ -72,13 +72,13 @@ define i64 @test_poisonous(i64 %a, i32 %n) {
; CHECK-NEXT: Loop %loop.body: Unpredictable symbolic max backedge-taken count.
; CHECK-NEXT: Loop %loop.body: Predicated backedge-taken count is (-1 + (1 smax (1 + (sext i32 %n to i64))<nsw>))<nsw>
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {1,+,1}<%loop.body> Added Flags: <nssw>
+; CHECK-NEXT: {1,+,1}<%loop.body> Added Flags: <nsuw>
; CHECK-NEXT: Loop %loop.body: Predicated constant max backedge-taken count is i64 2147483647
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {1,+,1}<%loop.body> Added Flags: <nssw>
+; CHECK-NEXT: {1,+,1}<%loop.body> Added Flags: <nsuw>
; CHECK-NEXT: Loop %loop.body: Predicated symbolic max backedge-taken count is (-1 + (1 smax (1 + (sext i32 %n to i64))<nsw>))<nsw>
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {1,+,1}<%loop.body> Added Flags: <nssw>
+; CHECK-NEXT: {1,+,1}<%loop.body> Added Flags: <nsuw>
;
entry:
br label %loop.body
diff --git a/llvm/test/Analysis/ScalarEvolution/predicated-trip-count.ll b/llvm/test/Analysis/ScalarEvolution/predicated-trip-count.ll
index 72f3c11d9c853..2393c559eeec7 100644
--- a/llvm/test/Analysis/ScalarEvolution/predicated-trip-count.ll
+++ b/llvm/test/Analysis/ScalarEvolution/predicated-trip-count.ll
@@ -35,7 +35,13 @@ define void @test1(i32 %N, i32 %M) {
; CHECK-NEXT: Loop %bb3: Unpredictable symbolic max backedge-taken count.
; CHECK-NEXT: Loop %bb3: Predicated backedge-taken count is (1 + (-1 smax %M))
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {0,+,1}<%bb3> Added Flags: <nssw>
+; CHECK-NEXT: {0,+,1}<%bb3> Added Flags: <nsuw>
+; CHECK-NEXT: Loop %bb3: Predicated constant max backedge-taken count is i32 -2147483648
+; CHECK-NEXT: Predicates:
+; CHECK-NEXT: {0,+,1}<%bb3> Added Flags: <nsuw>
+; CHECK-NEXT: Loop %bb3: Predicated symbolic max backedge-taken count is (1 + (-1 smax %M))
+; CHECK-NEXT: Predicates:
+; CHECK-NEXT: {0,+,1}<%bb3> Added Flags: <nsuw>
;
entry:
br label %bb3
@@ -100,9 +106,6 @@ define void @test2(i32 %N, i32 %M, i16 %Start) {
; CHECK-NEXT: Loop %bb3: Unpredictable backedge-taken count.
; CHECK-NEXT: Loop %bb3: Unpredictable constant max backedge-taken count.
; CHECK-NEXT: Loop %bb3: Unpredictable symbolic max backedge-taken count.
-; CHECK-NEXT: Loop %bb3: Predicated backedge-taken count is (1 + (sext i16 %Start to i32) + (-1 * ((1 + (sext i16 %Start to i32))<nsw> smin %M)))
-; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {%Start,+,-1}<%bb3> Added Flags: <nssw>
;
entry:
br label %bb3
diff --git a/llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll b/llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll
index 2ee2ec53f6c9e..20ae1911064fa 100644
--- a/llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll
+++ b/llvm/test/Analysis/ScalarEvolution/trip-count-implied-addrec.ll
@@ -60,13 +60,13 @@ define void @nw_implies_nsw(i16 %n) mustprogress {
; CHECK-NEXT: Loop %for.body: Unpredictable symbolic max backedge-taken count.
; CHECK-NEXT: Loop %for.body: Predicated backedge-taken count is (128 + (-128 smax %n))
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {-128,+,1}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {-128,+,1}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Loop %for.body: Predicated constant max backedge-taken count is i16 -32641
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {-128,+,1}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {-128,+,1}<%for.body> Added Flags: <nsuw>
; CHECK-NEXT: Loop %for.body: Predicated symbolic max backedge-taken count is (128 + (-128 smax %n))
; CHECK-NEXT: Predicates:
-; CHECK-NEXT: {-128,+,1}<%for.body> Added Flags: <nssw>
+; CHECK-NEXT: {-128,+,1}<%for.body> Added Flags: <nsuw>
;
entry:
br label %for.body
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll b/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
index 453ff606afedb..ea2daaf59c39e 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/bounded-load.ll
@@ -11,10 +11,8 @@ define i32 @bounded_load_reduction_bound2(ptr %A, i32 %N) {
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_SCEVCHECK:.*]]
; CHECK: [[VECTOR_SCEVCHECK]]:
; CHECK-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1
-; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1
; CHECK-NEXT: [[TMP2:%.*]] = icmp ugt i32 [[TMP0]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = or i1 [[TMP1]], [[TMP2]]
-; CHECK-NEXT: br i1 [[TMP3]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK-NEXT: br i1 [[TMP2]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
; CHECK: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
index 38e50c8614eb3..158614f34f5ba 100644
--- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
+++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll
@@ -549,7 +549,7 @@ define void at sext_sub_nsw_for_address(ptr %base, i64 %n, ptr %src) #0 {
; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = sub i64 0, [[MUL_RESULT]]
; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[BASE]], i64 [[TMP14]]
-; CHECK-NEXT: [[TMP16:%.*]] = icmp ugt ptr [[TMP15]], [[BASE]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp sgt ptr [[TMP15]], [[BASE]]
; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP16]], [[MUL_OVERFLOW]]
; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP5]], [[TMP8]]
; CHECK-NEXT: [[TMP19:%.*]] = or i1 [[TMP18]], [[TMP13]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
index f4b68fcec1261..0fbfd802480bb 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll
@@ -155,7 +155,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1
; RV64-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32
; RV64-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-; RV64-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]
+; RV64-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP6]], [[TMP4]]
; RV64-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
; RV64-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP9]]
; RV64-NEXT: br i1 [[TMP8]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
@@ -271,7 +271,7 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-UF2-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1
; RV64-UF2-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32
; RV64-UF2-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-; RV64-UF2-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]
+; RV64-UF2-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP6]], [[TMP4]]
; RV64-UF2-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
; RV64-UF2-NEXT: [[TMP10:%.*]] = or i1 [[TMP7]], [[TMP9]]
; RV64-UF2-NEXT: br i1 [[TMP10]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
@@ -370,7 +370,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1
; RV64-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32
; RV64-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-; RV64-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]
+; RV64-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP6]], [[TMP4]]
; RV64-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
; RV64-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[TMP9]]
; RV64-NEXT: br i1 [[TMP8]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
@@ -486,7 +486,7 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
; RV64-UF2-NEXT: [[TMP4:%.*]] = add i32 [[N]], -1
; RV64-UF2-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP3]] to i32
; RV64-UF2-NEXT: [[TMP6:%.*]] = sub i32 [[TMP4]], [[TMP5]]
-; RV64-UF2-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], [[TMP4]]
+; RV64-UF2-NEXT: [[TMP7:%.*]] = icmp sgt i32 [[TMP6]], [[TMP4]]
; RV64-UF2-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP3]], 4294967295
; RV64-UF2-NEXT: [[TMP10:%.*]] = or i1 [[TMP7]], [[TMP9]]
; RV64-UF2-NEXT: br i1 [[TMP10]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/runtime-check-dependent-on-stride.ll b/llvm/test/Transforms/LoopVectorize/RISCV/runtime-check-dependent-on-stride.ll
index 1e508a0ebc39c..1e57bf7c5a6e8 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/runtime-check-dependent-on-stride.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/runtime-check-dependent-on-stride.ll
@@ -50,7 +50,7 @@ define void @foo(ptr %p, ptr %p.strided, i64 %n, i64 %stride) vscale_range(2, 10
; NO-UNIT-STRIDE-MV-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[MUL_RESULT]]
; NO-UNIT-STRIDE-MV-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP6]]
; NO-UNIT-STRIDE-MV-NEXT: [[TMP9:%.*]] = icmp ult ptr [[TMP7]], [[SCEVGEP]]
-; NO-UNIT-STRIDE-MV-NEXT: [[TMP10:%.*]] = icmp ugt ptr [[TMP8]], [[SCEVGEP]]
+; NO-UNIT-STRIDE-MV-NEXT: [[TMP10:%.*]] = icmp sgt ptr [[TMP8]], [[SCEVGEP]]
; NO-UNIT-STRIDE-MV-NEXT: [[TMP11:%.*]] = select i1 [[TMP4]], i1 [[TMP10]], i1 [[TMP9]]
; NO-UNIT-STRIDE-MV-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW]]
; NO-UNIT-STRIDE-MV-NEXT: br i1 [[TMP12]], label %[[SCALAR_PH:.*]], label %[[VECTOR_MEMCHECK:.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
index b7c6b498c684f..50ab78e9c9440 100644
--- a/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
+++ b/llvm/test/Transforms/LoopVectorize/RISCV/strided-accesses.ll
@@ -711,7 +711,7 @@ define void @double_stride_int_scaled(ptr %p, ptr %p2, i64 %stride) vscale_range
; STRIDED-NEXT: [[TMP29:%.*]] = getelementptr i8, ptr [[P2]], i64 [[MUL_RESULT]]
; STRIDED-NEXT: [[TMP30:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP28]]
; STRIDED-NEXT: [[TMP31:%.*]] = icmp ult ptr [[TMP29]], [[P2]]
-; STRIDED-NEXT: [[TMP32:%.*]] = icmp ugt ptr [[TMP30]], [[P2]]
+; STRIDED-NEXT: [[TMP32:%.*]] = icmp sgt ptr [[TMP30]], [[P2]]
; STRIDED-NEXT: [[TMP33:%.*]] = select i1 [[TMP26]], i1 [[TMP32]], i1 [[TMP31]]
; STRIDED-NEXT: [[TMP13:%.*]] = or i1 [[TMP33]], [[MUL_OVERFLOW]]
; STRIDED-NEXT: [[TMP34:%.*]] = icmp slt i64 [[TMP24]], 0
@@ -723,7 +723,7 @@ define void @double_stride_int_scaled(ptr %p, ptr %p2, i64 %stride) vscale_range
; STRIDED-NEXT: [[TMP35:%.*]] = getelementptr i8, ptr [[P]], i64 [[MUL_RESULT2]]
; STRIDED-NEXT: [[TMP36:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP16]]
; STRIDED-NEXT: [[TMP37:%.*]] = icmp ult ptr [[TMP35]], [[P]]
-; STRIDED-NEXT: [[TMP38:%.*]] = icmp ugt ptr [[TMP36]], [[P]]
+; STRIDED-NEXT: [[TMP38:%.*]] = icmp sgt ptr [[TMP36]], [[P]]
; STRIDED-NEXT: [[TMP39:%.*]] = select i1 [[TMP34]], i1 [[TMP38]], i1 [[TMP37]]
; STRIDED-NEXT: [[TMP40:%.*]] = or i1 [[TMP39]], [[MUL_OVERFLOW3]]
; STRIDED-NEXT: [[TMP23:%.*]] = or i1 [[TMP13]], [[TMP40]]
@@ -806,7 +806,7 @@ define void @double_stride_int_scaled(ptr %p, ptr %p2, i64 %stride) vscale_range
; STRIDED-UF2-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[P2]], i64 [[MUL_RESULT]]
; STRIDED-UF2-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[P2]], i64 [[TMP6]]
; STRIDED-UF2-NEXT: [[TMP9:%.*]] = icmp ult ptr [[TMP7]], [[P2]]
-; STRIDED-UF2-NEXT: [[TMP10:%.*]] = icmp ugt ptr [[TMP8]], [[P2]]
+; STRIDED-UF2-NEXT: [[TMP10:%.*]] = icmp sgt ptr [[TMP8]], [[P2]]
; STRIDED-UF2-NEXT: [[TMP11:%.*]] = select i1 [[TMP4]], i1 [[TMP10]], i1 [[TMP9]]
; STRIDED-UF2-NEXT: [[TMP12:%.*]] = or i1 [[TMP11]], [[MUL_OVERFLOW]]
; STRIDED-UF2-NEXT: [[TMP13:%.*]] = icmp slt i64 [[TMP2]], 0
@@ -818,7 +818,7 @@ define void @double_stride_int_scaled(ptr %p, ptr %p2, i64 %stride) vscale_range
; STRIDED-UF2-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[P]], i64 [[MUL_RESULT2]]
; STRIDED-UF2-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP15]]
; STRIDED-UF2-NEXT: [[TMP18:%.*]] = icmp ult ptr [[TMP16]], [[P]]
-; STRIDED-UF2-NEXT: [[TMP19:%.*]] = icmp ugt ptr [[TMP17]], [[P]]
+; STRIDED-UF2-NEXT: [[TMP19:%.*]] = icmp sgt ptr [[TMP17]], [[P]]
; STRIDED-UF2-NEXT: [[TMP20:%.*]] = select i1 [[TMP13]], i1 [[TMP19]], i1 [[TMP18]]
; STRIDED-UF2-NEXT: [[TMP21:%.*]] = or i1 [[TMP20]], [[MUL_OVERFLOW3]]
; STRIDED-UF2-NEXT: [[TMP22:%.*]] = or i1 [[TMP12]], [[TMP21]]
diff --git a/llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll b/llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
index e9429bb6bea7f..98750ffa6f3cb 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/multi-exit-cost.ll
@@ -15,10 +15,8 @@ define i64 @test_value_in_exit_compare_chain_used_outside(ptr %src, i64 %x, i64
; CHECK-NEXT: [[TMP3:%.*]] = add nsw i64 [[N]], -1
; CHECK-NEXT: [[TMP4:%.*]] = freeze i64 [[TMP3]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[X]])
-; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[UMIN]] to i1
; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[UMIN]], 1
-; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]
-; CHECK-NEXT: br i1 [[TMP7]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[TMP6]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP2]], 7
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
diff --git a/llvm/test/Transforms/LoopVectorize/X86/pr35432.ll b/llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
index e9a758f7b21df..15491fd99121a 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/pr35432.ll
@@ -47,7 +47,7 @@ define i32 @main(ptr %ptr) {
; CHECK-NEXT: [[TMP7:%.*]] = sub i32 [[TMP6]], [[UMIN]]
; CHECK-NEXT: [[TMP8:%.*]] = trunc i32 [[TMP7]] to i8
; CHECK-NEXT: [[TMP9:%.*]] = sub i8 [[TMP5]], [[TMP8]]
-; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i8 [[TMP9]], [[TMP5]]
+; CHECK-NEXT: [[TMP10:%.*]] = icmp sgt i8 [[TMP9]], [[TMP5]]
; CHECK-NEXT: [[TMP12:%.*]] = icmp ugt i32 [[TMP7]], 255
; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP10]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[DOTPROMOTED]], 1
diff --git a/llvm/test/Transforms/LoopVectorize/bounded-load-multi-exit.ll b/llvm/test/Transforms/LoopVectorize/bounded-load-multi-exit.ll
index 3e703f78cbe18..d9aac846a6171 100644
--- a/llvm/test/Transforms/LoopVectorize/bounded-load-multi-exit.ll
+++ b/llvm/test/Transforms/LoopVectorize/bounded-load-multi-exit.ll
@@ -15,10 +15,8 @@ define i64 @bounded_load_multi_exit(ptr %src, i64 %x, i64 %N) {
; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[N]], -1
; CHECK-NEXT: [[TMP4:%.*]] = freeze i64 [[TMP3]]
; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[TMP4]], i64 [[X]])
-; CHECK-NEXT: [[TMP5:%.*]] = trunc i64 [[UMIN]] to i1
; CHECK-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[UMIN]], 1
-; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]
-; CHECK-NEXT: br i1 [[TMP7]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
+; CHECK-NEXT: br i1 [[TMP6]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP2]], 7
; CHECK-NEXT: [[TMP8:%.*]] = icmp eq i64 [[N_MOD_VF]], 0
diff --git a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
index db6aa937120c3..ca04f6115342c 100644
--- a/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
+++ b/llvm/test/Transforms/LoopVectorize/first-order-recurrence-dead-instructions.ll
@@ -5,59 +5,17 @@
define i8 @recurrence_phi_with_same_incoming_values_after_simplifications(i8 %for.start, ptr %dst) {
; CHECK-LABEL: define i8 @recurrence_phi_with_same_incoming_values_after_simplifications(
; CHECK-SAME: i8 [[FOR_START:%.*]], ptr [[DST:%.*]]) {
-; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: br label %[[VECTOR_PH:.*]]
-; CHECK: [[VECTOR_PH]]:
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i8> poison, i8 [[FOR_START]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLATINSERT]], <4 x i8> poison, <4 x i32> zeroinitializer
-; CHECK-NEXT: [[TMP0:%.*]] = shufflevector <4 x i8> [[BROADCAST_SPLAT]], <4 x i8> [[BROADCAST_SPLAT]], <4 x i32> <i32 3, i32 4, i32 5, i32 6>
-; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
-; CHECK: [[VECTOR_BODY]]:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
-; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i32 1, [[INDEX]]
-; CHECK-NEXT: [[TMP2:%.*]] = add i32 [[OFFSET_IDX]], 1
-; CHECK-NEXT: [[TMP3:%.*]] = add i32 [[OFFSET_IDX]], 2
-; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[OFFSET_IDX]], 3
-; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[OFFSET_IDX]], 4
-; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[OFFSET_IDX]], 5
-; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[OFFSET_IDX]], 6
-; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[OFFSET_IDX]], 7
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP2]]
-; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP3]]
-; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP4]]
-; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP5]]
-; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP6]]
-; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP7]]
-; CHECK-NEXT: [[TMP16:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[TMP8]]
-; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i8> [[TMP0]], i64 0
-; CHECK-NEXT: store i8 [[TMP17]], ptr [[TMP9]], align 1
-; CHECK-NEXT: [[TMP18:%.*]] = extractelement <4 x i8> [[TMP0]], i64 1
-; CHECK-NEXT: store i8 [[TMP18]], ptr [[TMP10]], align 1
-; CHECK-NEXT: [[TMP19:%.*]] = extractelement <4 x i8> [[TMP0]], i64 2
-; CHECK-NEXT: store i8 [[TMP19]], ptr [[TMP11]], align 1
-; CHECK-NEXT: [[TMP20:%.*]] = extractelement <4 x i8> [[TMP0]], i64 3
-; CHECK-NEXT: store i8 [[TMP20]], ptr [[TMP12]], align 1
-; CHECK-NEXT: store i8 [[TMP17]], ptr [[TMP13]], align 1
-; CHECK-NEXT: store i8 [[TMP18]], ptr [[TMP14]], align 1
-; CHECK-NEXT: store i8 [[TMP19]], ptr [[TMP15]], align 1
-; CHECK-NEXT: store i8 [[TMP20]], ptr [[TMP16]], align 1
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
-; CHECK-NEXT: [[TMP21:%.*]] = icmp eq i32 [[INDEX_NEXT]], -8
-; CHECK-NEXT: br i1 [[TMP21]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: [[MIDDLE_BLOCK]]:
-; CHECK-NEXT: br label %[[SCALAR_PH:.*]]
-; CHECK: [[SCALAR_PH]]:
+; CHECK-NEXT: [[SCALAR_PH:.*]]:
; CHECK-NEXT: br label %[[LOOP:.*]]
; CHECK: [[LOOP]]:
-; CHECK-NEXT: [[IV:%.*]] = phi i32 [ -7, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
+; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 1, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[FOR:%.*]] = phi i8 [ [[FOR_START]], %[[SCALAR_PH]] ], [ [[FOR_NEXT:%.*]], %[[LOOP]] ]
; CHECK-NEXT: [[FOR_NEXT]] = and i8 [[FOR_START]], -1
; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
; CHECK-NEXT: [[GEP_DST:%.*]] = getelementptr inbounds i8, ptr [[DST]], i32 [[IV]]
; CHECK-NEXT: store i8 [[FOR]], ptr [[GEP_DST]], align 1
; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_NEXT]], 0
-; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
+; CHECK-NEXT: br i1 [[EC]], label %[[EXIT:.*]], label %[[LOOP]]
; CHECK: [[EXIT]]:
; CHECK-NEXT: [[FOR_NEXT_LCSSA:%.*]] = phi i8 [ [[FOR_NEXT]], %[[LOOP]] ]
; CHECK-NEXT: ret i8 [[FOR_NEXT_LCSSA]]
@@ -100,7 +58,7 @@ define i32 @sink_after_dead_inst(ptr %A.ptr) {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[STEP_ADD]], splat (i16 4)
; CHECK-NEXT: [[TMP6:%.*]] = icmp eq i32 [[INDEX_NEXT]], 16
-; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP6]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP7:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1)
; CHECK-NEXT: [[TMP4:%.*]] = or <4 x i16> [[TMP7]], [[TMP7]]
@@ -164,7 +122,7 @@ define void @sink_dead_inst(ptr %a) {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[STEP_ADD]], splat (i16 4)
; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i32 [[INDEX_NEXT]], 40
-; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP12]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP2:%.*]] = zext <4 x i16> [[TMP1]] to <4 x i32>
; CHECK-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i16> [[TMP4]], i64 3
@@ -183,7 +141,7 @@ define void @sink_dead_inst(ptr %a) {
; CHECK-NEXT: [[REC_1_PREV]] = add i16 [[IV_NEXT]], 5
; CHECK-NEXT: [[GEP:%.*]] = getelementptr i16, ptr [[A]], i16 [[IV]]
; CHECK-NEXT: store i16 [[USE_REC_1]], ptr [[GEP]], align 2
-; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_END:.*]], label %[[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_END:.*]], label %[[FOR_COND]], !llvm.loop [[LOOP4:![0-9]+]]
; CHECK: [[FOR_END]]:
; CHECK-NEXT: ret void
;
@@ -223,7 +181,7 @@ define void @unused_recurrence(ptr %a) {
; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 8
; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i16> [[STEP_ADD]], splat (i16 4)
; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1024
-; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]]
+; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK-NEXT: [[TMP3:%.*]] = add <4 x i16> [[STEP_ADD]], splat (i16 1)
; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i16> [[TMP3]], splat (i16 5)
@@ -238,7 +196,7 @@ define void @unused_recurrence(ptr %a) {
; CHECK-NEXT: [[IV_NEXT]] = add i16 [[IV]], 1
; CHECK-NEXT: [[REC_1_PREV]] = add i16 [[IV_NEXT]], 5
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i16 [[IV]], 1000
-; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_END:.*]], label %[[FOR_COND]], !llvm.loop [[LOOP8:![0-9]+]]
+; CHECK-NEXT: br i1 [[CMP]], label %[[FOR_END:.*]], label %[[FOR_COND]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: [[FOR_END]]:
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LoopVectorize/induction.ll b/llvm/test/Transforms/LoopVectorize/induction.ll
index 193011f56e229..e04e9579d3688 100644
--- a/llvm/test/Transforms/LoopVectorize/induction.ll
+++ b/llvm/test/Transforms/LoopVectorize/induction.ll
@@ -5924,14 +5924,14 @@ define void @test_optimized_cast_induction_feeding_first_order_recurrence(i64 %n
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
; CHECK-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]
; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i8 [[MUL_RESULT]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i8 [[TMP6]], 0
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i8 [[TMP6]], 0
; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP3]], i1 [[TMP8]], i1 [[TMP7]]
; CHECK-NEXT: [[TMP10:%.*]] = or i1 [[TMP9]], [[MUL_OVERFLOW]]
; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[TMP0]], 255
; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP1]], 0
; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = sext i8 [[TMP1]] to i32
+; CHECK-NEXT: [[TMP15:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP15]]
; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP14]], [[IDENT_CHECK]]
; CHECK-NEXT: br i1 [[TMP16]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
@@ -5996,16 +5996,16 @@ define void @test_optimized_cast_induction_feeding_first_order_recurrence(i64 %n
; IND-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP3]], i8 [[TMP4]])
; IND-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
; IND-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
-; IND-NEXT: [[TMP20:%.*]] = sub i8 0, [[MUL_RESULT]]
+; IND-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]
; IND-NEXT: [[TMP5:%.*]] = icmp slt i8 [[MUL_RESULT]], 0
-; IND-NEXT: [[TMP6:%.*]] = icmp sgt i8 [[TMP20]], 0
-; IND-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 [[TMP5]]
-; IND-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]
+; IND-NEXT: [[TMP20:%.*]] = icmp ugt i8 [[TMP6]], 0
+; IND-NEXT: [[TMP22:%.*]] = select i1 [[TMP2]], i1 [[TMP20]], i1 [[TMP5]]
+; IND-NEXT: [[TMP8:%.*]] = or i1 [[TMP22]], [[MUL_OVERFLOW]]
; IND-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP0]], 255
; IND-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP1]], 0
; IND-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]]
; IND-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]]
-; IND-NEXT: [[TMP21:%.*]] = sext i8 [[TMP1]] to i32
+; IND-NEXT: [[TMP21:%.*]] = zext i8 [[TMP1]] to i32
; IND-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP21]]
; IND-NEXT: [[TMP14:%.*]] = or i1 [[TMP12]], [[IDENT_CHECK]]
; IND-NEXT: br i1 [[TMP14]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
@@ -6070,16 +6070,16 @@ define void @test_optimized_cast_induction_feeding_first_order_recurrence(i64 %n
; UNROLL-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP3]], i8 [[TMP4]])
; UNROLL-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
; UNROLL-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
-; UNROLL-NEXT: [[TMP23:%.*]] = sub i8 0, [[MUL_RESULT]]
+; UNROLL-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]
; UNROLL-NEXT: [[TMP5:%.*]] = icmp slt i8 [[MUL_RESULT]], 0
-; UNROLL-NEXT: [[TMP6:%.*]] = icmp sgt i8 [[TMP23]], 0
-; UNROLL-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 [[TMP5]]
-; UNROLL-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]
+; UNROLL-NEXT: [[TMP23:%.*]] = icmp ugt i8 [[TMP6]], 0
+; UNROLL-NEXT: [[TMP24:%.*]] = select i1 [[TMP2]], i1 [[TMP23]], i1 [[TMP5]]
+; UNROLL-NEXT: [[TMP8:%.*]] = or i1 [[TMP24]], [[MUL_OVERFLOW]]
; UNROLL-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP0]], 255
; UNROLL-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP1]], 0
; UNROLL-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]]
; UNROLL-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]]
-; UNROLL-NEXT: [[TMP15:%.*]] = sext i8 [[TMP1]] to i32
+; UNROLL-NEXT: [[TMP15:%.*]] = zext i8 [[TMP1]] to i32
; UNROLL-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP15]]
; UNROLL-NEXT: [[TMP14:%.*]] = or i1 [[TMP12]], [[IDENT_CHECK]]
; UNROLL-NEXT: br i1 [[TMP14]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
@@ -6148,14 +6148,14 @@ define void @test_optimized_cast_induction_feeding_first_order_recurrence(i64 %n
; UNROLL-NO-IC-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
; UNROLL-NO-IC-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]
; UNROLL-NO-IC-NEXT: [[TMP7:%.*]] = icmp slt i8 [[MUL_RESULT]], 0
-; UNROLL-NO-IC-NEXT: [[TMP8:%.*]] = icmp sgt i8 [[TMP6]], 0
+; UNROLL-NO-IC-NEXT: [[TMP8:%.*]] = icmp ugt i8 [[TMP6]], 0
; UNROLL-NO-IC-NEXT: [[TMP9:%.*]] = select i1 [[TMP3]], i1 [[TMP8]], i1 [[TMP7]]
; UNROLL-NO-IC-NEXT: [[TMP10:%.*]] = or i1 [[TMP9]], [[MUL_OVERFLOW]]
; UNROLL-NO-IC-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[TMP0]], 255
; UNROLL-NO-IC-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP1]], 0
; UNROLL-NO-IC-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]
; UNROLL-NO-IC-NEXT: [[TMP14:%.*]] = or i1 [[TMP10]], [[TMP13]]
-; UNROLL-NO-IC-NEXT: [[TMP15:%.*]] = sext i8 [[TMP1]] to i32
+; UNROLL-NO-IC-NEXT: [[TMP15:%.*]] = zext i8 [[TMP1]] to i32
; UNROLL-NO-IC-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP15]]
; UNROLL-NO-IC-NEXT: [[TMP16:%.*]] = or i1 [[TMP14]], [[IDENT_CHECK]]
; UNROLL-NO-IC-NEXT: br i1 [[TMP16]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
@@ -6222,16 +6222,16 @@ define void @test_optimized_cast_induction_feeding_first_order_recurrence(i64 %n
; INTERLEAVE-NEXT: [[MUL:%.*]] = call { i8, i1 } @llvm.umul.with.overflow.i8(i8 [[TMP3]], i8 [[TMP4]])
; INTERLEAVE-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
; INTERLEAVE-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
-; INTERLEAVE-NEXT: [[TMP23:%.*]] = sub i8 0, [[MUL_RESULT]]
+; INTERLEAVE-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]
; INTERLEAVE-NEXT: [[TMP5:%.*]] = icmp slt i8 [[MUL_RESULT]], 0
-; INTERLEAVE-NEXT: [[TMP6:%.*]] = icmp sgt i8 [[TMP23]], 0
-; INTERLEAVE-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 [[TMP5]]
-; INTERLEAVE-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]]
+; INTERLEAVE-NEXT: [[TMP23:%.*]] = icmp ugt i8 [[TMP6]], 0
+; INTERLEAVE-NEXT: [[TMP24:%.*]] = select i1 [[TMP2]], i1 [[TMP23]], i1 [[TMP5]]
+; INTERLEAVE-NEXT: [[TMP8:%.*]] = or i1 [[TMP24]], [[MUL_OVERFLOW]]
; INTERLEAVE-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[TMP0]], 255
; INTERLEAVE-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP1]], 0
; INTERLEAVE-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]]
; INTERLEAVE-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]]
-; INTERLEAVE-NEXT: [[TMP15:%.*]] = sext i8 [[TMP1]] to i32
+; INTERLEAVE-NEXT: [[TMP15:%.*]] = zext i8 [[TMP1]] to i32
; INTERLEAVE-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP15]]
; INTERLEAVE-NEXT: [[TMP14:%.*]] = or i1 [[TMP12]], [[IDENT_CHECK]]
; INTERLEAVE-NEXT: br i1 [[TMP14]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
diff --git a/llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll b/llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
index 1d19e85c1c1d3..6a315c4c2e034 100644
--- a/llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
+++ b/llvm/test/Transforms/LoopVectorize/pr30654-phiscev-sext-trunc.ll
@@ -52,14 +52,14 @@ define void @doit1(i32 %n, i32 %step) {
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
; CHECK-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]
; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i8 [[MUL_RESULT]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = icmp sgt i8 [[TMP6]], 0
+; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i8 [[TMP6]], 0
; CHECK-NEXT: [[TMP9:%.*]] = select i1 [[TMP3]], i1 [[TMP8]], i1 [[TMP7]]
; CHECK-NEXT: [[TMP10:%.*]] = or i1 [[TMP9]], [[MUL_OVERFLOW]]
; CHECK-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[TMP0]], 255
; CHECK-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP1]], 0
; CHECK-NEXT: [[TMP13:%.*]] = and i1 [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP10]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = sext i8 [[TMP1]] to i32
+; CHECK-NEXT: [[TMP15:%.*]] = zext i8 [[TMP1]] to i32
; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[STEP]], [[TMP15]]
; CHECK-NEXT: [[TMP16:%.*]] = or i1 [[TMP14]], [[IDENT_CHECK]]
; CHECK-NEXT: br i1 [[TMP16]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
@@ -171,7 +171,7 @@ define void @doit2(i32 %n, i32 %step) {
; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i8, i1 } [[MUL]], 0
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
; CHECK-NEXT: [[TMP6:%.*]] = sub i8 0, [[MUL_RESULT]]
-; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i8 [[TMP6]], 0
+; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i8 [[TMP6]], 0
; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP3]], i1 [[TMP7]], i1 false
; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]
; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP0]], 255
@@ -364,14 +364,17 @@ define void @doit4(i32 %n, i8 signext %cstep) {
; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i8, i1 } [[MUL]], 1
; CHECK-NEXT: [[TMP5:%.*]] = sub i8 0, [[MUL_RESULT]]
; CHECK-NEXT: [[TMP6:%.*]] = icmp slt i8 [[MUL_RESULT]], 0
-; CHECK-NEXT: [[TMP7:%.*]] = icmp sgt i8 [[TMP5]], 0
+; CHECK-NEXT: [[TMP7:%.*]] = icmp ugt i8 [[TMP5]], 0
; CHECK-NEXT: [[TMP8:%.*]] = select i1 [[TMP2]], i1 [[TMP7]], i1 [[TMP6]]
; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]]
; CHECK-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[TMP0]], 255
; CHECK-NEXT: [[TMP11:%.*]] = icmp ne i8 [[CSTEP]], 0
; CHECK-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]]
; CHECK-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]]
-; CHECK-NEXT: br i1 [[TMP13]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
+; CHECK-NEXT: [[TMP14:%.*]] = zext i8 [[CSTEP]] to i32
+; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[CONV]], [[TMP14]]
+; CHECK-NEXT: [[TMP18:%.*]] = or i1 [[TMP13]], [[IDENT_CHECK]]
+; CHECK-NEXT: br i1 [[TMP18]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[WIDE_TRIP_COUNT]], 3
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[WIDE_TRIP_COUNT]], [[N_MOD_VF]]
diff --git a/llvm/test/Transforms/LoopVectorize/pr33706.ll b/llvm/test/Transforms/LoopVectorize/pr33706.ll
index bae7d3d15c08f..83cab7a2d4f9b 100644
--- a/llvm/test/Transforms/LoopVectorize/pr33706.ll
+++ b/llvm/test/Transforms/LoopVectorize/pr33706.ll
@@ -41,7 +41,7 @@ define void @PR33706(ptr nocapture readonly %arg, ptr nocapture %arg1, i32 %arg2
; CHECK-NEXT: [[TMP12:%.*]] = add i16 [[TMP8]], [[MUL_RESULT]]
; CHECK-NEXT: [[TMP13:%.*]] = sub i16 [[TMP8]], [[MUL_RESULT]]
; CHECK-NEXT: [[TMP14:%.*]] = icmp ult i16 [[TMP12]], [[TMP8]]
-; CHECK-NEXT: [[TMP15:%.*]] = icmp ugt i16 [[TMP13]], [[TMP8]]
+; CHECK-NEXT: [[TMP15:%.*]] = icmp sgt i16 [[TMP13]], [[TMP8]]
; CHECK-NEXT: [[TMP16:%.*]] = select i1 [[TMP9]], i1 [[TMP15]], i1 [[TMP14]]
; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP16]], [[MUL_OVERFLOW]]
; CHECK-NEXT: [[TMP18:%.*]] = icmp ugt i32 [[TMP5]], 65535
diff --git a/llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll b/llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
index e816b559bffe6..7208901346c61 100644
--- a/llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
+++ b/llvm/test/Transforms/LoopVectorize/runtime-checks-difference.ll
@@ -685,14 +685,14 @@ define void @remove_diff_checks_via_guards(i32 %x, i32 %y, ptr %A) {
; CHECK-NEXT: [[SMAX:%.*]] = call i64 @llvm.smax.i64(i64 [[TMP5]], i64 0)
; CHECK-NEXT: [[TMP6:%.*]] = trunc i64 [[SMAX]] to i32
; CHECK-NEXT: [[TMP7:%.*]] = icmp slt i32 [[TMP6]], 0
-; CHECK-NEXT: [[TMP8:%.*]] = icmp ugt i64 [[SMAX]], 4294967295
-; CHECK-NEXT: [[TMP9:%.*]] = or i1 [[TMP7]], [[TMP8]]
+; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i64 [[SMAX]], 4294967295
+; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP7]], [[TMP13]]
; CHECK-NEXT: [[TMP11:%.*]] = add i32 [[OFFSET]], [[TMP6]]
; CHECK-NEXT: [[TMP12:%.*]] = icmp slt i32 [[TMP11]], [[OFFSET]]
-; CHECK-NEXT: [[TMP13:%.*]] = icmp ugt i64 [[SMAX]], 4294967295
-; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP12]], [[TMP13]]
-; CHECK-NEXT: [[TMP15:%.*]] = or i1 [[TMP9]], [[TMP14]]
-; CHECK-NEXT: br i1 [[TMP15]], [[SCALAR_PH]], [[VECTOR_MEMCHECK:label %.*]]
+; CHECK-NEXT: [[TMP16:%.*]] = icmp ugt i64 [[SMAX]], 4294967295
+; CHECK-NEXT: [[TMP14:%.*]] = or i1 [[TMP12]], [[TMP16]]
+; CHECK-NEXT: [[TMP17:%.*]] = or i1 [[TMP15]], [[TMP14]]
+; CHECK-NEXT: br i1 [[TMP17]], [[SCALAR_PH]], [[VECTOR_PH:label %.*]]
;
entry:
%offset = sub i32 %x, %y
diff --git a/llvm/test/Transforms/LoopVectorize/scev-check-unknown-prof.ll b/llvm/test/Transforms/LoopVectorize/scev-check-unknown-prof.ll
index f2d2f13a39a6b..3ed3fa3868a6e 100644
--- a/llvm/test/Transforms/LoopVectorize/scev-check-unknown-prof.ll
+++ b/llvm/test/Transforms/LoopVectorize/scev-check-unknown-prof.ll
@@ -16,12 +16,12 @@ define void @wrap_check(i32 %n, i32 %step) !prof !0 {
; CHECK: br i1 [[TMP16:%.*]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK: [[VECTOR_BODY:.*]]:
-; CHECK: br i1 [[TMP23:%.*]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP1:![0-9]+]]
+; CHECK: br i1 [[TMP23:%.*]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP2:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK: br i1 [[CMP_N:%.*]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK: [[LOOP:.*]]:
-; CHECK: br i1 [[EC:%.*]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK: br i1 [[EC:%.*]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
; CHECK: [[EXIT_LOOPEXIT]]:
; CHECK: [[EXIT]]:
;
@@ -61,17 +61,15 @@ define void @runtime_step_memcheck(ptr %in, ptr %out, i64 %n, i64 %step) !prof !
; CHECK: [[TMP9:%.*]] = select i1 [[TMP3]], i1 [[TMP8:%.*]], i1 [[TMP7:%.*]], !prof [[PROF1]]
; CHECK: br i1 [[TMP16:%.*]], label %[[SCALAR_PH]], label %[[VECTOR_MEMCHECK:.*]]
; CHECK: [[VECTOR_MEMCHECK]]:
-; CHECK: [[UMIN:%.*]] = select i1 [[TMP23:%.*]], ptr [[IN]], ptr [[SCEVGEP1:%.*]], !prof [[PROF1]]
-; CHECK: [[UMAX:%.*]] = select i1 [[TMP24:%.*]], ptr [[IN]], ptr [[SCEVGEP1]], !prof [[PROF1]]
; CHECK: br i1 [[FOUND_CONFLICT:%.*]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK: [[VECTOR_BODY:.*]]:
-; CHECK: br i1 [[TMP47:%.*]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]]
+; CHECK: br i1 [[TMP46:%.*]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK: br i1 [[CMP_N:%.*]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK: [[LOOP:.*]]:
-; CHECK: br i1 [[EC:%.*]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP11:![0-9]+]]
+; CHECK: br i1 [[EC:%.*]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP12:![0-9]+]]
; CHECK: [[EXIT_LOOPEXIT]]:
; CHECK: [[EXIT]]:
;
@@ -113,12 +111,12 @@ define void @wrap_check_not_profiled(i32 %n, i32 %step) {
; CHECK: br i1 [[TMP16:%.*]], label %[[SCALAR_PH]], label %[[VECTOR_PH:.*]]
; CHECK: [[VECTOR_PH]]:
; CHECK: [[VECTOR_BODY:.*]]:
-; CHECK: br i1 [[TMP23:%.*]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]]
+; CHECK: br i1 [[TMP23:%.*]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP13:![0-9]+]]
; CHECK: [[MIDDLE_BLOCK]]:
; CHECK: br i1 [[CMP_N:%.*]], label %[[EXIT_LOOPEXIT:.*]], label %[[SCALAR_PH]]
; CHECK: [[SCALAR_PH]]:
; CHECK: [[LOOP:.*]]:
-; CHECK: br i1 [[EC:%.*]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP13:![0-9]+]]
+; CHECK: br i1 [[EC:%.*]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP14:![0-9]+]]
; CHECK: [[EXIT_LOOPEXIT]]:
; CHECK: [[EXIT]]:
;
@@ -150,12 +148,12 @@ exit:
;.
; CHECK: [[PROF0]] = !{!"function_entry_count", i64 1000}
; CHECK: [[PROF1]] = !{!"unknown", !"scev-expander"}
-; CHECK: [[LOOP1]] = distinct !{[[LOOP1]], [[META2:![0-9]+]], [[META3:![0-9]+]]}
-; CHECK: [[META2]] = !{!"llvm.loop.isvectorized", i32 1}
-; CHECK: [[META3]] = !{!"llvm.loop.unroll.runtime.disable"}
-; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META2]]}
-; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META2]], [[META3]]}
-; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META2]]}
-; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META2]], [[META3]]}
-; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META2]]}
+; CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[META3:![0-9]+]], [[META4:![0-9]+]]}
+; CHECK: [[META3]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK: [[META4]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META3]]}
+; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META3]], [[META4]]}
+; CHECK: [[LOOP12]] = distinct !{[[LOOP12]], [[META3]]}
+; CHECK: [[LOOP13]] = distinct !{[[LOOP13]], [[META3]], [[META4]]}
+; CHECK: [[LOOP14]] = distinct !{[[LOOP14]], [[META3]]}
;.
diff --git a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll
index d851a936969d1..cd57f186a67b2 100644
--- a/llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll
+++ b/llvm/test/Transforms/LoopVersioning/wrapping-pointer-versioning.ll
@@ -149,7 +149,7 @@ define void @f2(ptr noalias %a,
; LV-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0
; LV-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1
; LV-NEXT: [[TMP3:%.*]] = sub i32 [[TMP1]], [[MUL_RESULT]]
-; LV-NEXT: [[TMP4:%.*]] = icmp ugt i32 [[TMP3]], [[TMP1]]
+; LV-NEXT: [[TMP4:%.*]] = icmp sgt i32 [[TMP3]], [[TMP1]]
; LV-NEXT: [[TMP5:%.*]] = or i1 [[TMP4]], [[MUL_OVERFLOW]]
; LV-NEXT: [[TMP6:%.*]] = icmp ugt i64 [[TMP0]], 4294967295
; LV-NEXT: [[TMP7:%.*]] = or i1 [[TMP5]], [[TMP6]]
@@ -162,7 +162,7 @@ define void @f2(ptr noalias %a,
; LV-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
; LV-NEXT: [[TMP11:%.*]] = sub i64 0, [[MUL_RESULT3]]
; LV-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP11]]
-; LV-NEXT: [[TMP13:%.*]] = icmp ugt ptr [[TMP12]], [[SCEVGEP]]
+; LV-NEXT: [[TMP13:%.*]] = icmp sgt ptr [[TMP12]], [[SCEVGEP]]
; LV-NEXT: [[TMP14:%.*]] = or i1 [[TMP13]], [[MUL_OVERFLOW4]]
; LV-NEXT: [[TMP15:%.*]] = or i1 [[TMP7]], [[TMP14]]
; LV-NEXT: br i1 [[TMP15]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
@@ -362,7 +362,7 @@ define void @f4(ptr noalias %a,
; LV-NEXT: [[MUL_OVERFLOW4:%.*]] = extractvalue { i64, i1 } [[MUL2]], 1
; LV-NEXT: [[TMP10:%.*]] = sub i64 0, [[MUL_RESULT3]]
; LV-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[SCEVGEP]], i64 [[TMP10]]
-; LV-NEXT: [[TMP12:%.*]] = icmp ugt ptr [[TMP11]], [[SCEVGEP]]
+; LV-NEXT: [[TMP12:%.*]] = icmp sgt ptr [[TMP11]], [[SCEVGEP]]
; LV-NEXT: [[TMP13:%.*]] = or i1 [[TMP12]], [[MUL_OVERFLOW4]]
; LV-NEXT: [[TMP14:%.*]] = or i1 [[TMP7]], [[TMP13]]
; LV-NEXT: br i1 [[TMP14]], label [[FOR_BODY_PH_LVER_ORIG:%.*]], label [[FOR_BODY_PH:%.*]]
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