[llvm] [GlobalISel] [AArch64] Skip redundant shift amount masking during isel (PR #223136)

[David Green via llvm-commits]

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@@ -771,6 +769,24 @@ bool AArch64DAGToDAGISel::SelectInlineAsmMemoryOperand(
   return true;
 }
 
+template <unsigned ShiftWidth>
+bool AArch64DAGToDAGISel::SelectShiftMask(SDValue N, SDValue &ShAmt) {
+  // AArch64 shift instructions only use the low log2(ShiftWidth) bits of the
+  // shift amount. If the shift amount has a redundant AND mask that covers
+  // those bits, we can remove it. Return false if nothing was combined so
+  // other patterns (e.g. zext/sext GPR32 → SUBREG_TO_REG) can match.
+  if (N.getOpcode() == ISD::AND && isa<ConstantSDNode>(N.getOperand(1)) &&
+      N.getValueType() == (ShiftWidth == 32 ? MVT::i32 : MVT::i64)) {
+    uint64_t Mask = N.getConstantOperandVal(1);
+    // Remove AND if the mask covers the low log2(ShiftWidth) bits.
+    if ((Mask & (ShiftWidth - 1)) == (ShiftWidth - 1)) {
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davemgreen wrote:

Mask.countr_one() > ShiftWidth

https://github.com/llvm/llvm-project/pull/223136