[llvm] e6e5ade - [llvm-objdump][RISC-V] Do not leak file-level features into $x<ISA> regions (#227513)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 29 22:10:07 PDT 2026
Author: Alexander Richardson
Date: 2026-09-29T22:10:01-07:00
New Revision: e6e5ade05a9b645beb37ce1dd5142f6a923b1eae
URL: https://github.com/llvm/llvm-project/commit/e6e5ade05a9b645beb37ce1dd5142f6a923b1eae
DIFF: https://github.com/llvm/llvm-project/commit/e6e5ade05a9b645beb37ce1dd5142f6a923b1eae.diff
LOG: [llvm-objdump][RISC-V] Do not leak file-level features into $x<ISA> regions (#227513)
Previously, RISCVISATargetCache::get initialized per-region features from
Base.SubtargetInfo->getFeatureString(), which already included the
file-level Tag_RISCV_arch and --mattr flags. Because RISCVISAInfo::toFeatures()
only emits "+ext" for extensions present in the "$x<ISA>" mapping symbol
(and never "-ext"), any extension enabled in Tag_RISCV_arch or via a
conflicting --mattr remained enabled even in regions whose "$x<ISA>"
mapping symbol disabled it.
Start from an empty SubtargetFeatures instead and populate it from the
parsed "$x<ISA>" mapping symbol (plus non-conflicting --mattr flags).
This commit was created with the help of AI tools
Pull-Request: https://github.com/llvm/llvm-project/pull/227513
Added:
Modified:
llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-disassembly.s
llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-mattr-conflict.s
llvm/tools/llvm-objdump/llvm-objdump.cpp
Removed:
################################################################################
diff --git a/llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-disassembly.s b/llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-disassembly.s
index f37d45be7f2b5..05cb4177c934f 100644
--- a/llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-disassembly.s
+++ b/llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-disassembly.s
@@ -6,10 +6,10 @@
## - Second V region: verifies ISA target cache is reused correctly
## - rv32 and rv64 both exercise parseNormalizedArchString
-# RUN: llvm-mc -triple=riscv64 -mattr=+c -filetype=obj %s -o %t.64.o
+# RUN: llvm-mc -triple=riscv64 -mattr=+c -riscv-add-build-attributes -filetype=obj %s -o %t.64.o
# RUN: llvm-objdump -d --no-show-raw-insn %t.64.o | FileCheck %s
#
-# RUN: llvm-mc -triple=riscv32 -mattr=+c -filetype=obj %s -o %t.32.o
+# RUN: llvm-mc -triple=riscv32 -mattr=+c -riscv-add-build-attributes -filetype=obj %s -o %t.32.o
# RUN: llvm-objdump -d --no-show-raw-insn %t.32.o | FileCheck %s
.text
diff --git a/llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-mattr-conflict.s b/llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-mattr-conflict.s
index f1fb782f67aa5..28567e9b5a8f3 100644
--- a/llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-mattr-conflict.s
+++ b/llvm/test/tools/llvm-objdump/ELF/RISCV/mapping-sym-isa-mattr-conflict.s
@@ -10,6 +10,8 @@
# RUN: llvm-mc -filetype=obj -triple=riscv32 %s -o %t.o
# RUN: llvm-objdump -d --no-show-raw-insn --mattr=+zfinx %t.o \
# RUN: | FileCheck %s
+# RUN: llvm-objdump -d --no-show-raw-insn --mattr=+f %t.o \
+# RUN: | FileCheck %s
.text
@@ -20,3 +22,11 @@
fadd.s fa0, fa1, fa2
# CHECK: fadd.s fa0, fa1, fa2
.option pop
+
+## fadd.s in a +zfinx region. Passing --mattr=+f conflicts with +zfinx and
+## must not leak from the file-level SubtargetInfo into this region.
+.option push
+.option arch, +zfinx
+fadd.s a0, a1, a2
+# CHECK: fadd.s a0, a1, a2
+.option pop
diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp
index ed45af32fbd8f..bcc1e093c3802 100644
--- a/llvm/tools/llvm-objdump/llvm-objdump.cpp
+++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp
@@ -1448,16 +1448,13 @@ class RISCVISATargetCache {
public:
explicit RISCVISATargetCache(StringRef FileName) : FileName(FileName) {}
- // Returns a DisassemblerTarget configured for ISAStr. Feature priority in
- // the returned target is (low -> high): Tag_RISCV_arch, the mapping-symbol
- // ISA, then --mattr, so an explicit --mattr on the command line overrides
- // both the attribute-recorded arch and the mapping symbol. If appending
- // --mattr on top of the mapping symbol would create a conflicting feature
- // set (e.g. mapping symbol rv64if combined with --mattr=+zfinx), the
- // --mattr layer is dropped for this region and only the mapping symbol
- // (layered on Tag_RISCV_arch) is used. Falls back to &Base when ISAStr is
- // empty or cannot be parsed; a parse failure is cached so the same bad
- // string is consumed only once.
+ // Returns a DisassemblerTarget configured for ISAStr. A "$x<ISA>" mapping
+ // symbol specifies the full ISA for its region rather than a delta on top of
+ // Base. An explicit --mattr on the command line is layered on top unless it
+ // conflicts with the mapping symbol (e.g. mapping symbol rv64if combined with
+ // --mattr=+zfinx), in which case --mattr is dropped for this region. Falls
+ // back to &Base when ISAStr is empty or cannot be parsed; a parse failure is
+ // cached so the same bad string is consumed only once.
DisassemblerTarget *get(DisassemblerTarget &Base, StringRef ISAStr) {
if (ISAStr.empty())
return &Base;
@@ -1468,11 +1465,11 @@ class RISCVISATargetCache {
auto ParseResult = RISCVISAInfo::parseNormalizedArchString(ISAStr);
if (ParseResult) {
std::vector<std::string> ISAFeatures = (*ParseResult)->toFeatures();
- // Base's feature string already contains Tag_RISCV_arch followed by
- // --mattr. Appending the mapping-symbol features here puts the
- // mapping symbol above both; the --mattr re-layering below then puts
- // --mattr back on top as the highest-priority source.
- SubtargetFeatures Features(Base.SubtargetInfo->getFeatureString());
+ // Start from an empty feature set rather than Base: "$x<ISA>" encodes
+ // the full ISA for this region, and toFeatures() only emits "+ext" for
+ // enabled extensions, so starting from Base would keep extensions from
+ // Tag_RISCV_arch or conflicting --mattr flags enabled.
+ SubtargetFeatures Features;
// toFeatures() only emits the extensions from Exts (i, m, f, ...),
// not the base-ISA XLEN. Derive 64bit from getXLen() so mapping
// symbols that switch XLEN (e.g. rv64 inside an rv32 triple) reach
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