[llvm] [Mips][nanoMIPS] Add initial nanoMIPS target support (PR #223032)

[Faraz Shahbazker via llvm-commits]

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+//===-- NanoMipsInstrInfo.td - nanoMIPS Instr Information --*- tablegen -*-===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file describes NanoMips instructions.
+//
+//===----------------------------------------------------------------------===//
+
+//===----------------------------------------------------------------------===//
+// Mips profiles and nodes
+//===----------------------------------------------------------------------===//
+
+// TODO: Add nodes
+
+//===----------------------------------------------------------------------===//
+// nanoMIPS Operand, Complex Patterns and Transformations Definitions.
+//===----------------------------------------------------------------------===//
+
+def uimm2_nm : Operand<i32>;
+def uimm2code_nm : Operand<i32>;
+def uimm3_nm : Operand<i32>;
+def uimm3shift_nm : Operand<i32>;
+def uimm4mask_nm : Operand<i32>;
+def uimm3plus1_nm : Operand<i32>;
+def uimm5s2_nm : Operand<i32>;
+def uimm6_nm : Operand<i32>;
+def uimm8s2_nm : Operand<i32>;
+def uimm8s4_nm : Operand<i32>;
+def uimm12_nm : Operand<i32>;
+def uimm12mask_nm : Operand<i32>;
+def uimm12s3_nm : Operand<i32>;
+def uimm16_nm : Operand<i32>;
+def uimm18_nm : Operand<i32>;
+def uimm19_nm : Operand<i32>;
+def uimm5s1_nm : Operand<i32>;
+def simm22s1_nm : Operand<i32>;
+def simm32_nm : Operand<i32>;
+def simm32s12_nm : Operand<i32>;
+def simm32s12_pcrel_nm : Operand<i32>;
+def nimm7_nm : Operand<i32>;
+def nimm12_nm : Operand<i32>;
+
+def mem_nm_sp5s2 : Operand<iPTR>;
+def mem_nm_gp7s2 : Operand<iPTR>;
+def mem_nm_6s2 : Operand<iPTR>;
+def mem_nm_3s1 : Operand<iPTR>;
+def mem_nm_2 : Operand<iPTR>;
+def mem_nm_gp19s2 : Operand<iPTR>;
+def mem_nm_gp18 : Operand<iPTR>;
+def mem_nm_gp17s1 : Operand<iPTR>;
+def mem_nm_u12 : Operand<iPTR>;
+def mem_nm_s9 : Operand<iPTR>;
+def mem_nm_rx : Operand<iPTR>;
+def mem_nm_rx16 : Operand<iPTR>;
+def mem_nm_4s2 : Operand<iPTR>;
+def mem_nm_7s2 : Operand<iPTR>;
+def mem_nm_0 : Operand<iPTR>;
+def mem_nm_0_no_offset : Operand<iPTR>;
+
+def reglist16_nm : Operand<OtherVT>;
+def reglist_nm : Operand<OtherVT>;
+
+foreach I = {7, 10, 11, 14, 25} in
+  def brtarget # I # _nm : Operand<OtherVT>;
+
+def brtarget4s1_nm : Operand<OtherVT>;
+
+def calltarget21_nm : Operand<iPTR>;
+def calltarget10_nm : Operand<iPTR>;
+def calltarget25_nm : Operand<iPTR>;
+
+def sym32_pc_nm : Operand<pAny>;
+def sym32_pc22_nm : Operand<pAny>;
+def sym32_gp_nm : Operand<pAny>;
+def sym32_gp18_nm : Operand<pAny>;
+def sym32_gp19s2_nm : Operand<pAny>;
+def sym32_nm : Operand<pAny>;
+
+//===----------------------------------------------------------------------===//
+// Instruction Descriptions
+//===----------------------------------------------------------------------===//
+
+// 16-bit arithmetic and logical instructions with 4x4 register operands
+// P16_4X4
+class Arith4x4_Desc<string opstr, RegisterOperand RO>
+  : InstNM<(outs RO:$dst), (ins RO:$rt, RO:$rs),
+           !strconcat(opstr, "\t$dst, $rt, $rs")>;
+
+// 32-bit arithmetic and logical instructions with 3 register operands.
+class ArithLogicR32_Desc<string opstr, RegisterOperand RO>
+  : InstNM<(outs RO:$rd), (ins RO:$rs, RO:$rt),
+           !strconcat(opstr, "\t$rd, $rs, $rt")>;
+
+// 16-bit arithmetic and logical instructions with 2 register operands
+// POOL16C_0
+class ArithLogicR16_Desc<string opstr, RegisterOperand RO>
+  : InstNM<(outs RO:$rd), (ins RO:$rs, RO:$rt),
+           !strconcat(opstr, "\t$rd, $rs, $rt")>;
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faraz-mtk wrote:

This was deliberately to match the 3-operand format for these instructions in the nanoMIPS ISA. The ISA mentions both 3-op and 2-op format in different places. I don't have a preference, do you think it would be better to define the short format instruction and follow it up with a separate InstAlias for the long format?

https://github.com/llvm/llvm-project/pull/223032