[llvm] b7458ff - [Mips] Add lowerConstantFP to optimize some floating load instrs to mtc1+mthc1 (#196226)
via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 29 19:17:07 PDT 2026
Author: Ying Huang
Date: 2026-09-30T10:16:59+08:00
New Revision: b7458ff8580ffc6844b3e4f5035e7f3b2a212816
URL: https://github.com/llvm/llvm-project/commit/b7458ff8580ffc6844b3e4f5035e7f3b2a212816
DIFF: https://github.com/llvm/llvm-project/commit/b7458ff8580ffc6844b3e4f5035e7f3b2a212816.diff
LOG: [Mips] Add lowerConstantFP to optimize some floating load instrs to mtc1+mthc1 (#196226)
Fix #180873.
Added:
Modified:
llvm/lib/Target/Mips/MipsISelLowering.cpp
llvm/lib/Target/Mips/MipsISelLowering.h
llvm/test/CodeGen/Mips/cconv/vector.ll
llvm/test/CodeGen/Mips/fcmp.ll
llvm/test/CodeGen/Mips/fp-intrinsics.ll
llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
llvm/test/CodeGen/Mips/o32_cc.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index ffe2e40b8c5d7..dbc0e59641ba8 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -272,6 +272,9 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
setOperationAction(ISD::FCANONICALIZE, MVT::f64, Custom);
}
+ if (Subtarget.hasMTHC1())
+ setOperationAction(ISD::ConstantFP, MVT::f64, Custom);
+
if (Subtarget.isGP64bit()) {
setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
setOperationAction(ISD::BlockAddress, MVT::i64, Custom);
@@ -1268,6 +1271,8 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const
case ISD::FP_TO_SINT: return lowerFP_TO_SINT(Op, DAG);
case ISD::READCYCLECOUNTER:
return lowerREADCYCLECOUNTER(Op, DAG);
+ case ISD::ConstantFP:
+ return lowerConstantFP(Op, DAG);
}
return SDValue();
}
@@ -2100,6 +2105,41 @@ MachineBasicBlock *MipsTargetLowering::emitAtomicCmpSwapPartword(
return exitMBB;
}
+SDValue MipsTargetLowering::lowerConstantFP(SDValue Op,
+ SelectionDAG &DAG) const {
+ EVT VT = Op.getValueType();
+ ConstantFPSDNode *CFP = cast<ConstantFPSDNode>(Op);
+ const APFloat &FPVal = CFP->getValueAPF();
+
+ if (FPVal.isZero())
+ return SDValue();
+
+ SDLoc DL(CFP);
+ APInt INTVal = FPVal.bitcastToAPInt();
+ switch (VT.getSimpleVT().SimpleTy) {
+ default:
+ llvm_unreachable("Unknown floating point type!");
+ break;
+ case MVT::f64: {
+ if (!Subtarget.hasMTHC1() || !Subtarget.hasMips32r2())
+ return SDValue();
+ uint64_t Bits = INTVal.getZExtValue();
+ uint32_t Lo = Bits & 0xFFFFFFFF;
+ if (Lo != 0 || Bits == 0)
+ return SDValue();
+
+ // TODO: DAG.getConstant(0) should be optimized to avoid generate an extra
+ // instr `addiu $x, $zero, 0`.
+ SDValue Low =
+ DAG.getCopyFromReg(DAG.getEntryNode(), DL, Mips::ZERO, MVT::i32);
+ SDValue Hi = DAG.getConstant(INTVal.extractBits(32, 32), DL, MVT::i32);
+ return DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Low, Hi);
+ }
+ }
+
+ return SDValue();
+}
+
SDValue MipsTargetLowering::lowerREADCYCLECOUNTER(SDValue Op,
SelectionDAG &DAG) const {
SmallVector<SDValue, 3> Results;
diff --git a/llvm/lib/Target/Mips/MipsISelLowering.h b/llvm/lib/Target/Mips/MipsISelLowering.h
index 75604cc20aaf4..ee830859b1f6d 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.h
+++ b/llvm/lib/Target/Mips/MipsISelLowering.h
@@ -382,6 +382,7 @@ using TargetRegisterClass = MCRegisterClass;
SDValue lowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerSTRICT_FP_TO_INT(SDValue Op, SelectionDAG &DAG) const;
SDValue lowerREADCYCLECOUNTER(SDValue Op, SelectionDAG &DAG) const;
+ SDValue lowerConstantFP(SDValue Op, SelectionDAG &DAG) const;
/// isEligibleForTailCallOptimization - Check whether the call is eligible
/// for tail call optimization.
diff --git a/llvm/test/CodeGen/Mips/cconv/vector.ll b/llvm/test/CodeGen/Mips/cconv/vector.ll
index 5cd2b77615fcd..49b068e584a53 100644
--- a/llvm/test/CodeGen/Mips/cconv/vector.ll
+++ b/llvm/test/CodeGen/Mips/cconv/vector.ll
@@ -5630,8 +5630,8 @@ define <4 x float> @mixed_32(<4 x float> %a, i32 %b) {
; MIPS32R5EB-NEXT: sw $1, 4($sp)
; MIPS32R5EB-NEXT: lui $1, 17200
; MIPS32R5EB-NEXT: sw $1, 0($sp)
-; MIPS32R5EB-NEXT: lui $1, %hi($CPI41_0)
-; MIPS32R5EB-NEXT: ldc1 $f0, %lo($CPI41_0)($1)
+; MIPS32R5EB-NEXT: mtc1 $zero, $f0
+; MIPS32R5EB-NEXT: mthc1 $1, $f0
; MIPS32R5EB-NEXT: ldc1 $f1, 0($sp)
; MIPS32R5EB-NEXT: sub.d $f0, $f1, $f0
; MIPS32R5EB-NEXT: insert.w $w1[0], $6
@@ -5652,15 +5652,12 @@ define <4 x float> @mixed_32(<4 x float> %a, i32 %b) {
; MIPS64R5EB: # %bb.0: # %entry
; MIPS64R5EB-NEXT: daddiu $sp, $sp, -16
; MIPS64R5EB-NEXT: .cfi_def_cfa_offset 16
-; MIPS64R5EB-NEXT: lui $1, %hi(%neg(%gp_rel(mixed_32)))
-; MIPS64R5EB-NEXT: daddu $1, $1, $25
-; MIPS64R5EB-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(mixed_32)))
-; MIPS64R5EB-NEXT: lui $2, 17200
-; MIPS64R5EB-NEXT: sw $2, 8($sp)
+; MIPS64R5EB-NEXT: lui $1, 17200
+; MIPS64R5EB-NEXT: sw $1, 8($sp)
; MIPS64R5EB-NEXT: sll $2, $6, 0
; MIPS64R5EB-NEXT: sw $2, 12($sp)
-; MIPS64R5EB-NEXT: ld $1, %got_page(.LCPI41_0)($1)
-; MIPS64R5EB-NEXT: ldc1 $f0, %got_ofst(.LCPI41_0)($1)
+; MIPS64R5EB-NEXT: mtc1 $zero, $f0
+; MIPS64R5EB-NEXT: mthc1 $1, $f0
; MIPS64R5EB-NEXT: ldc1 $f1, 8($sp)
; MIPS64R5EB-NEXT: sub.d $f0, $f1, $f0
; MIPS64R5EB-NEXT: insert.d $w1[0], $4
@@ -5757,10 +5754,10 @@ define <4 x float> @mixed_32(<4 x float> %a, i32 %b) {
; MIPS32R5EL-NEXT: .cfi_def_cfa_offset 8
; MIPS32R5EL-NEXT: lui $1, 17200
; MIPS32R5EL-NEXT: sw $1, 4($sp)
-; MIPS32R5EL-NEXT: lw $1, 32($sp)
-; MIPS32R5EL-NEXT: sw $1, 0($sp)
-; MIPS32R5EL-NEXT: lui $1, %hi($CPI41_0)
-; MIPS32R5EL-NEXT: ldc1 $f0, %lo($CPI41_0)($1)
+; MIPS32R5EL-NEXT: lw $2, 32($sp)
+; MIPS32R5EL-NEXT: sw $2, 0($sp)
+; MIPS32R5EL-NEXT: mtc1 $zero, $f0
+; MIPS32R5EL-NEXT: mthc1 $1, $f0
; MIPS32R5EL-NEXT: ldc1 $f1, 0($sp)
; MIPS32R5EL-NEXT: sub.d $f0, $f1, $f0
; MIPS32R5EL-NEXT: insert.w $w1[0], $6
@@ -5781,15 +5778,12 @@ define <4 x float> @mixed_32(<4 x float> %a, i32 %b) {
; MIPS64R5EL: # %bb.0: # %entry
; MIPS64R5EL-NEXT: daddiu $sp, $sp, -16
; MIPS64R5EL-NEXT: .cfi_def_cfa_offset 16
-; MIPS64R5EL-NEXT: lui $1, %hi(%neg(%gp_rel(mixed_32)))
-; MIPS64R5EL-NEXT: daddu $1, $1, $25
-; MIPS64R5EL-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(mixed_32)))
-; MIPS64R5EL-NEXT: lui $2, 17200
-; MIPS64R5EL-NEXT: sw $2, 12($sp)
+; MIPS64R5EL-NEXT: lui $1, 17200
+; MIPS64R5EL-NEXT: sw $1, 12($sp)
; MIPS64R5EL-NEXT: sll $2, $6, 0
; MIPS64R5EL-NEXT: sw $2, 8($sp)
-; MIPS64R5EL-NEXT: ld $1, %got_page(.LCPI41_0)($1)
-; MIPS64R5EL-NEXT: ldc1 $f0, %got_ofst(.LCPI41_0)($1)
+; MIPS64R5EL-NEXT: mtc1 $zero, $f0
+; MIPS64R5EL-NEXT: mthc1 $1, $f0
; MIPS64R5EL-NEXT: ldc1 $f1, 8($sp)
; MIPS64R5EL-NEXT: sub.d $f0, $f1, $f0
; MIPS64R5EL-NEXT: insert.d $w1[0], $4
diff --git a/llvm/test/CodeGen/Mips/fcmp.ll b/llvm/test/CodeGen/Mips/fcmp.ll
index dc90083833c69..3edc2fda86eff 100644
--- a/llvm/test/CodeGen/Mips/fcmp.ll
+++ b/llvm/test/CodeGen/Mips/fcmp.ll
@@ -1,15 +1,15 @@
; RUN: llc < %s -mtriple=mips -mcpu=mips32 | \
-; RUN: FileCheck %s -check-prefixes=ALL,32-C
+; RUN: FileCheck %s -check-prefixes=ALL,32-C,MIPS32
; RUN: llc < %s -mtriple=mips -mcpu=mips32r2 | \
-; RUN: FileCheck %s -check-prefixes=ALL,32-C
+; RUN: FileCheck %s -check-prefixes=ALL,32-C,MIPS32R2
; RUN: llc < %s -mtriple=mips -mcpu=mips32r6 | \
; RUN: FileCheck %s -check-prefixes=ALL,32-CMP
; RUN: llc < %s -mtriple=mips64 -mcpu=mips4 | \
; RUN: FileCheck %s -check-prefixes=ALL,64-C
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64 | \
-; RUN: FileCheck %s -check-prefixes=ALL,64-C
+; RUN: FileCheck %s -check-prefixes=ALL,64-C,MIPS64
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r2 | \
-; RUN: FileCheck %s -check-prefixes=ALL,64-C
+; RUN: FileCheck %s -check-prefixes=ALL,64-C,MIPS64R2
; RUN: llc < %s -mtriple=mips64 -mcpu=mips64r6 | \
; RUN: FileCheck %s -check-prefixes=ALL,64-CMP
; RUN: llc < %s -mtriple=mips -mcpu=mips32r3 -mattr=+micromips | FileCheck %s \
@@ -1142,41 +1142,57 @@ entry:
; ALL-LABEL: bug1_f64:
; 32-C-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-C-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
+; MIPS32-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
+; MIPS32R2-DAG: lui $[[T2:[0-9]+]], 16368
+; MIPS32R2-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
+; MIPS32R2-DAG: mthc1 $[[T2]], $[[T1]]
; 32-C-DAG: c.ole.d $[[T0]], $[[T1]]
; 32-C-DAG: bc1t
-; 32-CMP-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
-; 32-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo($CPI33_0)(
-; 32-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
-; 32-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
+; 32-CMP-DAG: lui $[[T0:[0-9]+]], 16368
+; 32-CMP-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
+; 32-CMP-DAG: mthc1 $[[T0]], $[[T1]]
+; 32-CMP-DAG: add.d $[[T2:f[0-9]+]], $f14, $f12
+; 32-CMP-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T2]], $[[T1]]
+; 32-CMP-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]]
; FIXME: This instruction is redundant.
-; 32-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
-; 32-CMP-DAG: bnezc $[[T4]],
-
-; 64-C-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-C-DAG: ldc1 $[[T1:f[0-9]+]], %lo(.LCPI33_0)(
-; 64-C-DAG: c.ole.d $[[T0]], $[[T1]]
-; 64-C-DAG: bc1t
-
-; 64-CMP-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
-; 64-CMP-DAG: ldc1 $[[T1:f[0-9]+]], %lo(.LCPI33_0)(
-; 64-CMP-DAG: cmp.le.d $[[T2:f[0-9]+]], $[[T0]], $[[T1]]
-; 64-CMP-DAG: mfc1 $[[T3:[0-9]+]], $[[T2]]
+; 32-CMP-DAG: andi $[[T5:[0-9]+]], $[[T4]], 1
+; 32-CMP-DAG: bnezc $[[T5]],
+
+; MIPS64-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
+; MIPS64-DAG: ldc1 $[[T1:f[0-9]+]], %lo(.LCPI33_0)(
+; MIPS64-DAG: c.ole.d $[[T0]], $[[T1]]
+; MIPS64-DAG: bc1t
+
+; MIPS64R2-DAG: add.d $[[T0:f[0-9]+]], $f13, $f12
+; MIPS64R2-DAG: lui $[[T1:[0-9]+]], 16368
+; MIPS64R2-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; MIPS64R2-DAG: mthc1 $[[T1]], $[[T2]]
+; MIPS64R2-DAG: c.ole.d $[[T0]], $[[T2]]
+; MIPS64R2-DAG: bc1t
+
+; 64-CMP-DAG: lui $[[T0:[0-9]+]], 16368
+; 64-CMP-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
+; 64-CMP-DAG: mthc1 $[[T0]], $[[T1]]
+; 64-CMP-DAG: add.d $[[T2:f[0-9]+]], $f13, $f12
+; 64-CMP-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T2]], $[[T1]]
+; 64-CMP-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]]
; FIXME: This instruction is redundant.
-; 64-CMP-DAG: andi $[[T4:[0-9]+]], $[[T3]], 1
-; 64-CMP-DAG: bnezc $[[T4]],
+; 64-CMP-DAG: andi $[[T5:[0-9]+]], $[[T4]], 1
+; 64-CMP-DAG: bnezc $[[T5]],
; MM32R3-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
-; MM32R3-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
-; MM32R3-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
+; MM32R3-DAG: lui $[[T1:[0-9]+]], 16368
+; MM32R3-DAG: mtc1 $zero, $[[T2:f[0-9]+]]
+; MM32R3-DAG: mthc1 $[[T1]], $[[T2]]
; MM32R3-DAG: c.ole.d $[[T0]], $[[T2]]
; MM32R3-DAG: bc1t
-; MM32R6-DAG: add.d $[[T0:f[0-9]+]], $f14, $f12
-; MM32R6-DAG: lui $[[T1:[0-9]+]], %hi($CPI33_0)
-; MM32R6-DAG: ldc1 $[[T2:f[0-9]+]], %lo($CPI33_0)($[[T1]])
-; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T0]], $[[T2]]
+; MM32R6-DAG: lui $[[T0:[0-9]+]], 16368
+; MM32R6-DAG: mtc1 $zero, $[[T1:f[0-9]+]]
+; MM32R6-DAG: mthc1 $[[T0]], $[[T1]]
+; MM32R6-DAG: add.d $[[T2:f[0-9]+]], $f14, $f12
+; MM32R6-DAG: cmp.le.d $[[T3:f[0-9]+]], $[[T2]], $[[T1]]
; MM32R6-DAG: mfc1 $[[T4:[0-9]+]], $[[T3]]
; MM32R6-DAG: andi16 $[[T5:[0-9]+]], $[[T4]], 1
; MM32R6-DAG: bnezc $[[T5]],
diff --git a/llvm/test/CodeGen/Mips/fp-intrinsics.ll b/llvm/test/CodeGen/Mips/fp-intrinsics.ll
index 66f966c3e4bf6..489b1d93fb32c 100644
--- a/llvm/test/CodeGen/Mips/fp-intrinsics.ll
+++ b/llvm/test/CodeGen/Mips/fp-intrinsics.ll
@@ -164,7 +164,10 @@ define float @roundeven_f32(float %x) #0 {
define float @uitofp_f32_i32(i32 %x) #0 {
; CHECK-LABEL: uitofp_f32_i32:
-; CHECK: ldc1
+; CHECK: lui
+; CHECK: sw
+; CHECK: mtc1
+; CHECK: mthc1
; CHECK: ldc1
; CHECK: cvt.s.d
%val = call float @llvm.experimental.constrained.uitofp.f32.i32(i32 %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
@@ -467,7 +470,10 @@ define double @roundeven_f64(double %x) #0 {
define double @uitofp_f64_i32(i32 %x) #0 {
; CHECK-LABEL: uitofp_f64_i32:
-; CHECK: ldc1
+; CHECK: lui
+; CHECK: sw
+; CHECK: mtc1
+; CHECK: mthc1
; CHECK: ldc1
%val = call double @llvm.experimental.constrained.uitofp.f64.i32(i32 %x, metadata !"round.tonearest", metadata !"fpexcept.strict") #0
ret double %val
diff --git a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
index b14c88e231413..5a29f2d9d4dc5 100644
--- a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
+++ b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll
@@ -324,8 +324,8 @@ define void @uitofp(i32 %a) {
; MIPS32-NEXT: lui $2, 17200
; MIPS32-NEXT: sw $2, 4($sp)
; MIPS32-NEXT: sw $4, 0($sp)
-; MIPS32-NEXT: lw $2, %got($CPI5_0)($1)
-; MIPS32-NEXT: ldc1 $f0, %lo($CPI5_0)($2)
+; MIPS32-NEXT: mtc1 $zero, $f0
+; MIPS32-NEXT: mthc1 $2, $f0
; MIPS32-NEXT: ldc1 $f1, 0($sp)
; MIPS32-NEXT: sub.d $f0, $f1, $f0
; MIPS32-NEXT: cvt.s.d $f0, $f0
@@ -346,10 +346,10 @@ define void @uitofp(i32 %a) {
; MIPS64R5-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
; MIPS64R5-N32-NEXT: lui $2, 17200
; MIPS64R5-N32-NEXT: sw $2, 12($sp)
-; MIPS64R5-N32-NEXT: sll $2, $4, 0
-; MIPS64R5-N32-NEXT: sw $2, 8($sp)
-; MIPS64R5-N32-NEXT: lw $2, %got_page(.LCPI5_0)($1)
-; MIPS64R5-N32-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
+; MIPS64R5-N32-NEXT: sll $3, $4, 0
+; MIPS64R5-N32-NEXT: sw $3, 8($sp)
+; MIPS64R5-N32-NEXT: mtc1 $zero, $f0
+; MIPS64R5-N32-NEXT: mthc1 $2, $f0
; MIPS64R5-N32-NEXT: ldc1 $f1, 8($sp)
; MIPS64R5-N32-NEXT: sub.d $f0, $f1, $f0
; MIPS64R5-N32-NEXT: cvt.s.d $f0, $f0
@@ -370,10 +370,10 @@ define void @uitofp(i32 %a) {
; MIPS64R5-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(uitofp)))
; MIPS64R5-N64-NEXT: lui $2, 17200
; MIPS64R5-N64-NEXT: sw $2, 12($sp)
-; MIPS64R5-N64-NEXT: sll $2, $4, 0
-; MIPS64R5-N64-NEXT: sw $2, 8($sp)
-; MIPS64R5-N64-NEXT: ld $2, %got_page(.LCPI5_0)($1)
-; MIPS64R5-N64-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
+; MIPS64R5-N64-NEXT: sll $3, $4, 0
+; MIPS64R5-N64-NEXT: sw $3, 8($sp)
+; MIPS64R5-N64-NEXT: mtc1 $zero, $f0
+; MIPS64R5-N64-NEXT: mthc1 $2, $f0
; MIPS64R5-N64-NEXT: ldc1 $f1, 8($sp)
; MIPS64R5-N64-NEXT: sub.d $f0, $f1, $f0
; MIPS64R5-N64-NEXT: cvt.s.d $f0, $f0
@@ -395,8 +395,8 @@ define void @uitofp(i32 %a) {
; MIPSR6-N32-NEXT: lui $2, 17200
; MIPSR6-N32-NEXT: sw $2, 12($sp)
; MIPSR6-N32-NEXT: sw $4, 8($sp)
-; MIPSR6-N32-NEXT: lw $2, %got_page(.LCPI5_0)($1)
-; MIPSR6-N32-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
+; MIPSR6-N32-NEXT: mtc1 $zero, $f0
+; MIPSR6-N32-NEXT: mthc1 $2, $f0
; MIPSR6-N32-NEXT: ldc1 $f1, 8($sp)
; MIPSR6-N32-NEXT: sub.d $f0, $f1, $f0
; MIPSR6-N32-NEXT: cvt.s.d $f0, $f0
@@ -418,8 +418,8 @@ define void @uitofp(i32 %a) {
; MIPSR6-N64-NEXT: lui $2, 17200
; MIPSR6-N64-NEXT: sw $2, 12($sp)
; MIPSR6-N64-NEXT: sw $4, 8($sp)
-; MIPSR6-N64-NEXT: ld $2, %got_page(.LCPI5_0)($1)
-; MIPSR6-N64-NEXT: ldc1 $f0, %got_ofst(.LCPI5_0)($2)
+; MIPSR6-N64-NEXT: mtc1 $zero, $f0
+; MIPSR6-N64-NEXT: mthc1 $2, $f0
; MIPSR6-N64-NEXT: ldc1 $f1, 8($sp)
; MIPSR6-N64-NEXT: sub.d $f0, $f1, $f0
; MIPSR6-N64-NEXT: cvt.s.d $f0, $f0
@@ -3369,16 +3369,13 @@ entry:
define half @uitofp_i32_f16(i32 %x) {
; MIPS32-LABEL: uitofp_i32_f16:
; MIPS32: # %bb.0: # %entry
-; MIPS32-NEXT: lui $2, %hi(_gp_disp)
-; MIPS32-NEXT: addiu $2, $2, %lo(_gp_disp)
; MIPS32-NEXT: addiu $sp, $sp, -8
; MIPS32-NEXT: .cfi_def_cfa_offset 8
-; MIPS32-NEXT: addu $1, $2, $25
-; MIPS32-NEXT: lui $2, 17200
-; MIPS32-NEXT: sw $2, 4($sp)
+; MIPS32-NEXT: lui $1, 17200
+; MIPS32-NEXT: sw $1, 4($sp)
; MIPS32-NEXT: sw $4, 0($sp)
-; MIPS32-NEXT: lw $1, %got($CPI37_0)($1)
-; MIPS32-NEXT: ldc1 $f0, %lo($CPI37_0)($1)
+; MIPS32-NEXT: mtc1 $zero, $f0
+; MIPS32-NEXT: mthc1 $1, $f0
; MIPS32-NEXT: ldc1 $f1, 0($sp)
; MIPS32-NEXT: sub.d $f0, $f1, $f0
; MIPS32-NEXT: cvt.s.d $f0, $f0
@@ -3392,15 +3389,12 @@ define half @uitofp_i32_f16(i32 %x) {
; MIPS64R5-N32: # %bb.0: # %entry
; MIPS64R5-N32-NEXT: addiu $sp, $sp, -16
; MIPS64R5-N32-NEXT: .cfi_def_cfa_offset 16
-; MIPS64R5-N32-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp_i32_f16)))
-; MIPS64R5-N32-NEXT: addu $1, $1, $25
-; MIPS64R5-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(uitofp_i32_f16)))
-; MIPS64R5-N32-NEXT: lui $2, 17200
-; MIPS64R5-N32-NEXT: sw $2, 12($sp)
+; MIPS64R5-N32-NEXT: lui $1, 17200
+; MIPS64R5-N32-NEXT: sw $1, 12($sp)
; MIPS64R5-N32-NEXT: sll $2, $4, 0
; MIPS64R5-N32-NEXT: sw $2, 8($sp)
-; MIPS64R5-N32-NEXT: lw $1, %got_page(.LCPI37_0)($1)
-; MIPS64R5-N32-NEXT: ldc1 $f0, %got_ofst(.LCPI37_0)($1)
+; MIPS64R5-N32-NEXT: mtc1 $zero, $f0
+; MIPS64R5-N32-NEXT: mthc1 $1, $f0
; MIPS64R5-N32-NEXT: ldc1 $f1, 8($sp)
; MIPS64R5-N32-NEXT: sub.d $f0, $f1, $f0
; MIPS64R5-N32-NEXT: cvt.s.d $f0, $f0
@@ -3414,15 +3408,12 @@ define half @uitofp_i32_f16(i32 %x) {
; MIPS64R5-N64: # %bb.0: # %entry
; MIPS64R5-N64-NEXT: daddiu $sp, $sp, -16
; MIPS64R5-N64-NEXT: .cfi_def_cfa_offset 16
-; MIPS64R5-N64-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp_i32_f16)))
-; MIPS64R5-N64-NEXT: daddu $1, $1, $25
-; MIPS64R5-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(uitofp_i32_f16)))
-; MIPS64R5-N64-NEXT: lui $2, 17200
-; MIPS64R5-N64-NEXT: sw $2, 12($sp)
+; MIPS64R5-N64-NEXT: lui $1, 17200
+; MIPS64R5-N64-NEXT: sw $1, 12($sp)
; MIPS64R5-N64-NEXT: sll $2, $4, 0
; MIPS64R5-N64-NEXT: sw $2, 8($sp)
-; MIPS64R5-N64-NEXT: ld $1, %got_page(.LCPI37_0)($1)
-; MIPS64R5-N64-NEXT: ldc1 $f0, %got_ofst(.LCPI37_0)($1)
+; MIPS64R5-N64-NEXT: mtc1 $zero, $f0
+; MIPS64R5-N64-NEXT: mthc1 $1, $f0
; MIPS64R5-N64-NEXT: ldc1 $f1, 8($sp)
; MIPS64R5-N64-NEXT: sub.d $f0, $f1, $f0
; MIPS64R5-N64-NEXT: cvt.s.d $f0, $f0
@@ -3436,14 +3427,11 @@ define half @uitofp_i32_f16(i32 %x) {
; MIPSR6-N32: # %bb.0: # %entry
; MIPSR6-N32-NEXT: addiu $sp, $sp, -16
; MIPSR6-N32-NEXT: .cfi_def_cfa_offset 16
-; MIPSR6-N32-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp_i32_f16)))
-; MIPSR6-N32-NEXT: addu $1, $1, $25
-; MIPSR6-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(uitofp_i32_f16)))
-; MIPSR6-N32-NEXT: lui $2, 17200
-; MIPSR6-N32-NEXT: sw $2, 12($sp)
+; MIPSR6-N32-NEXT: lui $1, 17200
+; MIPSR6-N32-NEXT: sw $1, 12($sp)
; MIPSR6-N32-NEXT: sw $4, 8($sp)
-; MIPSR6-N32-NEXT: lw $1, %got_page(.LCPI37_0)($1)
-; MIPSR6-N32-NEXT: ldc1 $f0, %got_ofst(.LCPI37_0)($1)
+; MIPSR6-N32-NEXT: mtc1 $zero, $f0
+; MIPSR6-N32-NEXT: mthc1 $1, $f0
; MIPSR6-N32-NEXT: ldc1 $f1, 8($sp)
; MIPSR6-N32-NEXT: sub.d $f0, $f1, $f0
; MIPSR6-N32-NEXT: cvt.s.d $f0, $f0
@@ -3457,14 +3445,11 @@ define half @uitofp_i32_f16(i32 %x) {
; MIPSR6-N64: # %bb.0: # %entry
; MIPSR6-N64-NEXT: daddiu $sp, $sp, -16
; MIPSR6-N64-NEXT: .cfi_def_cfa_offset 16
-; MIPSR6-N64-NEXT: lui $1, %hi(%neg(%gp_rel(uitofp_i32_f16)))
-; MIPSR6-N64-NEXT: daddu $1, $1, $25
-; MIPSR6-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(uitofp_i32_f16)))
-; MIPSR6-N64-NEXT: lui $2, 17200
-; MIPSR6-N64-NEXT: sw $2, 12($sp)
+; MIPSR6-N64-NEXT: lui $1, 17200
+; MIPSR6-N64-NEXT: sw $1, 12($sp)
; MIPSR6-N64-NEXT: sw $4, 8($sp)
-; MIPSR6-N64-NEXT: ld $1, %got_page(.LCPI37_0)($1)
-; MIPSR6-N64-NEXT: ldc1 $f0, %got_ofst(.LCPI37_0)($1)
+; MIPSR6-N64-NEXT: mtc1 $zero, $f0
+; MIPSR6-N64-NEXT: mthc1 $1, $f0
; MIPSR6-N64-NEXT: ldc1 $f1, 8($sp)
; MIPSR6-N64-NEXT: sub.d $f0, $f1, $f0
; MIPSR6-N64-NEXT: cvt.s.d $f0, $f0
diff --git a/llvm/test/CodeGen/Mips/o32_cc.ll b/llvm/test/CodeGen/Mips/o32_cc.ll
index fb6529ebe1472..c47bcc3bf447c 100644
--- a/llvm/test/CodeGen/Mips/o32_cc.ll
+++ b/llvm/test/CodeGen/Mips/o32_cc.ll
@@ -1,12 +1,18 @@
-; RUN: llc -mtriple=mipsel < %s | FileCheck -check-prefix=ALL %s
+; RUN: llc -mtriple=mipsel < %s | FileCheck -check-prefix=ALL,NO-MFHC1 %s
; RUN: llc -mtriple=mipsel -mcpu=mips32 < %s | FileCheck -check-prefixes=ALL,NO-MFHC1 %s
; RUN: llc -mtriple=mipsel -mcpu=mips32r2 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s
; RUN: llc -mtriple=mipsel -mcpu=mips32r2 -mattr=+fp64 < %s | FileCheck -check-prefixes=ALL,HAS-MFHC1 %s
; $f12, $f14
; ALL-LABEL: testlowercall0:
-; ALL-DAG: ldc1 $f12, %lo
-; ALL-DAG: ldc1 $f14, %lo
+; NO-MFHC1-DAG: ldc1 $f12, %lo
+; NO-MFHC1-DAG: ldc1 $f14, %lo
+; HAS-MFHC1-DAG: lui $1, 16404
+; HAS-MFHC1-DAG: mtc1 $zero, $f12
+; HAS-MFHC1-DAG: mthc1 $1, $f12
+; HAS-MFHC1-DAG: lui $1, 16408
+; HAS-MFHC1-DAG: mtc1 $zero, $f14
+; HAS-MFHC1-DAG: mthc1 $1, $f14
define void @testlowercall0() nounwind {
entry:
tail call void @f0(double 5.000000e+00, double 6.000000e+00) nounwind
@@ -29,8 +35,11 @@ declare void @f1(float, float)
; $f12, $f14
; ALL-LABEL: testlowercall2:
-; ALL-DAG: lwc1 $f12, %lo
-; ALL-DAG: ldc1 $f14, %lo
+; HAS-MFHC1-DAG: lui $1, 16408
+; HAS-MFHC1-DAG: mtc1 $zero, $f14
+; HAS-MFHC1-DAG: mthc1 $1, $f14
+; ALL-DAG: lwc1 $f12, %lo
+; NO-MFHC1-DAG: ldc1 $f14, %lo
define void @testlowercall2() nounwind {
entry:
tail call void @f2(float 8.000000e+00, double 6.000000e+00) nounwind
@@ -41,8 +50,11 @@ declare void @f2(float, double)
; $f12, $f14
; ALL-LABEL: testlowercall3:
-; ALL-DAG: ldc1 $f12, %lo
-; ALL-DAG: lwc1 $f14, %lo
+; HAS-MFHC1-DAG: lui $1, 16404
+; HAS-MFHC1-DAG: mtc1 $zero, $f12
+; HAS-MFHC1-DAG: mthc1 $1, $f12
+; NO-MFHC1-DAG: ldc1 $f12, %lo
+; ALL-DAG: lwc1 $f14, %lo
define void @testlowercall3() nounwind {
entry:
tail call void @f3(double 5.000000e+00, float 9.000000e+00) nounwind
@@ -67,10 +79,13 @@ declare void @f4(i32, i32, i32, i32)
; $f12, $6, stack
; ALL-LABEL: testlowercall5:
-; ALL-DAG: ldc1 $f12, %lo
-; ALL-DAG: addiu $6, $zero, 23
-; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
-; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
+; HAS-MFHC1-DAG: lui $1, 16430
+; HAS-MFHC1-DAG: mtc1 $zero, $f12
+; HAS-MFHC1-DAG: mthc1 $1, $f12
+; NO-MFHC1-DAG: ldc1 $f12, %lo
+; ALL-DAG: addiu $6, $zero, 23
+; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
+; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
define void @testlowercall5() nounwind {
entry:
tail call void @f5(double 1.500000e+01, i32 23, double 1.700000e+01) nounwind
@@ -81,9 +96,12 @@ declare void @f5(double, i32, double)
; $f12, $6, $7
; ALL-LABEL: testlowercall6:
-; ALL-DAG: ldc1 $f12, %lo
-; ALL-DAG: addiu $6, $zero, 33
-; ALL-DAG: addiu $7, $zero, 24
+; HAS-MFHC1-DAG: lui $1, 16441
+; HAS-MFHC1-DAG: mtc1 $zero, $f12
+; HAS-MFHC1-DAG: mthc1 $1, $f12
+; NO-MFHC1-DAG: ldc1 $f12, %lo
+; ALL-DAG: addiu $6, $zero, 33
+; ALL-DAG: addiu $7, $zero, 24
define void @testlowercall6() nounwind {
entry:
tail call void @f6(double 2.500000e+01, i32 33, i32 24) nounwind
@@ -201,9 +219,13 @@ declare void @f13(float, i32, float, i32)
; $f12, $f14, $7
; ALL-LABEL: testlowercall14:
-; ALL-DAG: ldc1 $f12, %lo
-; ALL-DAG: lwc1 $f14, %lo
-; ALL-DAG: lui $7, 16880
+; HAS-MFHC1-DAG: lui $1, 16449
+; HAS-MFHC1-DAG: ori $1, $1, 32768
+; HAS-MFHC1-DAG: mtc1 $zero, $f12
+; HAS-MFHC1-DAG: mthc1 $1, $f12
+; NO-MFHC1-DAG: ldc1 $f12, %lo
+; ALL-DAG: lwc1 $f14, %lo
+; ALL-DAG: lui $7, 16880
define void @testlowercall14() nounwind {
entry:
tail call void @f14(double 3.500000e+01, float 2.900000e+01, float 3.000000e+01) nounwind
@@ -324,8 +346,12 @@ declare void @f22(float, i32, double)
; $f12, f6
; ALL-LABEL: testlowercall23:
-; ALL-DAG: ldc1 $f12, %lo
-; ALL-DAG: addiu $6, $zero, 123
+; HAS-MFHC1-DAG: lui $1, 16454
+; HAS-MFHC1-DAG: ori $1, $1, 32768
+; HAS-MFHC1-DAG: mtc1 $zero, $f12
+; HAS-MFHC1-DAG: mthc1 $1, $f12
+; NO-MFHC1-DAG: ldc1 $f12, %lo
+; ALL-DAG: addiu $6, $zero, 123
define void @testlowercall23() nounwind {
entry:
tail call void @f23(double 4.500000e+01, i32 123) nounwind
@@ -336,10 +362,14 @@ declare void @f23(double, i32)
; $f12,$6, stack
; ALL-LABEL: testlowercall24:
-; ALL-DAG: ldc1 $f12, %lo
-; ALL-DAG: addiu $6, $zero, 133
-; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
-; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
+; HAS-MFHC1-DAG: lui $1, 16459
+; HAS-MFHC1-DAG: ori $1, $1, 32768
+; HAS-MFHC1-DAG: mtc1 $zero, $f12
+; HAS-MFHC1-DAG: mthc1 $1, $f12
+; NO-MFHC1-DAG: ldc1 $f12, %lo
+; ALL-DAG: addiu $6, $zero, 133
+; ALL-DAG: sw ${{[a-z0-9]+}}, 16($sp)
+; ALL-DAG: sw ${{[a-z0-9]+}}, 20($sp)
define void @testlowercall24() nounwind {
entry:
tail call void @f24(double 5.500000e+01, i32 133, double 6.700000e+01) nounwind
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