[llvm] [AMDGPU][GISel] Add regbank-aware same_val_zero fold to AMDGPURegBankCombiner (PR #225138)

[Chinmay Deshpande via llvm-commits]

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@@ -204,6 +204,17 @@ def zext_of_shift_amount_combines : GICombineGroup<[
   canonicalize_zext_lshr, canonicalize_zext_ashr, canonicalize_zext_shl
 ]>;
 
+// Fold (xor x, x) -> 0 and (sub x, x) -> 0.
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chinmaydd wrote:

Why cant we fix the generic rule to handle this ?

Also, needs handling for vector types

https://github.com/llvm/llvm-project/pull/225138