[llvm] 78aa14e - [TableGen] Reuse `UnitMaskIdx` lambda in `computeRegUnitLaneMasks` (NFC) (#227249)

[via llvm-commits]

Author: Igor Wodiany
Date: 2026-09-29T13:48:58+01:00
New Revision: 78aa14e1df4f0fb200c66732c4d06f52baabf69d

URL: https://github.com/llvm/llvm-project/commit/78aa14e1df4f0fb200c66732c4d06f52baabf69d
DIFF: https://github.com/llvm/llvm-project/commit/78aa14e1df4f0fb200c66732c4d06f52baabf69d.diff

LOG: [TableGen] Reuse `UnitMaskIdx` lambda in `computeRegUnitLaneMasks` (NFC) (#227249)

This simplifies the code at the expense of losing an assert that checks
that one `SUI` matches more than one `RU`s.

Added: 
    

Modified: 
    llvm/utils/TableGen/Common/CodeGenRegisters.cpp

Removed: 
    


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diff  --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index e1675ab68d20c..1da98db9cd4d1 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2376,29 +2376,6 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
     // Iterate through SubRegisters.
     using SubRegMap = CodeGenRegister::SubRegMap;
     const SubRegMap &SubRegs = Register.getSubRegs();
-    for (auto [SubRegIndex, SubReg] : SubRegs) {
-      // Ignore non-leaf subregisters, their lane masks are fully covered by
-      // the leaf subregisters, unless the subregister is not CoveredBySubRegs -
-      // this is dealt with by the loop below.
-      if (!SubReg->getSubRegs().empty())
-        continue;
-      LaneBitmask LaneMask = SubRegIndex->LaneMask;
-      // Distribute LaneMask to Register Units touched.
-      for (unsigned SUI : SubReg->getRegUnits()) {
-        bool Found = false;
-        unsigned u = 0;
-        for (unsigned RU : RegUnits) {
-          if (SUI == RU) {
-            RegUnitLaneMasks[u] &= LaneMask;
-            assert(!Found);
-            Found = true;
-          }
-          ++u;
-        }
-        (void)Found;
-        assert(Found);
-      }
-    }
 
     auto UnitMaskIdx = [&](unsigned SUI) {
       unsigned U = 0;
@@ -2410,6 +2387,18 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
       llvm_unreachable("unit is not part of the register");
     };
 
+    for (auto [SubRegIndex, SubReg] : SubRegs) {
+      // Ignore non-leaf subregisters, their lane masks are fully covered by
+      // the leaf subregisters, unless the subregister is not CoveredBySubRegs -
+      // this is dealt with by the loop below.
+      if (!SubReg->getSubRegs().empty())
+        continue;
+      LaneBitmask LaneMask = SubRegIndex->LaneMask;
+      // Distribute LaneMask to Register Units touched.
+      for (unsigned SUI : SubReg->getRegUnits())
+        RegUnitLaneMasks[UnitMaskIdx(SUI)] &= LaneMask;
+    }
+
     // A sub-register that is not CoveredBySubRegs may be missing lanes that
     // none of its leaves account for. If left unclaimed, those lanes would
     // not appear in any register unit's mask, making them invisible to