[llvm] [AArch64] Increase fixed-length SVE scalarization costs (PR #226120)
Utpal Bora via llvm-commits
llvm-commits at lists.llvm.org
Tue Sep 29 05:13:18 PDT 2026
https://github.com/utpalbora updated https://github.com/llvm/llvm-project/pull/226120
>From 05435c85602500fcdd5621978277a6bd4cb512c1 Mon Sep 17 00:00:00 2001
From: Utpal Bora <utpal.bora2 at arm.com>
Date: Thu, 24 Sep 2026 08:49:56 +0000
Subject: [PATCH 1/2] [AArch64] Increase fixed-length SVE scalarization costs
Scalarizing wide fixed-length SVE vectors can require expensive operand
materialization that is not reflected by the current cost model.
Add a conservative overhead to prevent SLP from selecting unprofitable trees.
---
.../AArch64/AArch64TargetTransformInfo.cpp | 26 +++++--
.../CostModel/AArch64/sve-vls-reduce-fp.ll | 18 ++---
.../AArch64/sve-wider-vector-inserts.ll | 71 +++++++++++++++++++
3 files changed, 100 insertions(+), 15 deletions(-)
create mode 100644 llvm/test/Transforms/SLPVectorizer/AArch64/sve-wider-vector-inserts.ll
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 581f37d4c17bce..21bf7354516100 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4891,12 +4891,26 @@ InstructionCost AArch64TTIImpl::getScalarizationOverhead(
TTI::VectorInstrContext VIC) const {
if (isa<ScalableVectorType>(Ty))
return InstructionCost::getInvalid();
- if (Ty->getElementType()->isFloatingPointTy())
- return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
- CostKind);
- unsigned VecInstCost =
- CostKind == TTI::TCK_CodeSize ? 1 : ST->getVectorInsertExtractBaseCost();
- return DemandedElts.popcount() * (Insert + Extract) * VecInstCost;
+
+ std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
+ if (!ST->useSVEForFixedLengthVectors(LT.second)) {
+ if (Ty->getElementType()->isFloatingPointTy())
+ return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
+ CostKind);
+
+ unsigned VecInstCost = CostKind == TTI::TCK_CodeSize
+ ? 1
+ : ST->getVectorInsertExtractBaseCost();
+ return DemandedElts.popcount() * (Insert + Extract) * VecInstCost;
+ }
+
+ // Scalarizing fixed-length SVE vectors is expensive. Add an extra cost to
+ // prevent the SLP vectorizer from selecting unprofitable trees.
+ // TODO: Model the scalarization overhead of wide fixed-length SVE vectors
+ // accurately.
+ return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
+ CostKind) +
+ 5;
}
std::optional<InstructionCost> AArch64TTIImpl::getFP16BF16PromoteCost(
diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-vls-reduce-fp.ll b/llvm/test/Analysis/CostModel/AArch64/sve-vls-reduce-fp.ll
index ae3de7d1217dc8..a6606a10b671a2 100644
--- a/llvm/test/Analysis/CostModel/AArch64/sve-vls-reduce-fp.ll
+++ b/llvm/test/Analysis/CostModel/AArch64/sve-vls-reduce-fp.ll
@@ -47,9 +47,9 @@ define void @reduce_fadd_strict_256b_types() {
; VSCALE-1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; VSCALE-FROM-2-LABEL: 'reduce_fadd_strict_256b_types'
-; VSCALE-FROM-2-NEXT: Cost Model: Found costs of RThru:62 CodeSize:47 Lat:94 SizeLat:62 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> poison)
-; VSCALE-FROM-2-NEXT: Cost Model: Found costs of RThru:30 CodeSize:23 Lat:46 SizeLat:30 for: %fadd_v8f32 = call float @llvm.vector.reduce.fadd.v8f32(float 0.000000e+00, <8 x float> poison)
-; VSCALE-FROM-2-NEXT: Cost Model: Found costs of RThru:14 CodeSize:11 Lat:22 SizeLat:14 for: %fadd_v4f64 = call double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> poison)
+; VSCALE-FROM-2-NEXT: Cost Model: Found costs of RThru:67 CodeSize:52 Lat:99 SizeLat:67 for: %fadd_v16f16 = call half @llvm.vector.reduce.fadd.v16f16(half 0.000000e+00, <16 x half> poison)
+; VSCALE-FROM-2-NEXT: Cost Model: Found costs of RThru:35 CodeSize:28 Lat:51 SizeLat:35 for: %fadd_v8f32 = call float @llvm.vector.reduce.fadd.v8f32(float 0.000000e+00, <8 x float> poison)
+; VSCALE-FROM-2-NEXT: Cost Model: Found costs of RThru:19 CodeSize:16 Lat:27 SizeLat:19 for: %fadd_v4f64 = call double @llvm.vector.reduce.fadd.v4f64(double 0.000000e+00, <4 x double> poison)
; VSCALE-FROM-2-NEXT: Cost Model: Found costs of RThru:22 CodeSize:4 Lat:8 SizeLat:4 for: %fadd_v2f128 = call fp128 @llvm.vector.reduce.fadd.v2f128(fp128 poison, <2 x fp128> poison)
; VSCALE-FROM-2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
@@ -69,16 +69,16 @@ define void @reduce_fadd_strict_512b_types() {
; VSCALE-1-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; VSCALE-2-LABEL: 'reduce_fadd_strict_512b_types'
-; VSCALE-2-NEXT: Cost Model: Found costs of RThru:124 CodeSize:94 Lat:188 SizeLat:124 for: %fadd_v32f16 = call half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> poison)
-; VSCALE-2-NEXT: Cost Model: Found costs of RThru:60 CodeSize:46 Lat:92 SizeLat:60 for: %fadd_v16f32 = call float @llvm.vector.reduce.fadd.v16f32(float 0.000000e+00, <16 x float> poison)
-; VSCALE-2-NEXT: Cost Model: Found costs of RThru:28 CodeSize:22 Lat:44 SizeLat:28 for: %fadd_v8f64 = call double @llvm.vector.reduce.fadd.v8f64(double 0.000000e+00, <8 x double> poison)
+; VSCALE-2-NEXT: Cost Model: Found costs of RThru:129 CodeSize:99 Lat:193 SizeLat:129 for: %fadd_v32f16 = call half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> poison)
+; VSCALE-2-NEXT: Cost Model: Found costs of RThru:65 CodeSize:51 Lat:97 SizeLat:65 for: %fadd_v16f32 = call float @llvm.vector.reduce.fadd.v16f32(float 0.000000e+00, <16 x float> poison)
+; VSCALE-2-NEXT: Cost Model: Found costs of RThru:33 CodeSize:27 Lat:49 SizeLat:33 for: %fadd_v8f64 = call double @llvm.vector.reduce.fadd.v8f64(double 0.000000e+00, <8 x double> poison)
; VSCALE-2-NEXT: Cost Model: Found costs of RThru:44 CodeSize:8 Lat:16 SizeLat:8 for: %fadd_v4f128 = call fp128 @llvm.vector.reduce.fadd.v4f128(fp128 poison, <4 x fp128> poison)
; VSCALE-2-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
; VSCALE-FROM-4-LABEL: 'reduce_fadd_strict_512b_types'
-; VSCALE-FROM-4-NEXT: Cost Model: Found costs of RThru:126 CodeSize:95 Lat:190 SizeLat:126 for: %fadd_v32f16 = call half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> poison)
-; VSCALE-FROM-4-NEXT: Cost Model: Found costs of RThru:62 CodeSize:47 Lat:94 SizeLat:62 for: %fadd_v16f32 = call float @llvm.vector.reduce.fadd.v16f32(float 0.000000e+00, <16 x float> poison)
-; VSCALE-FROM-4-NEXT: Cost Model: Found costs of RThru:30 CodeSize:23 Lat:46 SizeLat:30 for: %fadd_v8f64 = call double @llvm.vector.reduce.fadd.v8f64(double 0.000000e+00, <8 x double> poison)
+; VSCALE-FROM-4-NEXT: Cost Model: Found costs of RThru:131 CodeSize:100 Lat:195 SizeLat:131 for: %fadd_v32f16 = call half @llvm.vector.reduce.fadd.v32f16(half 0.000000e+00, <32 x half> poison)
+; VSCALE-FROM-4-NEXT: Cost Model: Found costs of RThru:67 CodeSize:52 Lat:99 SizeLat:67 for: %fadd_v16f32 = call float @llvm.vector.reduce.fadd.v16f32(float 0.000000e+00, <16 x float> poison)
+; VSCALE-FROM-4-NEXT: Cost Model: Found costs of RThru:35 CodeSize:28 Lat:51 SizeLat:35 for: %fadd_v8f64 = call double @llvm.vector.reduce.fadd.v8f64(double 0.000000e+00, <8 x double> poison)
; VSCALE-FROM-4-NEXT: Cost Model: Found costs of RThru:44 CodeSize:8 Lat:16 SizeLat:8 for: %fadd_v4f128 = call fp128 @llvm.vector.reduce.fadd.v4f128(fp128 poison, <4 x fp128> poison)
; VSCALE-FROM-4-NEXT: Cost Model: Found costs of RThru:0 CodeSize:1 Lat:1 SizeLat:1 for: ret void
;
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/sve-wider-vector-inserts.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/sve-wider-vector-inserts.ll
new file mode 100644
index 00000000000000..9eb186675dcfb4
--- /dev/null
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/sve-wider-vector-inserts.ll
@@ -0,0 +1,71 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
+; RUN: opt -passes=slp-vectorizer -mtriple=aarch64-none-linux-gnu \
+; RUN: -mattr=+sve -S %s | FileCheck %s
+
+; Check that the scalarization overhead for fixed-length SVE vectors prevents
+; SLP from selecting an unprofitable wide reduction tree.
+define double @insert_into_wider_vector(double %x, double %y) vscale_range(2, 0) {
+;
+; CHECK-LABEL: @insert_into_wider_vector(
+; CHECK-NEXT: [[MUL0:%.*]] = fmul fast double [[X:%.*]], 0.000000e+00
+; CHECK-NEXT: [[ADD0:%.*]] = fadd reassoc nsz double 0.000000e+00, [[MUL0]]
+; CHECK-NEXT: [[MUL1:%.*]] = fmul fast double 0.000000e+00, [[Y:%.*]]
+; CHECK-NEXT: [[TMP13:%.*]] = fadd reassoc nsz double [[ADD0]], [[MUL1]]
+; CHECK-NEXT: [[TMP14:%.*]] = fmul fast double 1.000000e+00, [[X]]
+; CHECK-NEXT: [[OP_RDX19:%.*]] = fadd reassoc nsz double [[TMP13]], [[TMP14]]
+; CHECK-NEXT: [[MUL3:%.*]] = fmul fast double 0.000000e+00, 0.000000e+00
+; CHECK-NEXT: [[ADD3:%.*]] = fadd reassoc nsz double [[OP_RDX19]], [[MUL3]]
+; CHECK-NEXT: [[MUL4:%.*]] = fmul fast double 1.000000e+00, 1.000000e+00
+; CHECK-NEXT: [[ADD4:%.*]] = fadd reassoc nsz double [[ADD3]], [[MUL4]]
+; CHECK-NEXT: [[MUL5:%.*]] = fmul fast double [[X]], [[Y]]
+; CHECK-NEXT: [[ADD5:%.*]] = fadd reassoc nsz double [[ADD4]], [[MUL5]]
+; CHECK-NEXT: [[ADD6:%.*]] = fadd reassoc nsz double [[ADD5]], 0.000000e+00
+; CHECK-NEXT: [[ADD7:%.*]] = fadd reassoc nsz double [[ADD6]], 0.000000e+00
+; CHECK-NEXT: [[MUL8:%.*]] = fmul fast double [[X]], 0.000000e+00
+; CHECK-NEXT: [[ADD8:%.*]] = fadd reassoc nsz double [[ADD7]], [[MUL8]]
+; CHECK-NEXT: [[MUL9:%.*]] = fmul fast double 0.000000e+00, [[Y]]
+; CHECK-NEXT: [[ADD9:%.*]] = fadd reassoc nsz double [[ADD8]], [[MUL9]]
+; CHECK-NEXT: [[MUL10:%.*]] = fmul fast double 1.000000e+00, [[X]]
+; CHECK-NEXT: [[ADD10:%.*]] = fadd reassoc nsz double [[ADD9]], [[MUL10]]
+; CHECK-NEXT: [[ADD11:%.*]] = fadd reassoc nsz double [[ADD10]], 0.000000e+00
+; CHECK-NEXT: [[ADD12:%.*]] = fadd reassoc nsz double [[ADD11]], 1.000000e+00
+; CHECK-NEXT: [[MUL13:%.*]] = fmul fast double [[X]], [[Y]]
+; CHECK-NEXT: [[ADD13:%.*]] = fadd reassoc nsz double [[ADD12]], [[MUL13]]
+; CHECK-NEXT: [[ADD14:%.*]] = fadd reassoc nsz double [[ADD13]], 0.000000e+00
+; CHECK-NEXT: [[OP_RDX20:%.*]] = fadd reassoc nsz double [[ADD14]], 0.000000e+00
+; CHECK-NEXT: ret double [[OP_RDX20]]
+;
+ %mul0 = fmul fast double %x, 0.0
+ %add0 = fadd reassoc nsz double 0.0, %mul0
+ %mul1 = fmul fast double 0.0, %y
+ %add1 = fadd reassoc nsz double %add0, %mul1
+ %mul2 = fmul fast double 1.0, %x
+ %add2 = fadd reassoc nsz double %add1, %mul2
+ %mul3 = fmul fast double 0.0, 0.0
+ %add3 = fadd reassoc nsz double %add2, %mul3
+ %mul4 = fmul fast double 1.0, 1.0
+ %add4 = fadd reassoc nsz double %add3, %mul4
+ %mul5 = fmul fast double %x, %y
+ %add5 = fadd reassoc nsz double %add4, %mul5
+ %mul6 = fmul fast double 0.0, 0.0
+ %add6 = fadd reassoc nsz double %add5, %mul6
+ %mul7 = fmul fast double 0.0, 0.0
+ %add7 = fadd reassoc nsz double %add6, %mul7
+ %mul8 = fmul fast double %x, 0.0
+ %add8 = fadd reassoc nsz double %add7, %mul8
+ %mul9 = fmul fast double 0.0, %y
+ %add9 = fadd reassoc nsz double %add8, %mul9
+ %mul10 = fmul fast double 1.0, %x
+ %add10 = fadd reassoc nsz double %add9, %mul10
+ %mul11 = fmul fast double 0.0, 0.0
+ %add11 = fadd reassoc nsz double %add10, %mul11
+ %mul12 = fmul fast double 1.0, 1.0
+ %add12 = fadd reassoc nsz double %add11, %mul12
+ %mul13 = fmul fast double %x, %y
+ %add13 = fadd reassoc nsz double %add12, %mul13
+ %mul14 = fmul fast double 0.0, 0.0
+ %add14 = fadd reassoc nsz double %add13, %mul14
+ %mul15 = fmul fast double 0.0, 0.0
+ %add15 = fadd reassoc nsz double %add14, %mul15
+ ret double %add15
+}
>From 0fcd6dddb1aea2e1513ccddc9fc8f8b7868af00e Mon Sep 17 00:00:00 2001
From: Utpal Bora <utpal.bora2 at arm.com>
Date: Tue, 29 Sep 2026 11:28:15 +0000
Subject: [PATCH 2/2] Addressed review comments. Updated testcase to prohibit
constant folding for the scalar case.
---
.../AArch64/AArch64TargetTransformInfo.cpp | 27 ++--
.../AArch64/sve-wider-vector-inserts.ll | 143 +++++++++++-------
2 files changed, 98 insertions(+), 72 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
index 21bf7354516100..98c86bb542c002 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp
@@ -4892,25 +4892,22 @@ InstructionCost AArch64TTIImpl::getScalarizationOverhead(
if (isa<ScalableVectorType>(Ty))
return InstructionCost::getInvalid();
- std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
- if (!ST->useSVEForFixedLengthVectors(LT.second)) {
- if (Ty->getElementType()->isFloatingPointTy())
- return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
- CostKind);
-
- unsigned VecInstCost = CostKind == TTI::TCK_CodeSize
- ? 1
- : ST->getVectorInsertExtractBaseCost();
- return DemandedElts.popcount() * (Insert + Extract) * VecInstCost;
- }
-
// Scalarizing fixed-length SVE vectors is expensive. Add an extra cost to
// prevent the SLP vectorizer from selecting unprofitable trees.
// TODO: Model the scalarization overhead of wide fixed-length SVE vectors
// accurately.
- return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
- CostKind) +
- 5;
+ std::pair<InstructionCost, MVT> LT = getTypeLegalizationCost(Ty);
+ if (ST->useSVEForFixedLengthVectors(LT.second)) {
+ return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
+ CostKind) +
+ 5;
+ }
+ if (Ty->getElementType()->isFloatingPointTy())
+ return BaseT::getScalarizationOverhead(Ty, DemandedElts, Insert, Extract,
+ CostKind);
+ unsigned VecInstCost =
+ CostKind == TTI::TCK_CodeSize ? 1 : ST->getVectorInsertExtractBaseCost();
+ return DemandedElts.popcount() * (Insert + Extract) * VecInstCost;
}
std::optional<InstructionCost> AArch64TTIImpl::getFP16BF16PromoteCost(
diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/sve-wider-vector-inserts.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/sve-wider-vector-inserts.ll
index 9eb186675dcfb4..3ddbb2f931189f 100644
--- a/llvm/test/Transforms/SLPVectorizer/AArch64/sve-wider-vector-inserts.ll
+++ b/llvm/test/Transforms/SLPVectorizer/AArch64/sve-wider-vector-inserts.ll
@@ -4,68 +4,97 @@
; Check that the scalarization overhead for fixed-length SVE vectors prevents
; SLP from selecting an unprofitable wide reduction tree.
-define double @insert_into_wider_vector(double %x, double %y) vscale_range(2, 0) {
+define double @insert_into_wider_vector(double %a0, double %a1, double %a2, double %a3, double %a4, double %a5, double %a6, double %a7, double %a8, double %a9, double %a10, double %a11, double %a12, double %a13, double %a14, double %a15) vscale_range(2, 0) {
;
; CHECK-LABEL: @insert_into_wider_vector(
-; CHECK-NEXT: [[MUL0:%.*]] = fmul fast double [[X:%.*]], 0.000000e+00
-; CHECK-NEXT: [[ADD0:%.*]] = fadd reassoc nsz double 0.000000e+00, [[MUL0]]
-; CHECK-NEXT: [[MUL1:%.*]] = fmul fast double 0.000000e+00, [[Y:%.*]]
-; CHECK-NEXT: [[TMP13:%.*]] = fadd reassoc nsz double [[ADD0]], [[MUL1]]
-; CHECK-NEXT: [[TMP14:%.*]] = fmul fast double 1.000000e+00, [[X]]
-; CHECK-NEXT: [[OP_RDX19:%.*]] = fadd reassoc nsz double [[TMP13]], [[TMP14]]
-; CHECK-NEXT: [[MUL3:%.*]] = fmul fast double 0.000000e+00, 0.000000e+00
-; CHECK-NEXT: [[ADD3:%.*]] = fadd reassoc nsz double [[OP_RDX19]], [[MUL3]]
-; CHECK-NEXT: [[MUL4:%.*]] = fmul fast double 1.000000e+00, 1.000000e+00
-; CHECK-NEXT: [[ADD4:%.*]] = fadd reassoc nsz double [[ADD3]], [[MUL4]]
-; CHECK-NEXT: [[MUL5:%.*]] = fmul fast double [[X]], [[Y]]
-; CHECK-NEXT: [[ADD5:%.*]] = fadd reassoc nsz double [[ADD4]], [[MUL5]]
-; CHECK-NEXT: [[ADD6:%.*]] = fadd reassoc nsz double [[ADD5]], 0.000000e+00
-; CHECK-NEXT: [[ADD7:%.*]] = fadd reassoc nsz double [[ADD6]], 0.000000e+00
-; CHECK-NEXT: [[MUL8:%.*]] = fmul fast double [[X]], 0.000000e+00
-; CHECK-NEXT: [[ADD8:%.*]] = fadd reassoc nsz double [[ADD7]], [[MUL8]]
-; CHECK-NEXT: [[MUL9:%.*]] = fmul fast double 0.000000e+00, [[Y]]
-; CHECK-NEXT: [[ADD9:%.*]] = fadd reassoc nsz double [[ADD8]], [[MUL9]]
-; CHECK-NEXT: [[MUL10:%.*]] = fmul fast double 1.000000e+00, [[X]]
-; CHECK-NEXT: [[ADD10:%.*]] = fadd reassoc nsz double [[ADD9]], [[MUL10]]
-; CHECK-NEXT: [[ADD11:%.*]] = fadd reassoc nsz double [[ADD10]], 0.000000e+00
-; CHECK-NEXT: [[ADD12:%.*]] = fadd reassoc nsz double [[ADD11]], 1.000000e+00
-; CHECK-NEXT: [[MUL13:%.*]] = fmul fast double [[X]], [[Y]]
-; CHECK-NEXT: [[ADD13:%.*]] = fadd reassoc nsz double [[ADD12]], [[MUL13]]
-; CHECK-NEXT: [[ADD14:%.*]] = fadd reassoc nsz double [[ADD13]], 0.000000e+00
-; CHECK-NEXT: [[OP_RDX20:%.*]] = fadd reassoc nsz double [[ADD14]], 0.000000e+00
-; CHECK-NEXT: ret double [[OP_RDX20]]
+; CHECK-NEXT: [[MUL0:%.*]] = fmul fast double [[A0:%.*]], 2.000000e+00
+; CHECK-NEXT: [[MUL1:%.*]] = fmul fast double [[A1:%.*]], 3.000000e+00
+; CHECK-NEXT: [[MUL2:%.*]] = fmul fast double [[A2:%.*]], 1.000000e+00
+; CHECK-NEXT: [[MUL3:%.*]] = fmul fast double [[A3:%.*]], 2.000000e+00
+; CHECK-NEXT: [[MUL4:%.*]] = fmul fast double [[A4:%.*]], 3.000000e+00
+; CHECK-NEXT: [[MUL5:%.*]] = fmul fast double [[A5:%.*]], 1.000000e+00
+; CHECK-NEXT: [[MUL7:%.*]] = fmul fast double [[A7:%.*]], 3.000000e+00
+; CHECK-NEXT: [[MUL8:%.*]] = fmul fast double [[A8:%.*]], 1.000000e+00
+; CHECK-NEXT: [[MUL10:%.*]] = fmul fast double [[A10:%.*]], 3.000000e+00
+; CHECK-NEXT: [[MUL11:%.*]] = fmul fast double [[A11:%.*]], 1.000000e+00
+; CHECK-NEXT: [[MUL13:%.*]] = fmul fast double [[A13:%.*]], 3.000000e+00
+; CHECK-NEXT: [[MUL14:%.*]] = fmul fast double [[A14:%.*]], 1.000000e+00
+; CHECK-NEXT: [[MUL15:%.*]] = fmul fast double [[A15:%.*]], 2.000000e+00
+; CHECK-NEXT: [[TMP1:%.*]] = fmul reassoc nsz double [[MUL0]], 2.000000e+00
+; CHECK-NEXT: [[TMP2:%.*]] = fmul reassoc nsz double [[MUL1]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX:%.*]] = fadd reassoc nsz double [[TMP1]], [[TMP2]]
+; CHECK-NEXT: [[TMP3:%.*]] = fmul reassoc nsz double [[MUL2]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX1:%.*]] = fadd reassoc nsz double [[OP_RDX]], [[TMP3]]
+; CHECK-NEXT: [[TMP4:%.*]] = fmul reassoc nsz double [[MUL3]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX2:%.*]] = fadd reassoc nsz double [[OP_RDX1]], [[TMP4]]
+; CHECK-NEXT: [[TMP5:%.*]] = fmul reassoc nsz double [[MUL4]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX3:%.*]] = fadd reassoc nsz double [[OP_RDX2]], [[TMP5]]
+; CHECK-NEXT: [[TMP6:%.*]] = fmul reassoc nsz double [[MUL5]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX4:%.*]] = fadd reassoc nsz double [[OP_RDX3]], [[TMP6]]
+; CHECK-NEXT: [[OP_RDX18:%.*]] = fmul reassoc nsz double 4.000000e+00, [[A6:%.*]]
+; CHECK-NEXT: [[OP_RDX5:%.*]] = fadd reassoc nsz double [[OP_RDX4]], [[OP_RDX18]]
+; CHECK-NEXT: [[TMP7:%.*]] = fmul reassoc nsz double [[MUL7]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX6:%.*]] = fadd reassoc nsz double [[OP_RDX5]], [[TMP7]]
+; CHECK-NEXT: [[TMP8:%.*]] = fmul reassoc nsz double [[MUL8]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX7:%.*]] = fadd reassoc nsz double [[OP_RDX6]], [[TMP8]]
+; CHECK-NEXT: [[OP_RDX17:%.*]] = fmul reassoc nsz double 4.000000e+00, [[A9:%.*]]
+; CHECK-NEXT: [[OP_RDX8:%.*]] = fadd reassoc nsz double [[OP_RDX7]], [[OP_RDX17]]
+; CHECK-NEXT: [[TMP9:%.*]] = fmul reassoc nsz double [[MUL10]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX9:%.*]] = fadd reassoc nsz double [[OP_RDX8]], [[TMP9]]
+; CHECK-NEXT: [[TMP10:%.*]] = fmul reassoc nsz double [[MUL11]], 2.000000e+00
+; CHECK-NEXT: [[OP_RDX10:%.*]] = fadd reassoc nsz double [[OP_RDX9]], [[TMP10]]
+; CHECK-NEXT: [[OP_RDX16:%.*]] = fmul reassoc nsz double 4.000000e+00, [[A12:%.*]]
+; CHECK-NEXT: [[OP_RDX11:%.*]] = fadd reassoc nsz double [[OP_RDX10]], [[OP_RDX16]]
+; CHECK-NEXT: [[OP_RDX12:%.*]] = fadd reassoc nsz double [[OP_RDX11]], [[MUL13]]
+; CHECK-NEXT: [[OP_RDX13:%.*]] = fadd reassoc nsz double [[OP_RDX12]], [[MUL14]]
+; CHECK-NEXT: [[OP_RDX14:%.*]] = fadd reassoc nsz double [[OP_RDX13]], [[MUL15]]
+; CHECK-NEXT: [[OP_RDX15:%.*]] = fadd reassoc nsz double [[OP_RDX14]], 0.000000e+00
+; CHECK-NEXT: ret double [[OP_RDX15]]
;
- %mul0 = fmul fast double %x, 0.0
- %add0 = fadd reassoc nsz double 0.0, %mul0
- %mul1 = fmul fast double 0.0, %y
- %add1 = fadd reassoc nsz double %add0, %mul1
- %mul2 = fmul fast double 1.0, %x
- %add2 = fadd reassoc nsz double %add1, %mul2
- %mul3 = fmul fast double 0.0, 0.0
- %add3 = fadd reassoc nsz double %add2, %mul3
- %mul4 = fmul fast double 1.0, 1.0
- %add4 = fadd reassoc nsz double %add3, %mul4
- %mul5 = fmul fast double %x, %y
- %add5 = fadd reassoc nsz double %add4, %mul5
- %mul6 = fmul fast double 0.0, 0.0
- %add6 = fadd reassoc nsz double %add5, %mul6
- %mul7 = fmul fast double 0.0, 0.0
- %add7 = fadd reassoc nsz double %add6, %mul7
- %mul8 = fmul fast double %x, 0.0
- %add8 = fadd reassoc nsz double %add7, %mul8
- %mul9 = fmul fast double 0.0, %y
- %add9 = fadd reassoc nsz double %add8, %mul9
- %mul10 = fmul fast double 1.0, %x
- %add10 = fadd reassoc nsz double %add9, %mul10
- %mul11 = fmul fast double 0.0, 0.0
- %add11 = fadd reassoc nsz double %add10, %mul11
- %mul12 = fmul fast double 1.0, 1.0
- %add12 = fadd reassoc nsz double %add11, %mul12
- %mul13 = fmul fast double %x, %y
+ %mul0 = fmul fast double %a0, 2.0
+ %dbl0 = fadd fast double %mul0, %mul0
+ %add0 = fadd reassoc nsz double 0.0, %dbl0
+ %mul1 = fmul fast double %a1, 3.0
+ %dbl1 = fadd fast double %mul1, %mul1
+ %add1 = fadd reassoc nsz double %add0, %dbl1
+ %mul2 = fmul fast double %a2, 1.0
+ %dbl2 = fadd fast double %mul2, %mul2
+ %add2 = fadd reassoc nsz double %add1, %dbl2
+ %mul3 = fmul fast double %a3, 2.0
+ %dbl3 = fadd fast double %mul3, %mul3
+ %add3 = fadd reassoc nsz double %add2, %dbl3
+ %mul4 = fmul fast double %a4, 3.0
+ %dbl4 = fadd fast double %mul4, %mul4
+ %add4 = fadd reassoc nsz double %add3, %dbl4
+ %mul5 = fmul fast double %a5, 1.0
+ %dbl5 = fadd fast double %mul5, %mul5
+ %add5 = fadd reassoc nsz double %add4, %dbl5
+ %mul6 = fmul fast double %a6, 2.0
+ %dbl6 = fadd fast double %mul6, %mul6
+ %add6 = fadd reassoc nsz double %add5, %dbl6
+ %mul7 = fmul fast double %a7, 3.0
+ %dbl7 = fadd fast double %mul7, %mul7
+ %add7 = fadd reassoc nsz double %add6, %dbl7
+ %mul8 = fmul fast double %a8, 1.0
+ %dbl8 = fadd fast double %mul8, %mul8
+ %add8 = fadd reassoc nsz double %add7, %dbl8
+ %mul9 = fmul fast double %a9, 2.0
+ %dbl9 = fadd fast double %mul9, %mul9
+ %add9 = fadd reassoc nsz double %add8, %dbl9
+ %mul10 = fmul fast double %a10, 3.0
+ %dbl10 = fadd fast double %mul10, %mul10
+ %add10 = fadd reassoc nsz double %add9, %dbl10
+ %mul11 = fmul fast double %a11, 1.0
+ %dbl11 = fadd fast double %mul11, %mul11
+ %add11 = fadd reassoc nsz double %add10, %dbl11
+ %mul12 = fmul fast double %a12, 2.0
+ %dbl12 = fadd fast double %mul12, %mul12
+ %add12 = fadd reassoc nsz double %add11, %dbl12
+ %mul13 = fmul fast double %a13, 3.0
%add13 = fadd reassoc nsz double %add12, %mul13
- %mul14 = fmul fast double 0.0, 0.0
+ %mul14 = fmul fast double %a14, 1.0
%add14 = fadd reassoc nsz double %add13, %mul14
- %mul15 = fmul fast double 0.0, 0.0
+ %mul15 = fmul fast double %a15, 2.0
%add15 = fadd reassoc nsz double %add14, %mul15
ret double %add15
}
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