[llvm] a4b0944 - [AArch64] ISel support for nxv1i1 vector_reverse (#226939)

[via llvm-commits]

Author: Gaëtan Bossu
Date: 2026-09-29T11:01:42+01:00
New Revision: a4b0944bde4640586dd902d3ad401a6270c8a1fe

URL: https://github.com/llvm/llvm-project/commit/a4b0944bde4640586dd902d3ad401a6270c8a1fe
DIFF: https://github.com/llvm/llvm-project/commit/a4b0944bde4640586dd902d3ad401a6270c8a1fe.diff

LOG: [AArch64] ISel support for nxv1i1 vector_reverse (#226939)

This ensures llvm.vector.reverse can be selected for nxv1i1 types. These intrinsics can be generated by LoopVectorizer for `VF = vscale x 1` and loops iterating in reverse order.

Added: 
    

Modified: 
    llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
    llvm/lib/Target/AArch64/AArch64ISelLowering.h
    llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 99f81c9b659ec..2ddc7fe934430 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1678,6 +1678,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
 
     setOperationAction(ISD::GET_ACTIVE_LANE_MASK, MVT::nxv1i1, Custom);
+    setOperationAction(ISD::VECTOR_REVERSE, MVT::nxv1i1, Custom);
 
     if (Subtarget->isSVEorStreamingSVEAvailable() &&
         (Subtarget->hasSVE2p1() || Subtarget->hasSME2()))
@@ -8889,6 +8890,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
     return LowerVECTOR_REPEAT(Op, DAG);
   case ISD::VECTOR_SHUFFLE:
     return LowerVECTOR_SHUFFLE(Op, DAG);
+  case ISD::VECTOR_REVERSE:
+    return LowerVECTOR_REVERSE(Op, DAG);
   case ISD::SPLAT_VECTOR:
     return LowerSPLAT_VECTOR(Op, DAG);
   case ISD::EXTRACT_SUBVECTOR:
@@ -13427,6 +13430,18 @@ SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op,
   return SDValue();
 }
 
+SDValue AArch64TargetLowering::LowerVECTOR_REVERSE(SDValue Op,
+                                                   SelectionDAG &DAG) const {
+  assert(Op.getValueType() == MVT::nxv1i1 && "Unexpected vector type!");
+
+  SDLoc DL(Op);
+  // Select nxv1i1 vector_reverse by widening to nxv2i1.
+  SDValue Widened = DAG.getInsertSubvector(DL, DAG.getPOISON(MVT::nxv2i1),
+                                           Op.getOperand(0), 0);
+  SDValue Reversed = DAG.getNode(ISD::VECTOR_REVERSE, DL, MVT::nxv2i1, Widened);
+  return DAG.getExtractSubvector(DL, MVT::nxv1i1, Reversed, 1);
+}
+
 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
                                               SelectionDAG &DAG) const {
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();

diff  --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index e1ac77334d2c7..027831aedb7eb 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -767,6 +767,7 @@ class AArch64TargetLowering : public TargetLowering {
   SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVECTOR_REPEAT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,

diff  --git a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
index 669a49330856d..e55778e7f15a5 100644
--- a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
+++ b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
@@ -8,6 +8,26 @@ target triple = "aarch64-unknown-linux-gnu"
 ; VECTOR_REVERSE - PPR
 ;
 
+define <vscale x 1 x i1> @reverse_nxv1i1(<vscale x 1 x i1> %a) #0 {
+; CHECK-SELDAG-LABEL: reverse_nxv1i1:
+; CHECK-SELDAG:       // %bb.0:
+; CHECK-SELDAG-NEXT:    uzp1 p0.d, p0.d, p0.d
+; CHECK-SELDAG-NEXT:    rev p0.d, p0.d
+; CHECK-SELDAG-NEXT:    punpkhi p0.h, p0.b
+; CHECK-SELDAG-NEXT:    ret
+;
+; CHECK-FASTISEL-LABEL: reverse_nxv1i1:
+; CHECK-FASTISEL:       // %bb.0:
+; CHECK-FASTISEL-NEXT:    // implicit-def: $p1
+; CHECK-FASTISEL-NEXT:    uzp1 p0.d, p0.d, p1.d
+; CHECK-FASTISEL-NEXT:    rev p0.d, p0.d
+; CHECK-FASTISEL-NEXT:    punpkhi p0.h, p0.b
+; CHECK-FASTISEL-NEXT:    ret
+
+  %res = call <vscale x 1 x i1> @llvm.vector.reverse.nxv1i1(<vscale x 1 x i1> %a)
+  ret <vscale x 1 x i1> %res
+}
+
 define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) #0 {
 ; CHECK-LABEL: reverse_nxv2i1:
 ; CHECK:       // %bb.0: