[llvm] [TableGen] Reuse `UnitMaskIdx` lambda in `computeRegUnitLaneMasks` (NFC) (PR #227249)

[Igor Wodiany via llvm-commits]

https://github.com/IgWod created https://github.com/llvm/llvm-project/pull/227249

This simplifies the code at the expense of losing an assert that checks that one `SUI` matches more than one `RU`s. Lambda was introduced as a part of #223653.

>From a63486b9b493854ec206bc079f060b8c2baf54a0 Mon Sep 17 00:00:00 2001
From: Igor Wodiany <igor.wodiany at amd.com>
Date: Tue, 29 Sep 2026 10:13:37 +0100
Subject: [PATCH] [TableGen] Reuse `UnitMaskIdx` lambda in
 `computeRegUnitLaneMasks` (NFC)

This simplifies the code at the expense of losing an assert that
checks that one `SUI` matches more than one `RU`s.
---
 .../TableGen/Common/CodeGenRegisters.cpp      | 35 +++++++------------
 1 file changed, 12 insertions(+), 23 deletions(-)

diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index e1675ab68d20c..1da98db9cd4d1 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -2376,29 +2376,6 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
     // Iterate through SubRegisters.
     using SubRegMap = CodeGenRegister::SubRegMap;
     const SubRegMap &SubRegs = Register.getSubRegs();
-    for (auto [SubRegIndex, SubReg] : SubRegs) {
-      // Ignore non-leaf subregisters, their lane masks are fully covered by
-      // the leaf subregisters, unless the subregister is not CoveredBySubRegs -
-      // this is dealt with by the loop below.
-      if (!SubReg->getSubRegs().empty())
-        continue;
-      LaneBitmask LaneMask = SubRegIndex->LaneMask;
-      // Distribute LaneMask to Register Units touched.
-      for (unsigned SUI : SubReg->getRegUnits()) {
-        bool Found = false;
-        unsigned u = 0;
-        for (unsigned RU : RegUnits) {
-          if (SUI == RU) {
-            RegUnitLaneMasks[u] &= LaneMask;
-            assert(!Found);
-            Found = true;
-          }
-          ++u;
-        }
-        (void)Found;
-        assert(Found);
-      }
-    }
 
     auto UnitMaskIdx = [&](unsigned SUI) {
       unsigned U = 0;
@@ -2410,6 +2387,18 @@ void CodeGenRegBank::computeRegUnitLaneMasks() {
       llvm_unreachable("unit is not part of the register");
     };
 
+    for (auto [SubRegIndex, SubReg] : SubRegs) {
+      // Ignore non-leaf subregisters, their lane masks are fully covered by
+      // the leaf subregisters, unless the subregister is not CoveredBySubRegs -
+      // this is dealt with by the loop below.
+      if (!SubReg->getSubRegs().empty())
+        continue;
+      LaneBitmask LaneMask = SubRegIndex->LaneMask;
+      // Distribute LaneMask to Register Units touched.
+      for (unsigned SUI : SubReg->getRegUnits())
+        RegUnitLaneMasks[UnitMaskIdx(SUI)] &= LaneMask;
+    }
+
     // A sub-register that is not CoveredBySubRegs may be missing lanes that
     // none of its leaves account for. If left unclaimed, those lanes would
     // not appear in any register unit's mask, making them invisible to