[llvm] Mips: Mark MUL's existing HI0/LO0 defs dead in FastISel (PR #227230)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/227230

Instead of appending a second, dead pair of implicit defs on top of the
ones the instruction description already provides, set the dead flag on
the existing operands. This drops the duplicate operands and avoids
later re-inference of dead.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>

>From 99fb45632987ae637aff3bd8d8f7a7f8a4cdf4b3 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Tue, 29 Sep 2026 07:02:58 +0200
Subject: [PATCH] Mips: Mark MUL's existing HI0/LO0 defs dead in FastISel

Instead of appending a second, dead pair of implicit defs on top of the
ones the instruction description already provides, set the dead flag on
the existing operands. This drops the duplicate operands and avoids
later re-inference of dead.

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
---
 llvm/lib/Target/Mips/MipsFastISel.cpp         |  8 ++++----
 .../CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll   | 19 +++++++++++++++++++
 2 files changed, 23 insertions(+), 4 deletions(-)
 create mode 100644 llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll

diff --git a/llvm/lib/Target/Mips/MipsFastISel.cpp b/llvm/lib/Target/Mips/MipsFastISel.cpp
index 8e79160c131f3..7d1f024002eaf 100644
--- a/llvm/lib/Target/Mips/MipsFastISel.cpp
+++ b/llvm/lib/Target/Mips/MipsFastISel.cpp
@@ -2147,10 +2147,10 @@ unsigned MipsFastISel::fastEmitInst_rr(unsigned MachineInstOpcode,
     Op0 = constrainOperandRegClass(II, Op0, II.getNumDefs());
     Op1 = constrainOperandRegClass(II, Op1, II.getNumDefs() + 1);
     BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, MIMD, II, ResultReg)
-      .addReg(Op0)
-      .addReg(Op1)
-      .addReg(Mips::HI0, RegState::ImplicitDefine | RegState::Dead)
-      .addReg(Mips::LO0, RegState::ImplicitDefine | RegState::Dead);
+        .addReg(Op0)
+        .addReg(Op1)
+        .setOperandDead(3)  // implicit-def $hi0
+        .setOperandDead(4); // implicit-def $lo0
     return ResultReg;
   }
 
diff --git a/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll b/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
new file mode 100644
index 0000000000000..2f7e661f3d58f
--- /dev/null
+++ b/llvm/test/CodeGen/Mips/Fast-ISel/mul-dead-hilo.ll
@@ -0,0 +1,19 @@
+; NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+; RUN: llc -mtriple=mipsel -mcpu=mips32 -O0 -relocation-model=pic -stop-after=finalize-isel -o - < %s | FileCheck %s
+
+define i32 @mul(i32 %a, i32 %b) {
+  ; CHECK-LABEL: name: mul
+  ; CHECK: bb.0.entry:
+  ; CHECK-NEXT:   liveins: $a0, $a1
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:gpr32 = COPY $a1
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:gpr32 = COPY $a0
+  ; CHECK-NEXT:   [[COPY2:%[0-9]+]]:gpr32 = COPY killed [[COPY1]]
+  ; CHECK-NEXT:   [[COPY3:%[0-9]+]]:gpr32 = COPY killed [[COPY]]
+  ; CHECK-NEXT:   [[MUL:%[0-9]+]]:gpr32 = MUL [[COPY2]], [[COPY3]], implicit-def dead $hi0, implicit-def dead $lo0
+  ; CHECK-NEXT:   $v0 = COPY [[MUL]]
+  ; CHECK-NEXT:   RetRA implicit $v0
+entry:
+  %0 = mul i32 %a, %b
+  ret i32 %0
+}