[llvm] [RISCV][MC] Restrict mips.ldp / mips.sdp to RV64 only (PR #227043)

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llvmorg-github-actions[bot] wrote:


<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-mips

Author: Zeyi Xu (zeyi2)

<details>
<summary>Changes</summary>

The [P8700-F programmer’s guide](https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf#page=11) describes an RV64GCZbaZbb processor. Its [`mips.ldp`](https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf#page=355) writes two 64-bit values to two integer registers, while [`mips.sdp`](https://mips.com/wp-content/uploads/2025/11/P8700-F_Programmers_Reference_Manual-TM.pdf#page=364) takes a 64-bit value from each of two integer registers. 

Based on these info, this commit restricts their assembly and disassembly to RV64.

AI Usage: Amp (GPT 6 Sol) was used to help with tests.

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Full diff: https://github.com/llvm/llvm-project/pull/227043.diff


3 Files Affected:

- (modified) llvm/lib/Target/RISCV/RISCVInstrInfoXMips.td (+2) 
- (added) llvm/test/MC/Disassembler/RISCV/xmipslsp.txt (+19) 
- (modified) llvm/test/MC/RISCV/xmips-invalid.s (+8) 


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</details>


https://github.com/llvm/llvm-project/pull/227043