[llvm] AMDGPU: Mark SCC def dead in kill/demote lowering (PR #227024)

[Matt Arsenault via llvm-commits]

https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/227024

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>

>From 9fc9f0b887287ce0d56ad77bfd4ac22da52e5771 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Thu, 24 Sep 2026 23:25:05 +0200
Subject: [PATCH] AMDGPU: Mark SCC def dead in kill/demote lowering

Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
---
 llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp | 18 ++++++++++++------
 llvm/test/CodeGen/AMDGPU/wqm.mir           |  2 +-
 2 files changed, 13 insertions(+), 7 deletions(-)

diff --git a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
index 3c6e11acf89f9..cfd10e9a4d981 100644
--- a/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
+++ b/llvm/lib/Target/AMDGPU/SIWholeQuadMode.cpp
@@ -934,7 +934,8 @@ MachineInstr *SIWholeQuadMode::lowerKillF32(MachineInstr &MI) {
   MachineInstr *ExecMaskMI =
       BuildMI(MBB, MI, DL, TII->get(LMC.AndN2Opc), LMC.ExecReg)
           .addReg(LMC.ExecReg)
-          .addReg(LMC.VccReg);
+          .addReg(LMC.VccReg)
+          .setOperandDead(3);
 
   assert(MBB.succ_size() == 1);
 
@@ -994,7 +995,8 @@ MachineInstr *SIWholeQuadMode::lowerKillI1(MachineInstr &MI, bool IsWQM) {
       TmpReg = MRI->createVirtualRegister(TRI->getBoolRC());
       ComputeKilledMaskMI = BuildMI(MBB, MI, DL, TII->get(LMC.AndN2Opc), TmpReg)
                                 .addReg(LMC.ExecReg)
-                                .add(Op);
+                                .add(Op)
+                                .setOperandDead(3);
       MaskUpdateMI = BuildMI(MBB, MI, DL, TII->get(LMC.AndN2Opc), LiveMaskReg)
                          .addReg(LiveMaskReg)
                          .addReg(TmpReg);
@@ -1020,10 +1022,12 @@ MachineInstr *SIWholeQuadMode::lowerKillI1(MachineInstr &MI, bool IsWQM) {
     // Demote - deactivate quads with only helper lanes
     LiveMaskWQM = MRI->createVirtualRegister(TRI->getBoolRC());
     WQMMaskMI = BuildMI(MBB, MI, DL, TII->get(LMC.WQMOpc), LiveMaskWQM)
-                    .addReg(LiveMaskReg);
+                    .addReg(LiveMaskReg)
+                    .setOperandDead(2);
     NewTerm = BuildMI(MBB, MI, DL, TII->get(LMC.AndOpc), LMC.ExecReg)
                   .addReg(LMC.ExecReg)
-                  .addReg(LiveMaskWQM);
+                  .addReg(LiveMaskWQM)
+                  .setOperandDead(3);
   } else {
     // Kill - deactivate lanes no longer in live mask
     if (Op.isImm()) {
@@ -1032,12 +1036,14 @@ MachineInstr *SIWholeQuadMode::lowerKillI1(MachineInstr &MI, bool IsWQM) {
     } else if (!IsWQM) {
       NewTerm = BuildMI(MBB, &MI, DL, TII->get(LMC.AndOpc), LMC.ExecReg)
                     .addReg(LMC.ExecReg)
-                    .addReg(LiveMaskReg);
+                    .addReg(LiveMaskReg)
+                    .setOperandDead(3);
     } else {
       unsigned Opcode = KillVal ? LMC.AndN2Opc : LMC.AndOpc;
       NewTerm = BuildMI(MBB, &MI, DL, TII->get(Opcode), LMC.ExecReg)
                     .addReg(LMC.ExecReg)
-                    .add(Op);
+                    .add(Op)
+                    .setOperandDead(3);
     }
   }
 
diff --git a/llvm/test/CodeGen/AMDGPU/wqm.mir b/llvm/test/CodeGen/AMDGPU/wqm.mir
index 61acddb6b170b..e67cd1a146218 100644
--- a/llvm/test/CodeGen/AMDGPU/wqm.mir
+++ b/llvm/test/CodeGen/AMDGPU/wqm.mir
@@ -635,7 +635,7 @@ body:             |
   ; CHECK-NEXT:   V_CMP_NGT_F32_e32 0, [[COPY1]], implicit-def $vcc, implicit $mode, implicit $exec
   ; CHECK-NEXT:   dead [[COPY:%[0-9]+]]:sreg_64 = S_ANDN2_B64 [[COPY]], $vcc, implicit-def $scc
   ; CHECK-NEXT:   SI_EARLY_TERMINATE_SCC0 implicit $exec, implicit $scc
-  ; CHECK-NEXT:   $exec = S_ANDN2_B64_term $exec, $vcc, implicit-def $scc
+  ; CHECK-NEXT:   $exec = S_ANDN2_B64_term $exec, $vcc, implicit-def dead $scc
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT: bb.1:
   ; CHECK-NEXT:   $exec = S_AND_B64 $exec, [[COPY2]], implicit-def $scc