[llvm] [X86] Prefer 128-bit vectors for Bulldozer CPUs (PR #225838)
Aman Chadha via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 28 08:52:15 PDT 2026
https://github.com/ac-mmi updated https://github.com/llvm/llvm-project/pull/225838
>From c894d1121d4cd5d8fb0a5ac07c79a8b67cddccc0 Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Wed, 23 Sep 2026 21:54:38 +0530
Subject: [PATCH 01/10] [X86] Prefer 128-bit vectors for Bulldozer CPUs
---
llvm/lib/Target/X86/X86.td | 3 +-
llvm/test/CodeGen/X86/memset.ll | 2 +-
llvm/test/CodeGen/X86/slow-unaligned-mem.ll | 8 ++---
.../X86/bdver2-prefer-128-bit.ll | 36 +++++++++++++++++++
.../LoopVectorize/X86/intrinsiccost.ll | 4 +--
.../Transforms/SLPVectorizer/X86/PR32086.ll | 2 +-
.../Transforms/SLPVectorizer/X86/PR36280.ll | 2 +-
.../SLPVectorizer/X86/bitreverse.ll | 4 +--
.../X86/blending-shuffle-inseltpoison.ll | 2 +-
.../SLPVectorizer/X86/blending-shuffle.ll | 2 +-
.../X86/extract-shuffle-inseltpoison.ll | 2 +-
.../SLPVectorizer/X86/extract-shuffle.ll | 2 +-
.../test/Transforms/SLPVectorizer/X86/fabs.ll | 2 +-
.../Transforms/SLPVectorizer/X86/fcopysign.ll | 2 +-
llvm/test/Transforms/SLPVectorizer/X86/fma.ll | 2 +-
.../Transforms/SLPVectorizer/X86/fmaxnum.ll | 2 +-
.../Transforms/SLPVectorizer/X86/fminnum.ll | 2 +-
.../Transforms/SLPVectorizer/X86/fmuladd.ll | 2 +-
.../SLPVectorizer/X86/fptosi-inseltpoison.ll | 2 +-
.../Transforms/SLPVectorizer/X86/fptosi.ll | 2 +-
.../Transforms/SLPVectorizer/X86/fptoui.ll | 2 +-
.../SLPVectorizer/X86/horizontal-list.ll | 4 +--
.../Transforms/SLPVectorizer/X86/partail.ll | 2 +-
.../SLPVectorizer/X86/reduction_unrolled.ll | 2 +-
.../SLPVectorizer/X86/reorder_repeated_ops.ll | 2 +-
.../Transforms/SLPVectorizer/X86/resched.ll | 2 +-
.../X86/reused-extractelements.ll | 2 +-
.../SLPVectorizer/X86/schedule-bundle.ll | 2 +-
.../SLPVectorizer/X86/shift-ashr.ll | 2 +-
.../SLPVectorizer/X86/shift-lshr.ll | 2 +-
.../Transforms/SLPVectorizer/X86/shift-shl.ll | 2 +-
.../SLPVectorizer/X86/sitofp-inseltpoison.ll | 2 +-
.../Transforms/SLPVectorizer/X86/sitofp.ll | 2 +-
.../SLPVectorizer/X86/slp-fma-loss.ll | 2 +-
.../SLPVectorizer/X86/slp-throttle.ll | 2 +-
.../Transforms/SLPVectorizer/X86/uitofp.ll | 2 +-
.../SLPVectorizer/X86/undef_vect.ll | 2 +-
.../X86/vect_copyable_in_binops.ll | 4 +--
.../X86/vectorize-reorder-reuse.ll | 2 +-
39 files changed, 82 insertions(+), 45 deletions(-)
create mode 100644 llvm/test/Transforms/LoopVectorize/X86/bdver2-prefer-128-bit.ll
diff --git a/llvm/lib/Target/X86/X86.td b/llvm/lib/Target/X86/X86.td
index 237eb5d4be7cc..ec71b1a36123d 100644
--- a/llvm/lib/Target/X86/X86.td
+++ b/llvm/lib/Target/X86/X86.td
@@ -1630,7 +1630,8 @@ def ProcessorFeatures {
TuningFastScalarShiftMasks,
TuningBranchFusion,
TuningSBBDepBreaking,
- TuningInsertVZEROUPPER];
+ TuningInsertVZEROUPPER,
+ TuningPrefer128Bit];
// PileDriver
list<SubtargetFeature> BdVer2AdditionalFeatures = [FeatureF16C,
diff --git a/llvm/test/CodeGen/X86/memset.ll b/llvm/test/CodeGen/X86/memset.ll
index 910c73a5097e9..cdd7618d25222 100644
--- a/llvm/test/CodeGen/X86/memset.ll
+++ b/llvm/test/CodeGen/X86/memset.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mcpu=pentium3 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=XMM
-; RUN: llc < %s -mcpu=bdver1 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM
+; RUN: llc < %s -mcpu=bdver1 -mattr=-prefer-128-bit -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM
%struct.x = type { i16, i16 }
diff --git a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
index 4eea8354d72c6..6c257fd1e3934 100644
--- a/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
+++ b/llvm/test/CodeGen/X86/slow-unaligned-mem.ll
@@ -42,10 +42,10 @@
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=barcelona 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-SSE
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=btver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
-; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
-; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
-; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
-; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX128
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX128
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver3 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX128
+; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=bdver4 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX128
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver1 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver2 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
; RUN: llc < %s -mtriple=i386-unknown-unknown -mcpu=znver3 2>&1 | FileCheck %s --check-prefixes=FAST,FAST-AVX256
diff --git a/llvm/test/Transforms/LoopVectorize/X86/bdver2-prefer-128-bit.ll b/llvm/test/Transforms/LoopVectorize/X86/bdver2-prefer-128-bit.ll
new file mode 100644
index 0000000000000..09c00b7ee00d3
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/X86/bdver2-prefer-128-bit.ll
@@ -0,0 +1,36 @@
+; RUN: opt -mcpu=bdver2 -passes=loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREFER-128
+; RUN: opt -mcpu=bdver2 -mattr=-prefer-128-bit -passes=loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREFER-256
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; Bulldozer-family CPUs dual-pump 256-bit AVX ops as two 128-bit operations.
+; Prefer 128-bit vectorization by default (see TuningPrefer128Bit on BdVer1Tuning).
+
+; CHECK-LABEL: @test_loop(
+; CHECK: vector.body:
+; CHECK-PREFER-128: load <4 x float>
+; CHECK-PREFER-128-NOT: load <8 x float>
+; CHECK-PREFER-256: load <8 x float>
+
+define void @test_loop(ptr noalias nocapture readonly %in, ptr noalias nocapture writeonly %out, i32 %n, float %scale, float %bias) {
+entry:
+ %cmp = icmp eq i32 %n, 0
+ br i1 %cmp, label %exit, label %loop
+
+loop:
+ %i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
+ %idx = zext i32 %i to i64
+ %in.ptr = getelementptr inbounds float, ptr %in, i64 %idx
+ %val = load float, ptr %in.ptr, align 4
+ %mul = fmul float %val, %scale
+ %add = fadd float %mul, %bias
+ %out.ptr = getelementptr inbounds float, ptr %out, i64 %idx
+ store float %add, ptr %out.ptr, align 4
+ %i.next = add nuw i32 %i, 1
+ %cond = icmp eq i32 %i.next, %n
+ br i1 %cond, label %exit, label %loop
+
+exit:
+ ret void
+}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
index 9c7c1e353352b..d4dd56c892f9c 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mcpu=bdver1 -passes=loop-vectorize -S %s | FileCheck %s --check-prefix=CHECK
-; RUN: opt -mcpu=bdver1 -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST
+; RUN: opt -mcpu=bdver1 -mattr=-prefer-128-bit -passes=loop-vectorize -S %s | FileCheck %s --check-prefix=CHECK
+; RUN: opt -mcpu=bdver1 -mattr=-prefer-128-bit -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST
; REQUIRES: asserts
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll
index 14685fcca5107..0820144c902ec 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
define void @i64_simplified(ptr noalias %st, ptr noalias %ld) {
; CHECK-LABEL: @i64_simplified(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR36280.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR36280.ll
index 2142cd5668af8..e2fafbc6819e3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR36280.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR36280.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
define float @jacobi(ptr %p, float %x, float %y, float %z) {
; CHECK-LABEL: @jacobi(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/bitreverse.ll b/llvm/test/Transforms/SLPVectorizer/X86/bitreverse.ll
index 8311e75572d60..dcbbfb66abbec 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/bitreverse.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/bitreverse.ll
@@ -2,8 +2,8 @@
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=XOP
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver2 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=XOP
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
index e2a7966703c9d..0629077557f93 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @g(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
index 397d70dfc2455..fe53651e03e16 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @g(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll
index 74b9f31973d12..e241991310139 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -slp-schedule-budget=1 | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit -slp-schedule-budget=1 | FileCheck %s
define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @g(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle.ll
index 9276efb6e9cdc..f65c2b128138a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -slp-schedule-budget=1 | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit -slp-schedule-budget=1 | FileCheck %s
define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @g(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll b/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
index 4fbc7f01735d0..ee4bcd757aa5d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll b/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
index ee370e537983e..d783c0fcb71f0 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
index e1ad4acf0f25d..5efc7533eb57a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
index f134086a293e4..86b28f5390bb6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,COREI7
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,BDVER1
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,BDVER1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
index f890ca169f59c..37dd5424f2168 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,COREI7
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,BDVER1
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,BDVER1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
index 49a83f3e6f02b..e85c290acfbce 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
index 673114cc0321d..9f24f21370afa 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
index 159f310623554..8dd95eb2be72c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
index ae0905db4cfbe..de0da417a9ac5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512F
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
index 69822351ffd57..cc7fe4582f728 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 | FileCheck %s
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -slp-threshold=-10 | FileCheck %s --check-prefix=THRESHOLD
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit -slp-threshold=-10 | FileCheck %s --check-prefix=THRESHOLD
@n = external local_unnamed_addr global i32, align 4
@arr = common local_unnamed_addr global [20 x float] zeroinitializer, align 16
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/partail.ll b/llvm/test/Transforms/SLPVectorizer/X86/partail.ll
index f37b5c75eadbd..44c1293c9e128 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/partail.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/partail.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
define void @get_block(i32 %y_pos, i1 %arg, ptr %p) {
; CHECK-LABEL: @get_block(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
index 811e2d282ac71..cb242636b352d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -debug-only=SLP < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit -debug-only=SLP < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,AVX
; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug-only=SLP < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,SSE
; REQUIRES: asserts
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
index 5f2199aef17ee..0ac14f8a4c386 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/resched.ll b/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
index 35e6b797245d6..aeda0f0e6efb8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
%"struct.std::array" = type { [32 x i8] }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-extractelements.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-extractelements.ll
index 2f5936357d0f5..48278181e2956 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-extractelements.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-extractelements.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -pass-remarks-output=%t | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit -pass-remarks-output=%t | FileCheck %s
; RUN: FileCheck --input-file=%t --check-prefix=YAML %s
; YAML: --- !Missed
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll b/llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
index 26e62d36fb6a8..1c8644237df2a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=slp-vectorizer,slp-vectorizer -mcpu=bdver1 < %s | FileCheck %s
+; RUN: opt -S -passes=slp-vectorizer,slp-vectorizer -mcpu=bdver1 -mattr=-prefer-128-bit < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll b/llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
index e4f5e23f13279..dad69dbb39106 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
@@ -9,7 +9,7 @@
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX,AVX2
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
@a64 = common global [8 x i64] zeroinitializer, align 64
@b64 = common global [8 x i64] zeroinitializer, align 64
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll b/llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
index b859ea57f16e0..e3fab37884ecd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
@@ -9,7 +9,7 @@
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
@a64 = common global [8 x i64] zeroinitializer, align 64
@b64 = common global [8 x i64] zeroinitializer, align 64
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll b/llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
index c518a066c4f89..c1a35e95bc745 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
@@ -9,7 +9,7 @@
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
@a64 = common global [8 x i64] zeroinitializer, align 64
@b64 = common global [8 x i64] zeroinitializer, align 64
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
index 0866e56cf46b2..c66f5c115c61a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
index 316dfd0a76ff9..f04aba29461eb 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll b/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
index 1a7b3a9ff170c..4efcf57d3dd9e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=slp-vectorizer -S -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=SSE4
-; RUN: opt -passes=slp-vectorizer -S -mcpu=bdver2 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=AVX
+; RUN: opt -passes=slp-vectorizer -S -mcpu=bdver2 -mattr=-prefer-128-bit -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=AVX
; RUN: opt -passes=slp-vectorizer -S -mcpu=core-avx2 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=AVX2
; This test checks for a case when a horizontal reduction of floating-point
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll b/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
index faecdaee31f14..30a9d9485a2df 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
define void @rftbsub(ptr %a) {
; CHECK-LABEL: @rftbsub(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
index c978095422b5d..2dd375adf978e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX1
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll b/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
index 9c00c368bf0bd..032541e64b8b7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
%"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76" = type { i32, i32 }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll b/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
index 2893e6e02f29c..ccafff6ea921c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
define void @add0(ptr noalias %dst, ptr noalias %src) {
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
index 013db32992a04..a715a845c6d15 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
define i32 @foo(ptr nocapture readonly %arr, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) {
; CHECK-LABEL: @foo(
>From 472c139110381dc1ea3f11c02197cca47ea83311 Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Wed, 23 Sep 2026 22:33:35 +0530
Subject: [PATCH 02/10] [X86] Update vector width tests for Bulldozer
---
.../X86/bdver2-prefer-128-bit.ll | 36 ---
.../LoopVectorize/X86/intrinsiccost.ll | 88 +++----
.../LoopVectorize/X86/prefer-128-bit.ll | 247 ++++++++++++++++++
3 files changed, 291 insertions(+), 80 deletions(-)
delete mode 100644 llvm/test/Transforms/LoopVectorize/X86/bdver2-prefer-128-bit.ll
create mode 100644 llvm/test/Transforms/LoopVectorize/X86/prefer-128-bit.ll
diff --git a/llvm/test/Transforms/LoopVectorize/X86/bdver2-prefer-128-bit.ll b/llvm/test/Transforms/LoopVectorize/X86/bdver2-prefer-128-bit.ll
deleted file mode 100644
index 09c00b7ee00d3..0000000000000
--- a/llvm/test/Transforms/LoopVectorize/X86/bdver2-prefer-128-bit.ll
+++ /dev/null
@@ -1,36 +0,0 @@
-; RUN: opt -mcpu=bdver2 -passes=loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREFER-128
-; RUN: opt -mcpu=bdver2 -mattr=-prefer-128-bit -passes=loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREFER-256
-
-target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
-target triple = "x86_64-unknown-linux-gnu"
-
-; Bulldozer-family CPUs dual-pump 256-bit AVX ops as two 128-bit operations.
-; Prefer 128-bit vectorization by default (see TuningPrefer128Bit on BdVer1Tuning).
-
-; CHECK-LABEL: @test_loop(
-; CHECK: vector.body:
-; CHECK-PREFER-128: load <4 x float>
-; CHECK-PREFER-128-NOT: load <8 x float>
-; CHECK-PREFER-256: load <8 x float>
-
-define void @test_loop(ptr noalias nocapture readonly %in, ptr noalias nocapture writeonly %out, i32 %n, float %scale, float %bias) {
-entry:
- %cmp = icmp eq i32 %n, 0
- br i1 %cmp, label %exit, label %loop
-
-loop:
- %i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
- %idx = zext i32 %i to i64
- %in.ptr = getelementptr inbounds float, ptr %in, i64 %idx
- %val = load float, ptr %in.ptr, align 4
- %mul = fmul float %val, %scale
- %add = fadd float %mul, %bias
- %out.ptr = getelementptr inbounds float, ptr %out, i64 %idx
- store float %add, ptr %out.ptr, align 4
- %i.next = add nuw i32 %i, 1
- %cond = icmp eq i32 %i.next, %n
- br i1 %cond, label %exit, label %loop
-
-exit:
- ret void
-}
diff --git a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
index d4dd56c892f9c..53ef882cbf5da 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -mcpu=bdver1 -mattr=-prefer-128-bit -passes=loop-vectorize -S %s | FileCheck %s --check-prefix=CHECK
-; RUN: opt -mcpu=bdver1 -mattr=-prefer-128-bit -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST
+; RUN: opt -mcpu=bdver1 -passes=loop-vectorize -S %s | FileCheck %s --check-prefix=CHECK
+; RUN: opt -mcpu=bdver1 -passes=loop-vectorize -debug-only=loop-vectorize -disable-output %s 2>&1 | FileCheck %s --check-prefix=CHECK-COST
; REQUIRES: asserts
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -18,43 +18,43 @@ define void @uaddsat(ptr nocapture readonly %pSrc, i16 signext %offset, ptr noca
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
; CHECK: vector.main.loop.iter.check:
-; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 64
+; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 32
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 63
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 31
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
; CHECK-NEXT: [[DOTCAST1:%.*]] = trunc i64 [[N_VEC]] to i32
; CHECK-NEXT: [[IND_END10:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST1]]
; CHECK-NEXT: [[TMP12:%.*]] = shl i64 [[N_VEC]], 1
; CHECK-NEXT: [[IND_END12:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[TMP12]]
; CHECK-NEXT: [[IND_END15:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[TMP12]]
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i16> poison, i16 [[OFFSET:%.*]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i16> [[BROADCAST_SPLATINSERT]], <16 x i16> poison, <16 x i32> zeroinitializer
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i16> poison, i16 [[OFFSET:%.*]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT]], <8 x i16> poison, <8 x i32> zeroinitializer
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[OFFSET_IDX]]
; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[OFFSET_IDX]]
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 8
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 16
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 32
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 48
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i16>, ptr [[NEXT_GEP]], align 2
-; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <16 x i16>, ptr [[TMP1]], align 2
-; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <16 x i16>, ptr [[TMP2]], align 2
-; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <16 x i16>, ptr [[TMP3]], align 2
-; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD]], <16 x i16> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD4]], <16 x i16> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP6:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD5]], <16 x i16> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD6]], <16 x i16> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 24
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[NEXT_GEP]], align 2
+; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i16>, ptr [[TMP9]], align 2
+; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i16>, ptr [[TMP1]], align 2
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <8 x i16>, ptr [[TMP10]], align 2
+; CHECK-NEXT: [[TMP20:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD]], <8 x i16> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP21:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD3]], <8 x i16> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP13:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD4]], <8 x i16> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP22:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD5]], <8 x i16> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i16, ptr [[NEXT_GEP3]], i64 8
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i16, ptr [[NEXT_GEP3]], i64 16
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[NEXT_GEP3]], i64 32
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[NEXT_GEP3]], i64 48
-; CHECK-NEXT: store <16 x i16> [[TMP4]], ptr [[NEXT_GEP3]], align 2
-; CHECK-NEXT: store <16 x i16> [[TMP5]], ptr [[TMP8]], align 2
-; CHECK-NEXT: store <16 x i16> [[TMP6]], ptr [[TMP9]], align 2
-; CHECK-NEXT: store <16 x i16> [[TMP7]], ptr [[TMP10]], align 2
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 64
+; CHECK-NEXT: [[TMP23:%.*]] = getelementptr i16, ptr [[NEXT_GEP3]], i64 24
+; CHECK-NEXT: store <8 x i16> [[TMP20]], ptr [[NEXT_GEP3]], align 2
+; CHECK-NEXT: store <8 x i16> [[TMP21]], ptr [[TMP15]], align 2
+; CHECK-NEXT: store <8 x i16> [[TMP13]], ptr [[TMP8]], align 2
+; CHECK-NEXT: store <8 x i16> [[TMP22]], ptr [[TMP23]], align 2
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
; CHECK: middle.block:
@@ -144,41 +144,41 @@ define void @fshl(ptr nocapture readonly %pSrc, i8 signext %offset, ptr nocaptur
; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
; CHECK: vector.main.loop.iter.check:
-; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 128
+; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 64
; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
; CHECK: vector.ph:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 127
+; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 63
; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
; CHECK-NEXT: [[DOTCAST8:%.*]] = trunc i64 [[N_VEC]] to i32
; CHECK-NEXT: [[IND_END9:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST8]]
; CHECK-NEXT: [[IND_END11:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[N_VEC]]
; CHECK-NEXT: [[IND_END14:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[N_VEC]]
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <32 x i8> poison, i8 [[OFFSET:%.*]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <32 x i8> [[BROADCAST_SPLATINSERT]], <32 x i8> poison, <32 x i32> zeroinitializer
+; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[OFFSET:%.*]], i64 0
+; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer
; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
; CHECK: vector.body:
; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX]]
; CHECK-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX]]
+; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 16
; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 32
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 64
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 96
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <32 x i8>, ptr [[NEXT_GEP]], align 2
-; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <32 x i8>, ptr [[TMP1]], align 2
-; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <32 x i8>, ptr [[TMP2]], align 2
-; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <32 x i8>, ptr [[TMP3]], align 2
-; CHECK-NEXT: [[TMP4:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD]], <32 x i8> [[WIDE_LOAD]], <32 x i8> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP5:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD3]], <32 x i8> [[WIDE_LOAD3]], <32 x i8> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP6:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD4]], <32 x i8> [[WIDE_LOAD4]], <32 x i8> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP7:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD5]], <32 x i8> [[WIDE_LOAD5]], <32 x i8> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 48
+; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[NEXT_GEP]], align 2
+; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <16 x i8>, ptr [[TMP6]], align 2
+; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <16 x i8>, ptr [[TMP1]], align 2
+; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <16 x i8>, ptr [[TMP16]], align 2
+; CHECK-NEXT: [[TMP9:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD]], <16 x i8> [[WIDE_LOAD]], <16 x i8> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP10:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD3]], <16 x i8> [[WIDE_LOAD3]], <16 x i8> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP17:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD4]], <16 x i8> [[WIDE_LOAD4]], <16 x i8> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP18:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD5]], <16 x i8> [[WIDE_LOAD5]], <16 x i8> [[BROADCAST_SPLAT]])
+; CHECK-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 16
; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 32
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 64
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 96
-; CHECK-NEXT: store <32 x i8> [[TMP4]], ptr [[NEXT_GEP2]], align 2
-; CHECK-NEXT: store <32 x i8> [[TMP5]], ptr [[TMP8]], align 2
-; CHECK-NEXT: store <32 x i8> [[TMP6]], ptr [[TMP9]], align 2
-; CHECK-NEXT: store <32 x i8> [[TMP7]], ptr [[TMP10]], align 2
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 128
+; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 48
+; CHECK-NEXT: store <16 x i8> [[TMP9]], ptr [[NEXT_GEP2]], align 2
+; CHECK-NEXT: store <16 x i8> [[TMP10]], ptr [[TMP19]], align 2
+; CHECK-NEXT: store <16 x i8> [[TMP17]], ptr [[TMP8]], align 2
+; CHECK-NEXT: store <16 x i8> [[TMP18]], ptr [[TMP20]], align 2
+; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 64
; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; CHECK: middle.block:
diff --git a/llvm/test/Transforms/LoopVectorize/X86/prefer-128-bit.ll b/llvm/test/Transforms/LoopVectorize/X86/prefer-128-bit.ll
new file mode 100644
index 0000000000000..c1bb73f5aed5d
--- /dev/null
+++ b/llvm/test/Transforms/LoopVectorize/X86/prefer-128-bit.ll
@@ -0,0 +1,247 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -mcpu=bdver2 -passes=loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREFER-128
+; RUN: opt -mcpu=bdver2 -mattr=-prefer-128-bit -passes=loop-vectorize -S < %s | FileCheck %s --check-prefixes=CHECK,CHECK-PREFER-256
+
+target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128"
+target triple = "x86_64-unknown-linux-gnu"
+
+; Bulldozer-family CPUs dual-pump 256-bit AVX ops as two 128-bit operations.
+; Prefer 128-bit vectorization by default (see TuningPrefer128Bit on BdVer1Tuning).
+
+
+define void @test_loop(ptr noalias nocapture readonly %in, ptr noalias nocapture writeonly %out, i32 %n, float %scale, float %bias) {
+; CHECK-PREFER-128-LABEL: define void @test_loop(
+; CHECK-PREFER-128-SAME: ptr noalias readonly captures(none) [[IN:%.*]], ptr noalias writeonly captures(none) [[OUT:%.*]], i32 [[N:%.*]], float [[SCALE:%.*]], float [[BIAS:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-PREFER-128-NEXT: [[ENTRY:.*:]]
+; CHECK-PREFER-128-NEXT: [[CMP:%.*]] = icmp eq i32 [[N]], 0
+; CHECK-PREFER-128-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[ITER_CHECK:.*]]
+; CHECK-PREFER-128: [[ITER_CHECK]]:
+; CHECK-PREFER-128-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
+; CHECK-PREFER-128-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK-PREFER-128: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
+; CHECK-PREFER-128-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 16
+; CHECK-PREFER-128-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-PREFER-128: [[VECTOR_PH]]:
+; CHECK-PREFER-128-NEXT: [[TMP0:%.*]] = and i32 [[N]], 15
+; CHECK-PREFER-128-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[TMP0]]
+; CHECK-PREFER-128-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[SCALE]], i64 0
+; CHECK-PREFER-128-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-PREFER-128-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x float> poison, float [[BIAS]], i64 0
+; CHECK-PREFER-128-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT2]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-PREFER-128-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-PREFER-128: [[VECTOR_BODY]]:
+; CHECK-PREFER-128-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-PREFER-128-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64
+; CHECK-PREFER-128-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[IN]], i64 [[TMP1]]
+; CHECK-PREFER-128-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 4
+; CHECK-PREFER-128-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 8
+; CHECK-PREFER-128-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 12
+; CHECK-PREFER-128-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
+; CHECK-PREFER-128-NEXT: [[WIDE_LOAD4:%.*]] = load <4 x float>, ptr [[TMP3]], align 4
+; CHECK-PREFER-128-NEXT: [[WIDE_LOAD5:%.*]] = load <4 x float>, ptr [[TMP4]], align 4
+; CHECK-PREFER-128-NEXT: [[WIDE_LOAD6:%.*]] = load <4 x float>, ptr [[TMP5]], align 4
+; CHECK-PREFER-128-NEXT: [[TMP6:%.*]] = fmul <4 x float> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
+; CHECK-PREFER-128-NEXT: [[TMP7:%.*]] = fmul <4 x float> [[WIDE_LOAD4]], [[BROADCAST_SPLAT]]
+; CHECK-PREFER-128-NEXT: [[TMP8:%.*]] = fmul <4 x float> [[WIDE_LOAD5]], [[BROADCAST_SPLAT]]
+; CHECK-PREFER-128-NEXT: [[TMP9:%.*]] = fmul <4 x float> [[WIDE_LOAD6]], [[BROADCAST_SPLAT]]
+; CHECK-PREFER-128-NEXT: [[TMP10:%.*]] = fadd <4 x float> [[TMP6]], [[BROADCAST_SPLAT3]]
+; CHECK-PREFER-128-NEXT: [[TMP11:%.*]] = fadd <4 x float> [[TMP7]], [[BROADCAST_SPLAT3]]
+; CHECK-PREFER-128-NEXT: [[TMP12:%.*]] = fadd <4 x float> [[TMP8]], [[BROADCAST_SPLAT3]]
+; CHECK-PREFER-128-NEXT: [[TMP13:%.*]] = fadd <4 x float> [[TMP9]], [[BROADCAST_SPLAT3]]
+; CHECK-PREFER-128-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[OUT]], i64 [[TMP1]]
+; CHECK-PREFER-128-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 4
+; CHECK-PREFER-128-NEXT: [[TMP16:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 8
+; CHECK-PREFER-128-NEXT: [[TMP17:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 12
+; CHECK-PREFER-128-NEXT: store <4 x float> [[TMP10]], ptr [[TMP14]], align 4
+; CHECK-PREFER-128-NEXT: store <4 x float> [[TMP11]], ptr [[TMP15]], align 4
+; CHECK-PREFER-128-NEXT: store <4 x float> [[TMP12]], ptr [[TMP16]], align 4
+; CHECK-PREFER-128-NEXT: store <4 x float> [[TMP13]], ptr [[TMP17]], align 4
+; CHECK-PREFER-128-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 16
+; CHECK-PREFER-128-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-PREFER-128-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-PREFER-128: [[MIDDLE_BLOCK]]:
+; CHECK-PREFER-128-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
+; CHECK-PREFER-128-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
+; CHECK-PREFER-128: [[VEC_EPILOG_ITER_CHECK]]:
+; CHECK-PREFER-128-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP0]], 4
+; CHECK-PREFER-128-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
+; CHECK-PREFER-128: [[VEC_EPILOG_PH]]:
+; CHECK-PREFER-128-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; CHECK-PREFER-128-NEXT: [[TMP19:%.*]] = and i32 [[N]], 3
+; CHECK-PREFER-128-NEXT: [[N_VEC7:%.*]] = sub i32 [[N]], [[TMP19]]
+; CHECK-PREFER-128-NEXT: [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <4 x float> poison, float [[SCALE]], i64 0
+; CHECK-PREFER-128-NEXT: [[BROADCAST_SPLAT9:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT8]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-PREFER-128-NEXT: [[BROADCAST_SPLATINSERT10:%.*]] = insertelement <4 x float> poison, float [[BIAS]], i64 0
+; CHECK-PREFER-128-NEXT: [[BROADCAST_SPLAT11:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT10]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-PREFER-128-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]
+; CHECK-PREFER-128: [[VEC_EPILOG_VECTOR_BODY]]:
+; CHECK-PREFER-128-NEXT: [[INDEX12:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT14:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
+; CHECK-PREFER-128-NEXT: [[TMP20:%.*]] = zext i32 [[INDEX12]] to i64
+; CHECK-PREFER-128-NEXT: [[TMP21:%.*]] = getelementptr inbounds float, ptr [[IN]], i64 [[TMP20]]
+; CHECK-PREFER-128-NEXT: [[WIDE_LOAD13:%.*]] = load <4 x float>, ptr [[TMP21]], align 4
+; CHECK-PREFER-128-NEXT: [[TMP22:%.*]] = fmul <4 x float> [[WIDE_LOAD13]], [[BROADCAST_SPLAT9]]
+; CHECK-PREFER-128-NEXT: [[TMP23:%.*]] = fadd <4 x float> [[TMP22]], [[BROADCAST_SPLAT11]]
+; CHECK-PREFER-128-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[OUT]], i64 [[TMP20]]
+; CHECK-PREFER-128-NEXT: store <4 x float> [[TMP23]], ptr [[TMP24]], align 4
+; CHECK-PREFER-128-NEXT: [[INDEX_NEXT14]] = add nuw i32 [[INDEX12]], 4
+; CHECK-PREFER-128-NEXT: [[TMP25:%.*]] = icmp eq i32 [[INDEX_NEXT14]], [[N_VEC7]]
+; CHECK-PREFER-128-NEXT: br i1 [[TMP25]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-PREFER-128: [[VEC_EPILOG_MIDDLE_BLOCK]]:
+; CHECK-PREFER-128-NEXT: [[CMP_N15:%.*]] = icmp eq i32 [[N]], [[N_VEC7]]
+; CHECK-PREFER-128-NEXT: br i1 [[CMP_N15]], label %[[EXIT_LOOPEXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
+; CHECK-PREFER-128: [[VEC_EPILOG_SCALAR_PH]]:
+; CHECK-PREFER-128-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC7]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-PREFER-128-NEXT: br label %[[LOOP:.*]]
+; CHECK-PREFER-128: [[LOOP]]:
+; CHECK-PREFER-128-NEXT: [[I:%.*]] = phi i32 [ [[I_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ]
+; CHECK-PREFER-128-NEXT: [[IDX:%.*]] = zext i32 [[I]] to i64
+; CHECK-PREFER-128-NEXT: [[IN_PTR:%.*]] = getelementptr inbounds float, ptr [[IN]], i64 [[IDX]]
+; CHECK-PREFER-128-NEXT: [[VAL:%.*]] = load float, ptr [[IN_PTR]], align 4
+; CHECK-PREFER-128-NEXT: [[MUL:%.*]] = fmul float [[VAL]], [[SCALE]]
+; CHECK-PREFER-128-NEXT: [[ADD:%.*]] = fadd float [[MUL]], [[BIAS]]
+; CHECK-PREFER-128-NEXT: [[OUT_PTR:%.*]] = getelementptr inbounds float, ptr [[OUT]], i64 [[IDX]]
+; CHECK-PREFER-128-NEXT: store float [[ADD]], ptr [[OUT_PTR]], align 4
+; CHECK-PREFER-128-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-PREFER-128-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N]]
+; CHECK-PREFER-128-NEXT: br i1 [[COND]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-PREFER-128: [[EXIT_LOOPEXIT]]:
+; CHECK-PREFER-128-NEXT: br label %[[EXIT]]
+; CHECK-PREFER-128: [[EXIT]]:
+; CHECK-PREFER-128-NEXT: ret void
+;
+; CHECK-PREFER-256-LABEL: define void @test_loop(
+; CHECK-PREFER-256-SAME: ptr noalias readonly captures(none) [[IN:%.*]], ptr noalias writeonly captures(none) [[OUT:%.*]], i32 [[N:%.*]], float [[SCALE:%.*]], float [[BIAS:%.*]]) #[[ATTR0:[0-9]+]] {
+; CHECK-PREFER-256-NEXT: [[ENTRY:.*:]]
+; CHECK-PREFER-256-NEXT: [[CMP:%.*]] = icmp eq i32 [[N]], 0
+; CHECK-PREFER-256-NEXT: br i1 [[CMP]], label %[[EXIT:.*]], label %[[ITER_CHECK:.*]]
+; CHECK-PREFER-256: [[ITER_CHECK]]:
+; CHECK-PREFER-256-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i32 [[N]], 4
+; CHECK-PREFER-256-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH:.*]], label %[[VECTOR_MAIN_LOOP_ITER_CHECK:.*]]
+; CHECK-PREFER-256: [[VECTOR_MAIN_LOOP_ITER_CHECK]]:
+; CHECK-PREFER-256-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i32 [[N]], 32
+; CHECK-PREFER-256-NEXT: br i1 [[MIN_ITERS_CHECK1]], label %[[VEC_EPILOG_PH:.*]], label %[[VECTOR_PH:.*]]
+; CHECK-PREFER-256: [[VECTOR_PH]]:
+; CHECK-PREFER-256-NEXT: [[TMP0:%.*]] = and i32 [[N]], 31
+; CHECK-PREFER-256-NEXT: [[N_VEC:%.*]] = sub i32 [[N]], [[TMP0]]
+; CHECK-PREFER-256-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x float> poison, float [[SCALE]], i64 0
+; CHECK-PREFER-256-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT]], <8 x float> poison, <8 x i32> zeroinitializer
+; CHECK-PREFER-256-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <8 x float> poison, float [[BIAS]], i64 0
+; CHECK-PREFER-256-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <8 x float> [[BROADCAST_SPLATINSERT2]], <8 x float> poison, <8 x i32> zeroinitializer
+; CHECK-PREFER-256-NEXT: br label %[[VECTOR_BODY:.*]]
+; CHECK-PREFER-256: [[VECTOR_BODY]]:
+; CHECK-PREFER-256-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
+; CHECK-PREFER-256-NEXT: [[TMP1:%.*]] = zext i32 [[INDEX]] to i64
+; CHECK-PREFER-256-NEXT: [[TMP2:%.*]] = getelementptr inbounds float, ptr [[IN]], i64 [[TMP1]]
+; CHECK-PREFER-256-NEXT: [[TMP3:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 8
+; CHECK-PREFER-256-NEXT: [[TMP4:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 16
+; CHECK-PREFER-256-NEXT: [[TMP5:%.*]] = getelementptr inbounds float, ptr [[TMP2]], i64 24
+; CHECK-PREFER-256-NEXT: [[WIDE_LOAD:%.*]] = load <8 x float>, ptr [[TMP2]], align 4
+; CHECK-PREFER-256-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x float>, ptr [[TMP3]], align 4
+; CHECK-PREFER-256-NEXT: [[WIDE_LOAD5:%.*]] = load <8 x float>, ptr [[TMP4]], align 4
+; CHECK-PREFER-256-NEXT: [[WIDE_LOAD6:%.*]] = load <8 x float>, ptr [[TMP5]], align 4
+; CHECK-PREFER-256-NEXT: [[TMP6:%.*]] = fmul <8 x float> [[WIDE_LOAD]], [[BROADCAST_SPLAT]]
+; CHECK-PREFER-256-NEXT: [[TMP7:%.*]] = fmul <8 x float> [[WIDE_LOAD4]], [[BROADCAST_SPLAT]]
+; CHECK-PREFER-256-NEXT: [[TMP8:%.*]] = fmul <8 x float> [[WIDE_LOAD5]], [[BROADCAST_SPLAT]]
+; CHECK-PREFER-256-NEXT: [[TMP9:%.*]] = fmul <8 x float> [[WIDE_LOAD6]], [[BROADCAST_SPLAT]]
+; CHECK-PREFER-256-NEXT: [[TMP10:%.*]] = fadd <8 x float> [[TMP6]], [[BROADCAST_SPLAT3]]
+; CHECK-PREFER-256-NEXT: [[TMP11:%.*]] = fadd <8 x float> [[TMP7]], [[BROADCAST_SPLAT3]]
+; CHECK-PREFER-256-NEXT: [[TMP12:%.*]] = fadd <8 x float> [[TMP8]], [[BROADCAST_SPLAT3]]
+; CHECK-PREFER-256-NEXT: [[TMP13:%.*]] = fadd <8 x float> [[TMP9]], [[BROADCAST_SPLAT3]]
+; CHECK-PREFER-256-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[OUT]], i64 [[TMP1]]
+; CHECK-PREFER-256-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 8
+; CHECK-PREFER-256-NEXT: [[TMP16:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 16
+; CHECK-PREFER-256-NEXT: [[TMP17:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i64 24
+; CHECK-PREFER-256-NEXT: store <8 x float> [[TMP10]], ptr [[TMP14]], align 4
+; CHECK-PREFER-256-NEXT: store <8 x float> [[TMP11]], ptr [[TMP15]], align 4
+; CHECK-PREFER-256-NEXT: store <8 x float> [[TMP12]], ptr [[TMP16]], align 4
+; CHECK-PREFER-256-NEXT: store <8 x float> [[TMP13]], ptr [[TMP17]], align 4
+; CHECK-PREFER-256-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 32
+; CHECK-PREFER-256-NEXT: [[TMP18:%.*]] = icmp eq i32 [[INDEX_NEXT]], [[N_VEC]]
+; CHECK-PREFER-256-NEXT: br i1 [[TMP18]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; CHECK-PREFER-256: [[MIDDLE_BLOCK]]:
+; CHECK-PREFER-256-NEXT: [[CMP_N:%.*]] = icmp eq i32 [[N]], [[N_VEC]]
+; CHECK-PREFER-256-NEXT: br i1 [[CMP_N]], label %[[EXIT_LOOPEXIT:.*]], label %[[VEC_EPILOG_ITER_CHECK:.*]]
+; CHECK-PREFER-256: [[VEC_EPILOG_ITER_CHECK]]:
+; CHECK-PREFER-256-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i32 [[TMP0]], 4
+; CHECK-PREFER-256-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label %[[VEC_EPILOG_SCALAR_PH]], label %[[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
+; CHECK-PREFER-256: [[VEC_EPILOG_PH]]:
+; CHECK-PREFER-256-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; CHECK-PREFER-256-NEXT: [[TMP19:%.*]] = and i32 [[N]], 3
+; CHECK-PREFER-256-NEXT: [[N_VEC7:%.*]] = sub i32 [[N]], [[TMP19]]
+; CHECK-PREFER-256-NEXT: [[BROADCAST_SPLATINSERT8:%.*]] = insertelement <4 x float> poison, float [[SCALE]], i64 0
+; CHECK-PREFER-256-NEXT: [[BROADCAST_SPLAT9:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT8]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-PREFER-256-NEXT: [[BROADCAST_SPLATINSERT10:%.*]] = insertelement <4 x float> poison, float [[BIAS]], i64 0
+; CHECK-PREFER-256-NEXT: [[BROADCAST_SPLAT11:%.*]] = shufflevector <4 x float> [[BROADCAST_SPLATINSERT10]], <4 x float> poison, <4 x i32> zeroinitializer
+; CHECK-PREFER-256-NEXT: br label %[[VEC_EPILOG_VECTOR_BODY:.*]]
+; CHECK-PREFER-256: [[VEC_EPILOG_VECTOR_BODY]]:
+; CHECK-PREFER-256-NEXT: [[INDEX12:%.*]] = phi i32 [ [[VEC_EPILOG_RESUME_VAL]], %[[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT14:%.*]], %[[VEC_EPILOG_VECTOR_BODY]] ]
+; CHECK-PREFER-256-NEXT: [[TMP20:%.*]] = zext i32 [[INDEX12]] to i64
+; CHECK-PREFER-256-NEXT: [[TMP21:%.*]] = getelementptr inbounds float, ptr [[IN]], i64 [[TMP20]]
+; CHECK-PREFER-256-NEXT: [[WIDE_LOAD13:%.*]] = load <4 x float>, ptr [[TMP21]], align 4
+; CHECK-PREFER-256-NEXT: [[TMP22:%.*]] = fmul <4 x float> [[WIDE_LOAD13]], [[BROADCAST_SPLAT9]]
+; CHECK-PREFER-256-NEXT: [[TMP23:%.*]] = fadd <4 x float> [[TMP22]], [[BROADCAST_SPLAT11]]
+; CHECK-PREFER-256-NEXT: [[TMP24:%.*]] = getelementptr inbounds float, ptr [[OUT]], i64 [[TMP20]]
+; CHECK-PREFER-256-NEXT: store <4 x float> [[TMP23]], ptr [[TMP24]], align 4
+; CHECK-PREFER-256-NEXT: [[INDEX_NEXT14]] = add nuw i32 [[INDEX12]], 4
+; CHECK-PREFER-256-NEXT: [[TMP25:%.*]] = icmp eq i32 [[INDEX_NEXT14]], [[N_VEC7]]
+; CHECK-PREFER-256-NEXT: br i1 [[TMP25]], label %[[VEC_EPILOG_MIDDLE_BLOCK:.*]], label %[[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; CHECK-PREFER-256: [[VEC_EPILOG_MIDDLE_BLOCK]]:
+; CHECK-PREFER-256-NEXT: [[CMP_N15:%.*]] = icmp eq i32 [[N]], [[N_VEC7]]
+; CHECK-PREFER-256-NEXT: br i1 [[CMP_N15]], label %[[EXIT_LOOPEXIT]], label %[[VEC_EPILOG_SCALAR_PH]]
+; CHECK-PREFER-256: [[VEC_EPILOG_SCALAR_PH]]:
+; CHECK-PREFER-256-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[N_VEC7]], %[[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], %[[VEC_EPILOG_ITER_CHECK]] ], [ 0, %[[ITER_CHECK]] ]
+; CHECK-PREFER-256-NEXT: br label %[[LOOP:.*]]
+; CHECK-PREFER-256: [[LOOP]]:
+; CHECK-PREFER-256-NEXT: [[I:%.*]] = phi i32 [ [[I_NEXT:%.*]], %[[LOOP]] ], [ [[BC_RESUME_VAL]], %[[VEC_EPILOG_SCALAR_PH]] ]
+; CHECK-PREFER-256-NEXT: [[IDX:%.*]] = zext i32 [[I]] to i64
+; CHECK-PREFER-256-NEXT: [[IN_PTR:%.*]] = getelementptr inbounds float, ptr [[IN]], i64 [[IDX]]
+; CHECK-PREFER-256-NEXT: [[VAL:%.*]] = load float, ptr [[IN_PTR]], align 4
+; CHECK-PREFER-256-NEXT: [[MUL:%.*]] = fmul float [[VAL]], [[SCALE]]
+; CHECK-PREFER-256-NEXT: [[ADD:%.*]] = fadd float [[MUL]], [[BIAS]]
+; CHECK-PREFER-256-NEXT: [[OUT_PTR:%.*]] = getelementptr inbounds float, ptr [[OUT]], i64 [[IDX]]
+; CHECK-PREFER-256-NEXT: store float [[ADD]], ptr [[OUT_PTR]], align 4
+; CHECK-PREFER-256-NEXT: [[I_NEXT]] = add nuw i32 [[I]], 1
+; CHECK-PREFER-256-NEXT: [[COND:%.*]] = icmp eq i32 [[I_NEXT]], [[N]]
+; CHECK-PREFER-256-NEXT: br i1 [[COND]], label %[[EXIT_LOOPEXIT]], label %[[LOOP]], !llvm.loop [[LOOP5:![0-9]+]]
+; CHECK-PREFER-256: [[EXIT_LOOPEXIT]]:
+; CHECK-PREFER-256-NEXT: br label %[[EXIT]]
+; CHECK-PREFER-256: [[EXIT]]:
+; CHECK-PREFER-256-NEXT: ret void
+;
+entry:
+ %cmp = icmp eq i32 %n, 0
+ br i1 %cmp, label %exit, label %loop
+
+loop:
+ %i = phi i32 [ 0, %entry ], [ %i.next, %loop ]
+ %idx = zext i32 %i to i64
+ %in.ptr = getelementptr inbounds float, ptr %in, i64 %idx
+ %val = load float, ptr %in.ptr, align 4
+ %mul = fmul float %val, %scale
+ %add = fadd float %mul, %bias
+ %out.ptr = getelementptr inbounds float, ptr %out, i64 %idx
+ store float %add, ptr %out.ptr, align 4
+ %i.next = add nuw i32 %i, 1
+ %cond = icmp eq i32 %i.next, %n
+ br i1 %cond, label %exit, label %loop
+
+exit:
+ ret void
+}
+;.
+; CHECK-PREFER-128: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK-PREFER-128: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK-PREFER-128: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK-PREFER-128: [[PROF3]] = !{!"branch_weights", i32 4, i32 12}
+; CHECK-PREFER-128: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK-PREFER-128: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
+;.
+; CHECK-PREFER-256: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
+; CHECK-PREFER-256: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
+; CHECK-PREFER-256: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
+; CHECK-PREFER-256: [[PROF3]] = !{!"branch_weights", i32 4, i32 28}
+; CHECK-PREFER-256: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
+; CHECK-PREFER-256: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
+;.
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
>From 1374f8cacbd787631a3e302a94d72ea79e2c7bf8 Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Wed, 23 Sep 2026 23:47:45 +0530
Subject: [PATCH 03/10] [X86] Update tests for Bulldozer 128-bit vector
preference
---
llvm/test/CodeGen/X86/memset.ll | 19 ++--
.../Transforms/SLPVectorizer/X86/PR32086.ll | 2 +-
.../Transforms/SLPVectorizer/X86/PR36280.ll | 2 +-
.../SLPVectorizer/X86/bitreverse.ll | 40 +++++---
.../X86/blending-shuffle-inseltpoison.ll | 2 +-
.../SLPVectorizer/X86/blending-shuffle.ll | 2 +-
.../X86/extract-shuffle-inseltpoison.ll | 2 +-
.../SLPVectorizer/X86/extract-shuffle.ll | 2 +-
.../test/Transforms/SLPVectorizer/X86/fabs.ll | 42 +++-----
.../Transforms/SLPVectorizer/X86/fcopysign.ll | 50 +++-------
llvm/test/Transforms/SLPVectorizer/X86/fma.ll | 57 +++--------
.../Transforms/SLPVectorizer/X86/fmaxnum.ll | 1 -
.../Transforms/SLPVectorizer/X86/fminnum.ll | 1 -
.../Transforms/SLPVectorizer/X86/fmuladd.ll | 58 ++++-------
.../SLPVectorizer/X86/fptosi-inseltpoison.ll | 35 ++++---
.../Transforms/SLPVectorizer/X86/fptosi.ll | 35 ++++---
.../Transforms/SLPVectorizer/X86/fptoui.ll | 36 ++++---
.../SLPVectorizer/X86/horizontal-list.ll | 4 +-
.../Transforms/SLPVectorizer/X86/partail.ll | 2 +-
.../SLPVectorizer/X86/reduction_unrolled.ll | 2 +-
.../SLPVectorizer/X86/reorder_repeated_ops.ll | 4 +-
.../Transforms/SLPVectorizer/X86/resched.ll | 2 +-
.../X86/reused-extractelements.ll | 2 +-
.../SLPVectorizer/X86/schedule-bundle.ll | 2 +-
.../SLPVectorizer/X86/shift-lshr.ll | 98 ++++++++++++-------
.../Transforms/SLPVectorizer/X86/shift-shl.ll | 98 ++++++++++++-------
.../SLPVectorizer/X86/sitofp-inseltpoison.ll | 1 -
.../SLPVectorizer/X86/slp-fma-loss.ll | 2 +-
.../SLPVectorizer/X86/slp-throttle.ll | 2 +-
.../Transforms/SLPVectorizer/X86/uitofp.ll | 1 -
.../SLPVectorizer/X86/undef_vect.ll | 2 +-
.../X86/vect_copyable_in_binops.ll | 4 +-
.../X86/vectorize-reorder-reuse.ll | 2 +-
33 files changed, 321 insertions(+), 293 deletions(-)
diff --git a/llvm/test/CodeGen/X86/memset.ll b/llvm/test/CodeGen/X86/memset.ll
index cdd7618d25222..23defd10e37ca 100644
--- a/llvm/test/CodeGen/X86/memset.ll
+++ b/llvm/test/CodeGen/X86/memset.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mcpu=pentium2 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=X86
; RUN: llc < %s -mcpu=pentium3 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=XMM
-; RUN: llc < %s -mcpu=bdver1 -mattr=-prefer-128-bit -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM
+; RUN: llc < %s -mcpu=bdver1 -mtriple=i686-apple-darwin8.8.0 | FileCheck %s --check-prefix=YMM
%struct.x = type { i16, i16 }
@@ -40,9 +40,9 @@ define void @t() nounwind {
; YMM-NEXT: subl $60, %esp
; YMM-NEXT: leal {{[0-9]+}}(%esp), %eax
; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; YMM-NEXT: vmovups %ymm0, {{[0-9]+}}(%esp)
+; YMM-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
+; YMM-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
; YMM-NEXT: movl %eax, (%esp)
-; YMM-NEXT: vzeroupper
; YMM-NEXT: calll _foo
; YMM-NEXT: addl $60, %esp
; YMM-NEXT: retl
@@ -127,12 +127,13 @@ define void @PR83077(ptr %a) {
; YMM-LABEL: PR83077:
; YMM: ## %bb.0:
; YMM-NEXT: movl {{[0-9]+}}(%esp), %eax
-; YMM-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; YMM-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
-; YMM-NEXT: vmovups %ymm0, 58(%eax)
-; YMM-NEXT: vmovups %ymm0, 32(%eax)
-; YMM-NEXT: vmovups %ymm0, (%eax)
-; YMM-NEXT: vzeroupper
+; YMM-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; YMM-NEXT: vmovdqu %xmm0, 74(%eax)
+; YMM-NEXT: vmovdqu %xmm0, 64(%eax)
+; YMM-NEXT: vmovdqu %xmm0, 48(%eax)
+; YMM-NEXT: vmovdqu %xmm0, 32(%eax)
+; YMM-NEXT: vmovdqu %xmm0, 16(%eax)
+; YMM-NEXT: vmovdqu %xmm0, (%eax)
; YMM-NEXT: retl
call void @llvm.memset.p0.i32(ptr noundef nonnull align 4 dereferenceable(90) %a, i8 -1, i32 90, i1 false)
ret void
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll
index 0820144c902ec..14685fcca5107 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR32086.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 | FileCheck %s
define void @i64_simplified(ptr noalias %st, ptr noalias %ld) {
; CHECK-LABEL: @i64_simplified(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/PR36280.ll b/llvm/test/Transforms/SLPVectorizer/X86/PR36280.ll
index e2fafbc6819e3..2142cd5668af8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/PR36280.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/PR36280.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 | FileCheck %s
define float @jacobi(ptr %p, float %x, float %y, float %z) {
; CHECK-LABEL: @jacobi(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/bitreverse.ll b/llvm/test/Transforms/SLPVectorizer/X86/bitreverse.ll
index dcbbfb66abbec..c2cfe503f42f1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/bitreverse.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/bitreverse.ll
@@ -2,8 +2,8 @@
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver2 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=XOP
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=XOP
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
@@ -54,9 +54,12 @@ define void @bitreverse_4i64() #0 {
; AVX-NEXT: ret void
;
; XOP-LABEL: @bitreverse_4i64(
-; XOP-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 4
-; XOP-NEXT: [[TMP2:%.*]] = call <4 x i64> @llvm.bitreverse.v4i64(<4 x i64> [[TMP1]])
-; XOP-NEXT: store <4 x i64> [[TMP2]], ptr @dst64, align 4
+; XOP-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 4
+; XOP-NEXT: [[TMP2:%.*]] = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> [[TMP1]])
+; XOP-NEXT: store <2 x i64> [[TMP2]], ptr @dst64, align 4
+; XOP-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([4 x i64], ptr @src64, i64 0, i64 2), align 4
+; XOP-NEXT: [[TMP4:%.*]] = call <2 x i64> @llvm.bitreverse.v2i64(<2 x i64> [[TMP3]])
+; XOP-NEXT: store <2 x i64> [[TMP4]], ptr getelementptr inbounds ([4 x i64], ptr @dst64, i64 0, i64 2), align 4
; XOP-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 4
@@ -113,9 +116,12 @@ define void @bitreverse_8i32() #0 {
; AVX-NEXT: ret void
;
; XOP-LABEL: @bitreverse_8i32(
-; XOP-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 2
-; XOP-NEXT: [[TMP2:%.*]] = call <8 x i32> @llvm.bitreverse.v8i32(<8 x i32> [[TMP1]])
-; XOP-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 2
+; XOP-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 2
+; XOP-NEXT: [[TMP2:%.*]] = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> [[TMP1]])
+; XOP-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 2
+; XOP-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([8 x i32], ptr @src32, i32 0, i64 4), align 2
+; XOP-NEXT: [[TMP4:%.*]] = call <4 x i32> @llvm.bitreverse.v4i32(<4 x i32> [[TMP3]])
+; XOP-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([8 x i32], ptr @dst32, i32 0, i64 4), align 2
; XOP-NEXT: ret void
;
%ld0 = load i32, ptr @src32, align 2
@@ -196,9 +202,12 @@ define void @bitreverse_16i16() #0 {
; AVX-NEXT: ret void
;
; XOP-LABEL: @bitreverse_16i16(
-; XOP-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @src16, align 2
-; XOP-NEXT: [[TMP2:%.*]] = call <16 x i16> @llvm.bitreverse.v16i16(<16 x i16> [[TMP1]])
-; XOP-NEXT: store <16 x i16> [[TMP2]], ptr @dst16, align 2
+; XOP-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 2
+; XOP-NEXT: [[TMP2:%.*]] = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> [[TMP1]])
+; XOP-NEXT: store <8 x i16> [[TMP2]], ptr @dst16, align 2
+; XOP-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([16 x i16], ptr @src16, i16 0, i64 8), align 2
+; XOP-NEXT: [[TMP4:%.*]] = call <8 x i16> @llvm.bitreverse.v8i16(<8 x i16> [[TMP3]])
+; XOP-NEXT: store <8 x i16> [[TMP4]], ptr getelementptr inbounds ([16 x i16], ptr @dst16, i16 0, i64 8), align 2
; XOP-NEXT: ret void
;
%ld0 = load i16, ptr @src16, align 2
@@ -327,9 +336,12 @@ define void @bitreverse_32i8() #0 {
; AVX-NEXT: ret void
;
; XOP-LABEL: @bitreverse_32i8(
-; XOP-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @src8, align 1
-; XOP-NEXT: [[TMP2:%.*]] = call <32 x i8> @llvm.bitreverse.v32i8(<32 x i8> [[TMP1]])
-; XOP-NEXT: store <32 x i8> [[TMP2]], ptr @dst8, align 1
+; XOP-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @src8, align 1
+; XOP-NEXT: [[TMP2:%.*]] = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> [[TMP1]])
+; XOP-NEXT: store <16 x i8> [[TMP2]], ptr @dst8, align 1
+; XOP-NEXT: [[TMP3:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([32 x i8], ptr @src8, i8 0, i64 16), align 1
+; XOP-NEXT: [[TMP4:%.*]] = call <16 x i8> @llvm.bitreverse.v16i8(<16 x i8> [[TMP3]])
+; XOP-NEXT: store <16 x i8> [[TMP4]], ptr getelementptr inbounds ([32 x i8], ptr @dst8, i8 0, i64 16), align 1
; XOP-NEXT: ret void
;
%ld0 = load i8, ptr @src8, align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
index 0629077557f93..e2a7966703c9d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle-inseltpoison.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 | FileCheck %s
define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @g(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
index fe53651e03e16..397d70dfc2455 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/blending-shuffle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 | FileCheck %s
define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @g(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll
index e241991310139..74b9f31973d12 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle-inseltpoison.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit -slp-schedule-budget=1 | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -slp-schedule-budget=1 | FileCheck %s
define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @g(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle.ll b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle.ll
index f65c2b128138a..9276efb6e9cdc 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/extract-shuffle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit -slp-schedule-budget=1 | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -slp-schedule-budget=1 | FileCheck %s
define <2 x i8> @g(<2 x i8> %x, <2 x i8> %y) {
; CHECK-LABEL: @g(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll b/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
index ee4bcd757aa5d..b5c98613d740a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
@@ -50,11 +49,11 @@ define void @fabs_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fabs_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[TMP1]])
-; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 8
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fabs_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[TMP1]])
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -87,15 +86,6 @@ define void @fabs_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @fabs_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 4
-; AVX256-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[TMP1]])
-; AVX256-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 4
-; AVX256-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 4
-; AVX256-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[TMP3]])
-; AVX256-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; AVX256-NEXT: ret void
-;
; AVX512-LABEL: @fabs_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 4
; AVX512-NEXT: [[TMP2:%.*]] = call <8 x double> @llvm.fabs.v8f64(<8 x double> [[TMP1]])
@@ -161,11 +151,11 @@ define void @fabs_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fabs_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP1]])
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fabs_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP1]])
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -210,15 +200,6 @@ define void @fabs_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @fabs_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX256-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP1]])
-; AVX256-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 4
-; AVX256-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 8), align 4
-; AVX256-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP3]])
-; AVX256-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; AVX256-NEXT: ret void
-;
; AVX512-LABEL: @fabs_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @src32, align 4
; AVX512-NEXT: [[TMP2:%.*]] = call <16 x float> @llvm.fabs.v16f32(<16 x float> [[TMP1]])
@@ -277,3 +258,6 @@ define void @fabs_16f32() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
+; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll b/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
index d783c0fcb71f0..dc16571abb7a9 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256
@@ -59,12 +58,12 @@ define void @fcopysign_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fcopysign_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
-; AVX-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.copysign.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; AVX-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fcopysign_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX512-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.copysign.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
+; AVX512-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 8
@@ -105,17 +104,6 @@ define void @fcopysign_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @fcopysign_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; AVX256-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.copysign.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; AVX256-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 4
-; AVX256-NEXT: [[TMP4:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; AVX256-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; AVX256-NEXT: [[TMP6:%.*]] = call <4 x double> @llvm.copysign.v4f64(<4 x double> [[TMP4]], <4 x double> [[TMP5]])
-; AVX256-NEXT: store <4 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; AVX256-NEXT: ret void
-;
; AVX512-LABEL: @fcopysign_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
; AVX512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
@@ -197,12 +185,12 @@ define void @fcopysign_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fcopysign_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; AVX-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fcopysign_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
+; AVX512-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
@@ -259,17 +247,6 @@ define void @fcopysign_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @fcopysign_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX256-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; AVX256-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; AVX256-NEXT: [[TMP4:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; AVX256-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; AVX256-NEXT: [[TMP6:%.*]] = call <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP4]], <8 x float> [[TMP5]])
-; AVX256-NEXT: store <8 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; AVX256-NEXT: ret void
-;
; AVX512-LABEL: @fcopysign_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
; AVX512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
@@ -345,3 +322,6 @@ define void @fcopysign_16f32() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
+; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
index 5efc7533eb57a..4464b280f5532 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA --check-prefix=FMA256
@@ -87,13 +86,13 @@ define void @fma_4f64() #0 {
; NO-FMA-NEXT: store double [[FMA3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; NO-FMA-NEXT: ret void
;
-; FMA-LABEL: @fma_4f64(
-; FMA-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
-; FMA-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
-; FMA-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
-; FMA-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
-; FMA-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
-; FMA-NEXT: ret void
+; FMA512-LABEL: @fma_4f64(
+; FMA512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; FMA512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; FMA512-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
+; FMA512-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
+; FMA512-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
+; FMA512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 8
@@ -162,19 +161,6 @@ define void @fma_8f64() #0 {
; NO-FMA-NEXT: store double [[FMA7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 4
; NO-FMA-NEXT: ret void
;
-; FMA256-LABEL: @fma_8f64(
-; FMA256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; FMA256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; FMA256-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 4
-; FMA256-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
-; FMA256-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 4
-; FMA256-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; FMA256-NEXT: [[TMP6:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; FMA256-NEXT: [[TMP7:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 4), align 4
-; FMA256-NEXT: [[TMP8:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x double> [[TMP7]])
-; FMA256-NEXT: store <4 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; FMA256-NEXT: ret void
-;
; FMA512-LABEL: @fma_8f64(
; FMA512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
@@ -325,13 +311,13 @@ define void @fma_8f32() #0 {
; NO-FMA-NEXT: store float [[FMA7]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 7), align 4
; NO-FMA-NEXT: ret void
;
-; FMA-LABEL: @fma_8f32(
-; FMA-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; FMA-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; FMA-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
-; FMA-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
-; FMA-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
-; FMA-NEXT: ret void
+; FMA512-LABEL: @fma_8f32(
+; FMA512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; FMA512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; FMA512-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
+; FMA512-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
+; FMA512-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
+; FMA512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
@@ -460,19 +446,6 @@ define void @fma_16f32() #0 {
; NO-FMA-NEXT: store float [[FMA15]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 15), align 4
; NO-FMA-NEXT: ret void
;
-; FMA256-LABEL: @fma_16f32(
-; FMA256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; FMA256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; FMA256-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
-; FMA256-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
-; FMA256-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
-; FMA256-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; FMA256-NEXT: [[TMP6:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; FMA256-NEXT: [[TMP7:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 8), align 4
-; FMA256-NEXT: [[TMP8:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP5]], <8 x float> [[TMP6]], <8 x float> [[TMP7]])
-; FMA256-NEXT: store <8 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; FMA256-NEXT: ret void
-;
; FMA512-LABEL: @fma_16f32(
; FMA512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
@@ -565,3 +538,5 @@ define void @fma_16f32() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; FMA256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
index 86b28f5390bb6..f9c0b57826154 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,COREI7
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,BDVER1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
index 37dd5424f2168..a51c1df70aaf3 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,COREI7
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,BDVER1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
index e85c290acfbce..f5dcd28f312a5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
@@ -89,13 +88,13 @@ define void @fmuladd_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fmuladd_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
-; AVX-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
-; AVX-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
-; AVX-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fmuladd_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX512-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
+; AVX512-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
+; AVX512-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 8
@@ -144,19 +143,6 @@ define void @fmuladd_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP16]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @fmuladd_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; AVX256-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 4
-; AVX256-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
-; AVX256-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 4
-; AVX256-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; AVX256-NEXT: [[TMP6:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; AVX256-NEXT: [[TMP7:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 4), align 4
-; AVX256-NEXT: [[TMP8:%.*]] = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x double> [[TMP7]])
-; AVX256-NEXT: store <4 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; AVX256-NEXT: ret void
-;
; AVX512-LABEL: @fmuladd_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
; AVX512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
@@ -254,13 +240,13 @@ define void @fmuladd_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fmuladd_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
-; AVX-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
-; AVX-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fmuladd_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
+; AVX512-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
+; AVX512-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
@@ -329,19 +315,6 @@ define void @fmuladd_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP16]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @fmuladd_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX256-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
-; AVX256-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
-; AVX256-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
-; AVX256-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; AVX256-NEXT: [[TMP6:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; AVX256-NEXT: [[TMP7:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 8), align 4
-; AVX256-NEXT: [[TMP8:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP5]], <8 x float> [[TMP6]], <8 x float> [[TMP7]])
-; AVX256-NEXT: store <8 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; AVX256-NEXT: ret void
-;
; AVX512-LABEL: @fmuladd_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
; AVX512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
@@ -434,3 +407,6 @@ define void @fmuladd_16f32() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
+; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
index 9f24f21370afa..d78071f9a6463 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
@@ -130,11 +129,17 @@ define void @fptosi_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptosi_8f64_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fptosi_8f64_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f64_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -342,11 +347,17 @@ define void @fptosi_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptosi_8f32_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fptosi_8f32_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f32_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -488,3 +499,5 @@ define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3)
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
index 8dd95eb2be72c..7ceb28facf562 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=CHECK --check-prefix=AVX --check-prefix=AVX256DQ
@@ -130,11 +129,17 @@ define void @fptosi_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptosi_8f64_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fptosi_8f64_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f64_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -342,11 +347,17 @@ define void @fptosi_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptosi_8f32_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512-LABEL: @fptosi_8f32_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f32_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -488,3 +499,5 @@ define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3)
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
index de0da417a9ac5..6bfacfb7f2741 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512F
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256DQ
@@ -130,11 +130,17 @@ define void @fptoui_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptoui_8f64_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512F-LABEL: @fptoui_8f64_8i32(
+; AVX512F-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512F-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i32>
+; AVX512F-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512F-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptoui_8f64_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -342,11 +348,17 @@ define void @fptoui_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptoui_8f32_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX512F-LABEL: @fptoui_8f32_8i32(
+; AVX512F-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512F-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i32>
+; AVX512F-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512F-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptoui_8f32_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -444,3 +456,5 @@ define void @fptoui_8f32_8i8() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
index cc7fe4582f728..69822351ffd57 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/horizontal-list.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit -slp-threshold=-10 | FileCheck %s --check-prefix=THRESHOLD
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -slp-threshold=-10 | FileCheck %s --check-prefix=THRESHOLD
@n = external local_unnamed_addr global i32, align 4
@arr = common local_unnamed_addr global [20 x float] zeroinitializer, align 16
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/partail.ll b/llvm/test/Transforms/SLPVectorizer/X86/partail.ll
index 44c1293c9e128..f37b5c75eadbd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/partail.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/partail.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
define void @get_block(i32 %y_pos, i1 %arg, ptr %p) {
; CHECK-LABEL: @get_block(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll b/llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
index cb242636b352d..811e2d282ac71 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reduction_unrolled.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit -debug-only=SLP < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,AVX
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -debug-only=SLP < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,AVX
; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -S -mtriple=x86_64-unknown-linux-gnu -mcpu=core2 -debug-only=SLP < %s 2>&1 | FileCheck %s --check-prefixes=CHECK,SSE
; REQUIRES: asserts
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
index 0ac14f8a4c386..f6c6372b4915b 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
@@ -1,12 +1,12 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define void @hoge(i1 %arg) {
; CHECK-LABEL: @hoge(
; CHECK-NEXT: bb:
-; CHECK-NEXT: br i1 %arg, label [[BB1:%.*]], label [[BB2:%.*]]
+; CHECK-NEXT: br i1 [[ARG:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
; CHECK-NEXT: ret void
; CHECK: bb2:
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/resched.ll b/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
index aeda0f0e6efb8..35e6b797245d6 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/resched.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
%"struct.std::array" = type { [32 x i8] }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reused-extractelements.ll b/llvm/test/Transforms/SLPVectorizer/X86/reused-extractelements.ll
index 48278181e2956..2f5936357d0f5 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reused-extractelements.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reused-extractelements.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -mattr=-prefer-128-bit -pass-remarks-output=%t | FileCheck %s
+; RUN: opt < %s -passes=slp-vectorizer -S -o - -mtriple=x86_64-unknown-linux -mcpu=bdver2 -pass-remarks-output=%t | FileCheck %s
; RUN: FileCheck --input-file=%t --check-prefix=YAML %s
; YAML: --- !Missed
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll b/llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
index 1c8644237df2a..26e62d36fb6a8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/schedule-bundle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -S -passes=slp-vectorizer,slp-vectorizer -mcpu=bdver1 -mattr=-prefer-128-bit < %s | FileCheck %s
+; RUN: opt -S -passes=slp-vectorizer,slp-vectorizer -mcpu=bdver1 < %s | FileCheck %s
target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll b/llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
index e3fab37884ecd..cb463f8e6e1d8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shift-lshr.ll
@@ -9,7 +9,7 @@
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
@a64 = common global [8 x i64] zeroinitializer, align 64
@b64 = common global [8 x i64] zeroinitializer, align 64
@@ -63,14 +63,22 @@ define void @lshr_v8i64() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @lshr_v8i64(
-; XOP-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @a64, align 8
-; XOP-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr @b64, align 8
-; XOP-NEXT: [[TMP3:%.*]] = lshr <4 x i64> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <4 x i64> [[TMP3]], ptr @c64, align 8
-; XOP-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 4), align 8
-; XOP-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 4), align 8
-; XOP-NEXT: [[TMP6:%.*]] = lshr <4 x i64> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <4 x i64> [[TMP6]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @a64, align 8
+; XOP-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @b64, align 8
+; XOP-NEXT: [[TMP3:%.*]] = lshr <2 x i64> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <2 x i64> [[TMP3]], ptr @c64, align 8
+; XOP-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP6:%.*]] = lshr <2 x i64> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <2 x i64> [[TMP6]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP9:%.*]] = lshr <2 x i64> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <2 x i64> [[TMP9]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 6), align 8
+; XOP-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 6), align 8
+; XOP-NEXT: [[TMP12:%.*]] = lshr <2 x i64> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <2 x i64> [[TMP12]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 6), align 8
; XOP-NEXT: ret void
;
%a0 = load i64, ptr @a64, align 8
@@ -147,14 +155,22 @@ define void @lshr_v16i32() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @lshr_v16i32(
-; XOP-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @a32, align 4
-; XOP-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr @b32, align 4
-; XOP-NEXT: [[TMP3:%.*]] = lshr <8 x i32> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <8 x i32> [[TMP3]], ptr @c32, align 4
-; XOP-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 8), align 4
-; XOP-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 8), align 4
-; XOP-NEXT: [[TMP6:%.*]] = lshr <8 x i32> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <8 x i32> [[TMP6]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @a32, align 4
+; XOP-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @b32, align 4
+; XOP-NEXT: [[TMP3:%.*]] = lshr <4 x i32> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <4 x i32> [[TMP3]], ptr @c32, align 4
+; XOP-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP6:%.*]] = lshr <4 x i32> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <4 x i32> [[TMP6]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP9:%.*]] = lshr <4 x i32> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <4 x i32> [[TMP9]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 12), align 4
+; XOP-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 12), align 4
+; XOP-NEXT: [[TMP12:%.*]] = lshr <4 x i32> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <4 x i32> [[TMP12]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 12), align 4
; XOP-NEXT: ret void
;
%a0 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 0 ), align 4
@@ -263,14 +279,22 @@ define void @lshr_v32i16() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @lshr_v32i16(
-; XOP-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @a16, align 2
-; XOP-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @b16, align 2
-; XOP-NEXT: [[TMP3:%.*]] = lshr <16 x i16> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <16 x i16> [[TMP3]], ptr @c16, align 2
-; XOP-NEXT: [[TMP4:%.*]] = load <16 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 16), align 2
-; XOP-NEXT: [[TMP5:%.*]] = load <16 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 16), align 2
-; XOP-NEXT: [[TMP6:%.*]] = lshr <16 x i16> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <16 x i16> [[TMP6]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @a16, align 2
+; XOP-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @b16, align 2
+; XOP-NEXT: [[TMP3:%.*]] = lshr <8 x i16> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <8 x i16> [[TMP3]], ptr @c16, align 2
+; XOP-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP6:%.*]] = lshr <8 x i16> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <8 x i16> [[TMP6]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP7:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP8:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP9:%.*]] = lshr <8 x i16> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <8 x i16> [[TMP9]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP10:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 24), align 2
+; XOP-NEXT: [[TMP11:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 24), align 2
+; XOP-NEXT: [[TMP12:%.*]] = lshr <8 x i16> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <8 x i16> [[TMP12]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 24), align 2
; XOP-NEXT: ret void
;
%a0 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 0 ), align 2
@@ -443,14 +467,22 @@ define void @lshr_v64i8() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @lshr_v64i8(
-; XOP-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @a8, align 1
-; XOP-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr @b8, align 1
-; XOP-NEXT: [[TMP3:%.*]] = lshr <32 x i8> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <32 x i8> [[TMP3]], ptr @c8, align 1
-; XOP-NEXT: [[TMP4:%.*]] = load <32 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 32), align 1
-; XOP-NEXT: [[TMP5:%.*]] = load <32 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 32), align 1
-; XOP-NEXT: [[TMP6:%.*]] = lshr <32 x i8> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <32 x i8> [[TMP6]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @a8, align 1
+; XOP-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr @b8, align 1
+; XOP-NEXT: [[TMP3:%.*]] = lshr <16 x i8> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <16 x i8> [[TMP3]], ptr @c8, align 1
+; XOP-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP6:%.*]] = lshr <16 x i8> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <16 x i8> [[TMP6]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP9:%.*]] = lshr <16 x i8> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <16 x i8> [[TMP9]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 48), align 1
+; XOP-NEXT: [[TMP11:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 48), align 1
+; XOP-NEXT: [[TMP12:%.*]] = lshr <16 x i8> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <16 x i8> [[TMP12]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 48), align 1
; XOP-NEXT: ret void
;
%a0 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 0 ), align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll b/llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
index c1a35e95bc745..30cbfe9d2f1a1 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shift-shl.ll
@@ -9,7 +9,7 @@
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
@a64 = common global [8 x i64] zeroinitializer, align 64
@b64 = common global [8 x i64] zeroinitializer, align 64
@@ -63,14 +63,22 @@ define void @shl_v8i64() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @shl_v8i64(
-; XOP-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @a64, align 8
-; XOP-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr @b64, align 8
-; XOP-NEXT: [[TMP3:%.*]] = shl <4 x i64> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <4 x i64> [[TMP3]], ptr @c64, align 8
-; XOP-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 4), align 8
-; XOP-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 4), align 8
-; XOP-NEXT: [[TMP6:%.*]] = shl <4 x i64> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <4 x i64> [[TMP6]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @a64, align 8
+; XOP-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @b64, align 8
+; XOP-NEXT: [[TMP3:%.*]] = shl <2 x i64> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <2 x i64> [[TMP3]], ptr @c64, align 8
+; XOP-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP6:%.*]] = shl <2 x i64> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <2 x i64> [[TMP6]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP9:%.*]] = shl <2 x i64> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <2 x i64> [[TMP9]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 6), align 8
+; XOP-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 6), align 8
+; XOP-NEXT: [[TMP12:%.*]] = shl <2 x i64> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <2 x i64> [[TMP12]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 6), align 8
; XOP-NEXT: ret void
;
%a0 = load i64, ptr @a64, align 8
@@ -195,14 +203,22 @@ define void @shl_v16i32() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @shl_v16i32(
-; XOP-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @a32, align 4
-; XOP-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr @b32, align 4
-; XOP-NEXT: [[TMP3:%.*]] = shl <8 x i32> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <8 x i32> [[TMP3]], ptr @c32, align 4
-; XOP-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 8), align 4
-; XOP-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 8), align 4
-; XOP-NEXT: [[TMP6:%.*]] = shl <8 x i32> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <8 x i32> [[TMP6]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @a32, align 4
+; XOP-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @b32, align 4
+; XOP-NEXT: [[TMP3:%.*]] = shl <4 x i32> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <4 x i32> [[TMP3]], ptr @c32, align 4
+; XOP-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP6:%.*]] = shl <4 x i32> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <4 x i32> [[TMP6]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP9:%.*]] = shl <4 x i32> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <4 x i32> [[TMP9]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 12), align 4
+; XOP-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 12), align 4
+; XOP-NEXT: [[TMP12:%.*]] = shl <4 x i32> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <4 x i32> [[TMP12]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 12), align 4
; XOP-NEXT: ret void
;
%a0 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 0 ), align 4
@@ -311,14 +327,22 @@ define void @shl_v32i16() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @shl_v32i16(
-; XOP-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @a16, align 2
-; XOP-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @b16, align 2
-; XOP-NEXT: [[TMP3:%.*]] = shl <16 x i16> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <16 x i16> [[TMP3]], ptr @c16, align 2
-; XOP-NEXT: [[TMP4:%.*]] = load <16 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 16), align 2
-; XOP-NEXT: [[TMP5:%.*]] = load <16 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 16), align 2
-; XOP-NEXT: [[TMP6:%.*]] = shl <16 x i16> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <16 x i16> [[TMP6]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @a16, align 2
+; XOP-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @b16, align 2
+; XOP-NEXT: [[TMP3:%.*]] = shl <8 x i16> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <8 x i16> [[TMP3]], ptr @c16, align 2
+; XOP-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP6:%.*]] = shl <8 x i16> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <8 x i16> [[TMP6]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP7:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP8:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP9:%.*]] = shl <8 x i16> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <8 x i16> [[TMP9]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP10:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 24), align 2
+; XOP-NEXT: [[TMP11:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 24), align 2
+; XOP-NEXT: [[TMP12:%.*]] = shl <8 x i16> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <8 x i16> [[TMP12]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 24), align 2
; XOP-NEXT: ret void
;
%a0 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 0 ), align 2
@@ -491,14 +515,22 @@ define void @shl_v64i8() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @shl_v64i8(
-; XOP-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @a8, align 1
-; XOP-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr @b8, align 1
-; XOP-NEXT: [[TMP3:%.*]] = shl <32 x i8> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <32 x i8> [[TMP3]], ptr @c8, align 1
-; XOP-NEXT: [[TMP4:%.*]] = load <32 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 32), align 1
-; XOP-NEXT: [[TMP5:%.*]] = load <32 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 32), align 1
-; XOP-NEXT: [[TMP6:%.*]] = shl <32 x i8> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <32 x i8> [[TMP6]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @a8, align 1
+; XOP-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr @b8, align 1
+; XOP-NEXT: [[TMP3:%.*]] = shl <16 x i8> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <16 x i8> [[TMP3]], ptr @c8, align 1
+; XOP-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP6:%.*]] = shl <16 x i8> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <16 x i8> [[TMP6]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP9:%.*]] = shl <16 x i8> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <16 x i8> [[TMP9]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 48), align 1
+; XOP-NEXT: [[TMP11:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 48), align 1
+; XOP-NEXT: [[TMP12:%.*]] = shl <16 x i8> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <16 x i8> [[TMP12]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 48), align 1
; XOP-NEXT: ret void
;
%a0 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 0 ), align 1
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
index c66f5c115c61a..bc0df1378728f 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll b/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
index 4efcf57d3dd9e..1a7b3a9ff170c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/slp-fma-loss.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt -passes=slp-vectorizer -S -mcpu=corei7 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=SSE4
-; RUN: opt -passes=slp-vectorizer -S -mcpu=bdver2 -mattr=-prefer-128-bit -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=AVX
+; RUN: opt -passes=slp-vectorizer -S -mcpu=bdver2 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=AVX
; RUN: opt -passes=slp-vectorizer -S -mcpu=core-avx2 -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-2 < %s | FileCheck %s --check-prefixes=AVX2
; This test checks for a case when a horizontal reduction of floating-point
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll b/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
index 30a9d9485a2df..faecdaee31f14 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/slp-throttle.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
define void @rftbsub(ptr %a) {
; CHECK-LABEL: @rftbsub(
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
index 2dd375adf978e..9b9736b7fd50d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
@@ -1,7 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX1
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll b/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
index 032541e64b8b7..9c00c368bf0bd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/undef_vect.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-hor -slp-vectorize-hor-store -S < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 | FileCheck %s
%"struct.std::h.0.4.8.12.16.20.24.28.248.0.1.2.3.76" = type { i32, i32 }
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll b/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
index ccafff6ea921c..2893e6e02f29c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vect_copyable_in_binops.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
-; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2 -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -slp-vectorize-non-power-of-2=false -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
define void @add0(ptr noalias %dst, ptr noalias %src) {
;
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
index a715a845c6d15..013db32992a04 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/vectorize-reorder-reuse.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 -mattr=-prefer-128-bit < %s | FileCheck %s
+; RUN: opt -passes=slp-vectorizer -S -mtriple=x86_64-unknown-linux-gnu -mcpu=bdver2 < %s | FileCheck %s
define i32 @foo(ptr nocapture readonly %arr, i32 %a1, i32 %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6, i32 %a7, i32 %a8) {
; CHECK-LABEL: @foo(
>From 85caff4427d5d8ec16550e5f24b794fd650d2433 Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Thu, 24 Sep 2026 20:41:02 +0530
Subject: [PATCH 04/10] [X86] Update tests for Bulldozer 128-bit vector
preference
---
llvm/test/CodeGen/X86/memset.ll | 17 +-
.../LoopVectorize/X86/intrinsiccost.ll | 449 +++++++++++----
.../test/Transforms/SLPVectorizer/X86/fabs.ll | 84 ++-
.../Transforms/SLPVectorizer/X86/fcopysign.ll | 102 +++-
llvm/test/Transforms/SLPVectorizer/X86/fma.ll | 56 +-
.../Transforms/SLPVectorizer/X86/fmaxnum.ll | 102 +++-
.../Transforms/SLPVectorizer/X86/fminnum.ll | 102 +++-
.../Transforms/SLPVectorizer/X86/fmuladd.ll | 120 +++-
.../SLPVectorizer/X86/fptosi-inseltpoison.ll | 119 +++-
.../Transforms/SLPVectorizer/X86/fptosi.ll | 119 +++-
.../Transforms/SLPVectorizer/X86/fptoui.ll | 119 +++-
.../SLPVectorizer/X86/sitofp-inseltpoison.ll | 521 +++++++++++++++---
.../Transforms/SLPVectorizer/X86/sitofp.ll | 521 +++++++++++++++---
.../Transforms/SLPVectorizer/X86/uitofp.ll | 353 +++++++++++-
14 files changed, 2347 insertions(+), 437 deletions(-)
diff --git a/llvm/test/CodeGen/X86/memset.ll b/llvm/test/CodeGen/X86/memset.ll
index f0715151c51e2..d678fc1c18d86 100644
--- a/llvm/test/CodeGen/X86/memset.ll
+++ b/llvm/test/CodeGen/X86/memset.ll
@@ -41,9 +41,9 @@ define void @t() nounwind {
; AVX1-NEXT: subl $60, %esp
; AVX1-NEXT: leal {{[0-9]+}}(%esp), %eax
; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: vmovups %ymm0, {{[0-9]+}}(%esp)
+; AVX1-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
+; AVX1-NEXT: vmovaps %xmm0, {{[0-9]+}}(%esp)
; AVX1-NEXT: movl %eax, (%esp)
-; AVX1-NEXT: vzeroupper
; AVX1-NEXT: calll _foo
; AVX1-NEXT: addl $60, %esp
; AVX1-NEXT: retl
@@ -140,12 +140,13 @@ define void @PR83077(ptr %a) {
; AVX1-LABEL: PR83077:
; AVX1: ## %bb.0:
; AVX1-NEXT: movl {{[0-9]+}}(%esp), %eax
-; AVX1-NEXT: vxorps %xmm0, %xmm0, %xmm0
-; AVX1-NEXT: vcmptrueps %ymm0, %ymm0, %ymm0
-; AVX1-NEXT: vmovups %ymm0, 58(%eax)
-; AVX1-NEXT: vmovups %ymm0, 32(%eax)
-; AVX1-NEXT: vmovups %ymm0, (%eax)
-; AVX1-NEXT: vzeroupper
+; AVX1-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0
+; AVX1-NEXT: vmovdqu %xmm0, 74(%eax)
+; AVX1-NEXT: vmovdqu %xmm0, 64(%eax)
+; AVX1-NEXT: vmovdqu %xmm0, 48(%eax)
+; AVX1-NEXT: vmovdqu %xmm0, 32(%eax)
+; AVX1-NEXT: vmovdqu %xmm0, 16(%eax)
+; AVX1-NEXT: vmovdqu %xmm0, (%eax)
; AVX1-NEXT: retl
;
; AVX2-LABEL: PR83077:
diff --git a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
index daee52035f5a4..b4aed613d4162 100644
--- a/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
+++ b/llvm/test/Transforms/LoopVectorize/X86/intrinsiccost.ll
@@ -13,107 +13,311 @@ target triple = "x86_64-unknown-linux-gnu"
; CHECK-COST-LABEL: uaddsat
define void @uaddsat(ptr nocapture readonly %pSrc, i16 signext %offset, ptr nocapture noalias %pDst, i32 %blockSize) #0 {
-; CHECK-LABEL: @uaddsat(
-; CHECK-NEXT: entry:
-; CHECK-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
-; CHECK-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[ITER_CHECK:%.*]]
-; CHECK: iter.check:
-; CHECK-NEXT: [[TMP0:%.*]] = zext i32 [[BLOCKSIZE]] to i64
-; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
-; CHECK: vector.main.loop.iter.check:
-; CHECK-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 64
-; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
-; CHECK: vector.ph:
-; CHECK-NEXT: [[N_MOD_VF:%.*]] = and i64 [[TMP0]], 63
-; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]]
-; CHECK-NEXT: [[DOTCAST1:%.*]] = trunc i64 [[N_VEC]] to i32
-; CHECK-NEXT: [[IND_END10:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST1]]
-; CHECK-NEXT: [[TMP12:%.*]] = shl i64 [[N_VEC]], 1
-; CHECK-NEXT: [[IND_END12:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[TMP12]]
-; CHECK-NEXT: [[IND_END15:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[TMP12]]
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i16> poison, i16 [[OFFSET:%.*]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i16> [[BROADCAST_SPLATINSERT]], <16 x i16> poison, <16 x i32> zeroinitializer
-; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
-; CHECK: vector.body:
-; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
-; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1
-; CHECK-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[OFFSET_IDX]]
-; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 16
-; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 32
-; CHECK-NEXT: [[TMP3:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 48
-; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i16>, ptr [[NEXT_GEP]], align 2
-; CHECK-NEXT: [[WIDE_LOAD4:%.*]] = load <16 x i16>, ptr [[TMP1]], align 2
-; CHECK-NEXT: [[WIDE_LOAD5:%.*]] = load <16 x i16>, ptr [[TMP2]], align 2
-; CHECK-NEXT: [[WIDE_LOAD6:%.*]] = load <16 x i16>, ptr [[TMP3]], align 2
-; CHECK-NEXT: [[TMP4:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD]], <16 x i16> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP5:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD4]], <16 x i16> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP6:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD5]], <16 x i16> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP7:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD6]], <16 x i16> [[BROADCAST_SPLAT]])
-; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i16, ptr [[NEXT_GEP3]], i64 16
-; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[NEXT_GEP3]], i64 32
-; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[NEXT_GEP3]], i64 48
-; CHECK-NEXT: store <16 x i16> [[TMP4]], ptr [[NEXT_GEP3]], align 2
-; CHECK-NEXT: store <16 x i16> [[TMP5]], ptr [[TMP8]], align 2
-; CHECK-NEXT: store <16 x i16> [[TMP6]], ptr [[TMP9]], align 2
-; CHECK-NEXT: store <16 x i16> [[TMP7]], ptr [[TMP10]], align 2
-; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 64
-; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
-; CHECK: middle.block:
-; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
-; CHECK-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
-; CHECK: vec.epilog.iter.check:
-; CHECK-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_MOD_VF]], 8
-; CHECK-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
-; CHECK: vec.epilog.ph:
-; CHECK-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
-; CHECK-NEXT: [[N_MOD_VF6:%.*]] = and i64 [[TMP0]], 7
-; CHECK-NEXT: [[N_VEC8:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF6]]
-; CHECK-NEXT: [[DOTCAST:%.*]] = trunc i64 [[N_VEC8]] to i32
-; CHECK-NEXT: [[IND_END:%.*]] = sub i32 [[BLOCKSIZE]], [[DOTCAST]]
-; CHECK-NEXT: [[TMP14:%.*]] = shl i64 [[N_VEC8]], 1
-; CHECK-NEXT: [[IND_END11:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP14]]
-; CHECK-NEXT: [[IND_END14:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP14]]
-; CHECK-NEXT: [[BROADCAST_SPLATINSERT23:%.*]] = insertelement <8 x i16> poison, i16 [[OFFSET]], i64 0
-; CHECK-NEXT: [[BROADCAST_SPLAT24:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT23]], <8 x i16> poison, <8 x i32> zeroinitializer
-; CHECK-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
-; CHECK: vec.epilog.vector.body:
-; CHECK-NEXT: [[INDEX17:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT25:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
-; CHECK-NEXT: [[OFFSET_IDX18:%.*]] = shl i64 [[INDEX17]], 1
-; CHECK-NEXT: [[NEXT_GEP19:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[OFFSET_IDX18]]
-; CHECK-NEXT: [[NEXT_GEP21:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[OFFSET_IDX18]]
-; CHECK-NEXT: [[WIDE_LOAD22:%.*]] = load <8 x i16>, ptr [[NEXT_GEP19]], align 2
-; CHECK-NEXT: [[TMP16:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD22]], <8 x i16> [[BROADCAST_SPLAT24]])
-; CHECK-NEXT: store <8 x i16> [[TMP16]], ptr [[NEXT_GEP21]], align 2
-; CHECK-NEXT: [[INDEX_NEXT25]] = add nuw i64 [[INDEX17]], 8
-; CHECK-NEXT: [[TMP17:%.*]] = icmp eq i64 [[INDEX_NEXT25]], [[N_VEC8]]
-; CHECK-NEXT: br i1 [[TMP17]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
-; CHECK: vec.epilog.middle.block:
-; CHECK-NEXT: [[CMP_N16:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC8]]
-; CHECK-NEXT: br i1 [[CMP_N16]], label [[WHILE_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
-; CHECK: vec.epilog.scalar.ph:
-; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END10]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[BLOCKSIZE]], [[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL13:%.*]] = phi ptr [ [[IND_END11]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END12]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PSRC]], [[ITER_CHECK]] ]
-; CHECK-NEXT: [[BC_RESUME_VAL16:%.*]] = phi ptr [ [[IND_END14]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[IND_END15]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PDST]], [[ITER_CHECK]] ]
-; CHECK-NEXT: br label [[WHILE_BODY:%.*]]
-; CHECK: while.body:
-; CHECK-NEXT: [[BLKCNT_09:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ]
-; CHECK-NEXT: [[PSRC_ADDR_08:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL13]], [[VEC_EPILOG_SCALAR_PH]] ]
-; CHECK-NEXT: [[PDST_ADDR_07:%.*]] = phi ptr [ [[INCDEC_PTR3:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL16]], [[VEC_EPILOG_SCALAR_PH]] ]
-; CHECK-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16, ptr [[PSRC_ADDR_08]], i32 1
-; CHECK-NEXT: [[TMP18:%.*]] = load i16, ptr [[PSRC_ADDR_08]], align 2
-; CHECK-NEXT: [[TMP19:%.*]] = tail call i16 @llvm.uadd.sat.i16(i16 [[TMP18]], i16 [[OFFSET]])
-; CHECK-NEXT: [[INCDEC_PTR3]] = getelementptr inbounds i16, ptr [[PDST_ADDR_07]], i32 1
-; CHECK-NEXT: store i16 [[TMP19]], ptr [[PDST_ADDR_07]], align 2
-; CHECK-NEXT: [[DEC]] = add i32 [[BLKCNT_09]], -1
-; CHECK-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
-; CHECK-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT]], label [[WHILE_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
-; CHECK: while.end.loopexit:
-; CHECK-NEXT: br label [[WHILE_END]]
-; CHECK: while.end:
-; CHECK-NEXT: ret void
+; AVX1-LABEL: @uaddsat(
+; AVX1-NEXT: entry:
+; AVX1-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
+; AVX1-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[ITER_CHECK:%.*]]
+; AVX1: iter.check:
+; AVX1-NEXT: [[TMP0:%.*]] = zext i32 [[BLOCKSIZE]] to i64
+; AVX1-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
+; AVX1-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
+; AVX1: vector.main.loop.iter.check:
+; AVX1-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 64
+; AVX1-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
+; AVX1: vector.ph:
+; AVX1-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 63
+; AVX1-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; AVX1-NEXT: [[TMP2:%.*]] = trunc i64 [[N_VEC]] to i32
+; AVX1-NEXT: [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP2]]
+; AVX1-NEXT: [[TMP4:%.*]] = shl i64 [[N_VEC]], 1
+; AVX1-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[TMP4]]
+; AVX1-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[TMP4]]
+; AVX1-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i16> poison, i16 [[OFFSET:%.*]], i64 0
+; AVX1-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i16> [[BROADCAST_SPLATINSERT]], <16 x i16> poison, <16 x i32> zeroinitializer
+; AVX1-NEXT: br label [[VECTOR_BODY:%.*]]
+; AVX1: vector.body:
+; AVX1-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; AVX1-NEXT: [[TMP7:%.*]] = shl i64 [[INDEX]], 1
+; AVX1-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP7]]
+; AVX1-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP7]]
+; AVX1-NEXT: [[TMP8:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 16
+; AVX1-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 32
+; AVX1-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 48
+; AVX1-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i16>, ptr [[NEXT_GEP]], align 2
+; AVX1-NEXT: [[WIDE_LOAD3:%.*]] = load <16 x i16>, ptr [[TMP8]], align 2
+; AVX1-NEXT: [[WIDE_LOAD4:%.*]] = load <16 x i16>, ptr [[TMP9]], align 2
+; AVX1-NEXT: [[WIDE_LOAD5:%.*]] = load <16 x i16>, ptr [[TMP10]], align 2
+; AVX1-NEXT: [[TMP11:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD]], <16 x i16> [[BROADCAST_SPLAT]])
+; AVX1-NEXT: [[TMP12:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD3]], <16 x i16> [[BROADCAST_SPLAT]])
+; AVX1-NEXT: [[TMP13:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD4]], <16 x i16> [[BROADCAST_SPLAT]])
+; AVX1-NEXT: [[TMP14:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD5]], <16 x i16> [[BROADCAST_SPLAT]])
+; AVX1-NEXT: [[TMP15:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 16
+; AVX1-NEXT: [[TMP16:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 32
+; AVX1-NEXT: [[TMP17:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 48
+; AVX1-NEXT: store <16 x i16> [[TMP11]], ptr [[NEXT_GEP2]], align 2
+; AVX1-NEXT: store <16 x i16> [[TMP12]], ptr [[TMP15]], align 2
+; AVX1-NEXT: store <16 x i16> [[TMP13]], ptr [[TMP16]], align 2
+; AVX1-NEXT: store <16 x i16> [[TMP14]], ptr [[TMP17]], align 2
+; AVX1-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 64
+; AVX1-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; AVX1-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; AVX1: middle.block:
+; AVX1-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; AVX1-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
+; AVX1: vec.epilog.iter.check:
+; AVX1-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
+; AVX1-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
+; AVX1: vec.epilog.ph:
+; AVX1-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; AVX1-NEXT: [[TMP19:%.*]] = and i64 [[TMP0]], 7
+; AVX1-NEXT: [[N_VEC8:%.*]] = sub i64 [[TMP0]], [[TMP19]]
+; AVX1-NEXT: [[TMP20:%.*]] = trunc i64 [[N_VEC8]] to i32
+; AVX1-NEXT: [[TMP21:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP20]]
+; AVX1-NEXT: [[TMP22:%.*]] = shl i64 [[N_VEC8]], 1
+; AVX1-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP22]]
+; AVX1-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP22]]
+; AVX1-NEXT: [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <8 x i16> poison, i16 [[OFFSET]], i64 0
+; AVX1-NEXT: [[BROADCAST_SPLAT10:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT9]], <8 x i16> poison, <8 x i32> zeroinitializer
+; AVX1-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
+; AVX1: vec.epilog.vector.body:
+; AVX1-NEXT: [[INDEX11:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT15:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
+; AVX1-NEXT: [[TMP25:%.*]] = shl i64 [[INDEX11]], 1
+; AVX1-NEXT: [[NEXT_GEP12:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP25]]
+; AVX1-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP25]]
+; AVX1-NEXT: [[WIDE_LOAD14:%.*]] = load <8 x i16>, ptr [[NEXT_GEP12]], align 2
+; AVX1-NEXT: [[TMP26:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD14]], <8 x i16> [[BROADCAST_SPLAT10]])
+; AVX1-NEXT: store <8 x i16> [[TMP26]], ptr [[NEXT_GEP13]], align 2
+; AVX1-NEXT: [[INDEX_NEXT15]] = add nuw i64 [[INDEX11]], 8
+; AVX1-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT15]], [[N_VEC8]]
+; AVX1-NEXT: br i1 [[TMP27]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; AVX1: vec.epilog.middle.block:
+; AVX1-NEXT: [[CMP_N16:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC8]]
+; AVX1-NEXT: br i1 [[CMP_N16]], label [[WHILE_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
+; AVX1: vec.epilog.scalar.ph:
+; AVX1-NEXT: [[BC_RESUME_VAL17:%.*]] = phi i32 [ [[TMP21]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[BLOCKSIZE]], [[ITER_CHECK]] ]
+; AVX1-NEXT: [[BC_RESUME_VAL18:%.*]] = phi ptr [ [[TMP23]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP5]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PSRC]], [[ITER_CHECK]] ]
+; AVX1-NEXT: [[BC_RESUME_VAL19:%.*]] = phi ptr [ [[TMP24]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP6]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PDST]], [[ITER_CHECK]] ]
+; AVX1-NEXT: br label [[WHILE_BODY:%.*]]
+; AVX1: while.body:
+; AVX1-NEXT: [[BLKCNT_09:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL17]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX1-NEXT: [[PSRC_ADDR_08:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL18]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX1-NEXT: [[PDST_ADDR_07:%.*]] = phi ptr [ [[INCDEC_PTR3:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL19]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX1-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16, ptr [[PSRC_ADDR_08]], i32 1
+; AVX1-NEXT: [[TMP28:%.*]] = load i16, ptr [[PSRC_ADDR_08]], align 2
+; AVX1-NEXT: [[TMP29:%.*]] = tail call i16 @llvm.uadd.sat.i16(i16 [[TMP28]], i16 [[OFFSET]])
+; AVX1-NEXT: [[INCDEC_PTR3]] = getelementptr inbounds i16, ptr [[PDST_ADDR_07]], i32 1
+; AVX1-NEXT: store i16 [[TMP29]], ptr [[PDST_ADDR_07]], align 2
+; AVX1-NEXT: [[DEC]] = add i32 [[BLKCNT_09]], -1
+; AVX1-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
+; AVX1-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT]], label [[WHILE_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; AVX1: while.end.loopexit:
+; AVX1-NEXT: br label [[WHILE_END]]
+; AVX1: while.end:
+; AVX1-NEXT: ret void
+;
+; AVX2-LABEL: @uaddsat(
+; AVX2-NEXT: entry:
+; AVX2-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
+; AVX2-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[ITER_CHECK:%.*]]
+; AVX2: iter.check:
+; AVX2-NEXT: [[TMP0:%.*]] = zext i32 [[BLOCKSIZE]] to i64
+; AVX2-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
+; AVX2-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
+; AVX2: vector.main.loop.iter.check:
+; AVX2-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 64
+; AVX2-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
+; AVX2: vector.ph:
+; AVX2-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 63
+; AVX2-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; AVX2-NEXT: [[TMP2:%.*]] = trunc i64 [[N_VEC]] to i32
+; AVX2-NEXT: [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP2]]
+; AVX2-NEXT: [[TMP4:%.*]] = shl i64 [[N_VEC]], 1
+; AVX2-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[TMP4]]
+; AVX2-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[TMP4]]
+; AVX2-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i16> poison, i16 [[OFFSET:%.*]], i64 0
+; AVX2-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i16> [[BROADCAST_SPLATINSERT]], <16 x i16> poison, <16 x i32> zeroinitializer
+; AVX2-NEXT: br label [[VECTOR_BODY:%.*]]
+; AVX2: vector.body:
+; AVX2-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; AVX2-NEXT: [[TMP7:%.*]] = shl i64 [[INDEX]], 1
+; AVX2-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP7]]
+; AVX2-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP7]]
+; AVX2-NEXT: [[TMP8:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 16
+; AVX2-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 32
+; AVX2-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 48
+; AVX2-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i16>, ptr [[NEXT_GEP]], align 2
+; AVX2-NEXT: [[WIDE_LOAD3:%.*]] = load <16 x i16>, ptr [[TMP8]], align 2
+; AVX2-NEXT: [[WIDE_LOAD4:%.*]] = load <16 x i16>, ptr [[TMP9]], align 2
+; AVX2-NEXT: [[WIDE_LOAD5:%.*]] = load <16 x i16>, ptr [[TMP10]], align 2
+; AVX2-NEXT: [[TMP11:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD]], <16 x i16> [[BROADCAST_SPLAT]])
+; AVX2-NEXT: [[TMP12:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD3]], <16 x i16> [[BROADCAST_SPLAT]])
+; AVX2-NEXT: [[TMP13:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD4]], <16 x i16> [[BROADCAST_SPLAT]])
+; AVX2-NEXT: [[TMP14:%.*]] = call <16 x i16> @llvm.uadd.sat.v16i16(<16 x i16> [[WIDE_LOAD5]], <16 x i16> [[BROADCAST_SPLAT]])
+; AVX2-NEXT: [[TMP15:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 16
+; AVX2-NEXT: [[TMP16:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 32
+; AVX2-NEXT: [[TMP17:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 48
+; AVX2-NEXT: store <16 x i16> [[TMP11]], ptr [[NEXT_GEP2]], align 2
+; AVX2-NEXT: store <16 x i16> [[TMP12]], ptr [[TMP15]], align 2
+; AVX2-NEXT: store <16 x i16> [[TMP13]], ptr [[TMP16]], align 2
+; AVX2-NEXT: store <16 x i16> [[TMP14]], ptr [[TMP17]], align 2
+; AVX2-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 64
+; AVX2-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; AVX2-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; AVX2: middle.block:
+; AVX2-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; AVX2-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
+; AVX2: vec.epilog.iter.check:
+; AVX2-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
+; AVX2-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
+; AVX2: vec.epilog.ph:
+; AVX2-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; AVX2-NEXT: [[TMP19:%.*]] = and i64 [[TMP0]], 7
+; AVX2-NEXT: [[N_VEC8:%.*]] = sub i64 [[TMP0]], [[TMP19]]
+; AVX2-NEXT: [[TMP20:%.*]] = trunc i64 [[N_VEC8]] to i32
+; AVX2-NEXT: [[TMP21:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP20]]
+; AVX2-NEXT: [[TMP22:%.*]] = shl i64 [[N_VEC8]], 1
+; AVX2-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP22]]
+; AVX2-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP22]]
+; AVX2-NEXT: [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <8 x i16> poison, i16 [[OFFSET]], i64 0
+; AVX2-NEXT: [[BROADCAST_SPLAT10:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT9]], <8 x i16> poison, <8 x i32> zeroinitializer
+; AVX2-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
+; AVX2: vec.epilog.vector.body:
+; AVX2-NEXT: [[INDEX11:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT15:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
+; AVX2-NEXT: [[TMP25:%.*]] = shl i64 [[INDEX11]], 1
+; AVX2-NEXT: [[NEXT_GEP12:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP25]]
+; AVX2-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP25]]
+; AVX2-NEXT: [[WIDE_LOAD14:%.*]] = load <8 x i16>, ptr [[NEXT_GEP12]], align 2
+; AVX2-NEXT: [[TMP26:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD14]], <8 x i16> [[BROADCAST_SPLAT10]])
+; AVX2-NEXT: store <8 x i16> [[TMP26]], ptr [[NEXT_GEP13]], align 2
+; AVX2-NEXT: [[INDEX_NEXT15]] = add nuw i64 [[INDEX11]], 8
+; AVX2-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT15]], [[N_VEC8]]
+; AVX2-NEXT: br i1 [[TMP27]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; AVX2: vec.epilog.middle.block:
+; AVX2-NEXT: [[CMP_N16:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC8]]
+; AVX2-NEXT: br i1 [[CMP_N16]], label [[WHILE_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
+; AVX2: vec.epilog.scalar.ph:
+; AVX2-NEXT: [[BC_RESUME_VAL17:%.*]] = phi i32 [ [[TMP21]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[BLOCKSIZE]], [[ITER_CHECK]] ]
+; AVX2-NEXT: [[BC_RESUME_VAL18:%.*]] = phi ptr [ [[TMP23]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP5]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PSRC]], [[ITER_CHECK]] ]
+; AVX2-NEXT: [[BC_RESUME_VAL19:%.*]] = phi ptr [ [[TMP24]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP6]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PDST]], [[ITER_CHECK]] ]
+; AVX2-NEXT: br label [[WHILE_BODY:%.*]]
+; AVX2: while.body:
+; AVX2-NEXT: [[BLKCNT_09:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL17]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX2-NEXT: [[PSRC_ADDR_08:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL18]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX2-NEXT: [[PDST_ADDR_07:%.*]] = phi ptr [ [[INCDEC_PTR3:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL19]], [[VEC_EPILOG_SCALAR_PH]] ]
+; AVX2-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16, ptr [[PSRC_ADDR_08]], i32 1
+; AVX2-NEXT: [[TMP28:%.*]] = load i16, ptr [[PSRC_ADDR_08]], align 2
+; AVX2-NEXT: [[TMP29:%.*]] = tail call i16 @llvm.uadd.sat.i16(i16 [[TMP28]], i16 [[OFFSET]])
+; AVX2-NEXT: [[INCDEC_PTR3]] = getelementptr inbounds i16, ptr [[PDST_ADDR_07]], i32 1
+; AVX2-NEXT: store i16 [[TMP29]], ptr [[PDST_ADDR_07]], align 2
+; AVX2-NEXT: [[DEC]] = add i32 [[BLKCNT_09]], -1
+; AVX2-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
+; AVX2-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT]], label [[WHILE_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; AVX2: while.end.loopexit:
+; AVX2-NEXT: br label [[WHILE_END]]
+; AVX2: while.end:
+; AVX2-NEXT: ret void
+;
+; XOP-LABEL: @uaddsat(
+; XOP-NEXT: entry:
+; XOP-NEXT: [[CMP_NOT6:%.*]] = icmp eq i32 [[BLOCKSIZE:%.*]], 0
+; XOP-NEXT: br i1 [[CMP_NOT6]], label [[WHILE_END:%.*]], label [[ITER_CHECK:%.*]]
+; XOP: iter.check:
+; XOP-NEXT: [[TMP0:%.*]] = zext i32 [[BLOCKSIZE]] to i64
+; XOP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
+; XOP-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
+; XOP: vector.main.loop.iter.check:
+; XOP-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 32
+; XOP-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
+; XOP: vector.ph:
+; XOP-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 31
+; XOP-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]]
+; XOP-NEXT: [[TMP2:%.*]] = trunc i64 [[N_VEC]] to i32
+; XOP-NEXT: [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP2]]
+; XOP-NEXT: [[TMP4:%.*]] = shl i64 [[N_VEC]], 1
+; XOP-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[TMP4]]
+; XOP-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[TMP4]]
+; XOP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <8 x i16> poison, i16 [[OFFSET:%.*]], i64 0
+; XOP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT]], <8 x i16> poison, <8 x i32> zeroinitializer
+; XOP-NEXT: br label [[VECTOR_BODY:%.*]]
+; XOP: vector.body:
+; XOP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
+; XOP-NEXT: [[TMP7:%.*]] = shl i64 [[INDEX]], 1
+; XOP-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP7]]
+; XOP-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP7]]
+; XOP-NEXT: [[TMP8:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 8
+; XOP-NEXT: [[TMP9:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 16
+; XOP-NEXT: [[TMP10:%.*]] = getelementptr i16, ptr [[NEXT_GEP]], i64 24
+; XOP-NEXT: [[WIDE_LOAD:%.*]] = load <8 x i16>, ptr [[NEXT_GEP]], align 2
+; XOP-NEXT: [[WIDE_LOAD3:%.*]] = load <8 x i16>, ptr [[TMP8]], align 2
+; XOP-NEXT: [[WIDE_LOAD4:%.*]] = load <8 x i16>, ptr [[TMP9]], align 2
+; XOP-NEXT: [[WIDE_LOAD5:%.*]] = load <8 x i16>, ptr [[TMP10]], align 2
+; XOP-NEXT: [[TMP11:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD]], <8 x i16> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP12:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD3]], <8 x i16> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP13:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD4]], <8 x i16> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP14:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD5]], <8 x i16> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP15:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 8
+; XOP-NEXT: [[TMP16:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 16
+; XOP-NEXT: [[TMP17:%.*]] = getelementptr i16, ptr [[NEXT_GEP2]], i64 24
+; XOP-NEXT: store <8 x i16> [[TMP11]], ptr [[NEXT_GEP2]], align 2
+; XOP-NEXT: store <8 x i16> [[TMP12]], ptr [[TMP15]], align 2
+; XOP-NEXT: store <8 x i16> [[TMP13]], ptr [[TMP16]], align 2
+; XOP-NEXT: store <8 x i16> [[TMP14]], ptr [[TMP17]], align 2
+; XOP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32
+; XOP-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
+; XOP-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
+; XOP: middle.block:
+; XOP-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]]
+; XOP-NEXT: br i1 [[CMP_N]], label [[WHILE_END_LOOPEXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]]
+; XOP: vec.epilog.iter.check:
+; XOP-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8
+; XOP-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]], !prof [[PROF3:![0-9]+]]
+; XOP: vec.epilog.ph:
+; XOP-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ]
+; XOP-NEXT: [[TMP19:%.*]] = and i64 [[TMP0]], 7
+; XOP-NEXT: [[N_VEC8:%.*]] = sub i64 [[TMP0]], [[TMP19]]
+; XOP-NEXT: [[TMP20:%.*]] = trunc i64 [[N_VEC8]] to i32
+; XOP-NEXT: [[TMP21:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP20]]
+; XOP-NEXT: [[TMP22:%.*]] = shl i64 [[N_VEC8]], 1
+; XOP-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP22]]
+; XOP-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP22]]
+; XOP-NEXT: [[BROADCAST_SPLATINSERT9:%.*]] = insertelement <8 x i16> poison, i16 [[OFFSET]], i64 0
+; XOP-NEXT: [[BROADCAST_SPLAT10:%.*]] = shufflevector <8 x i16> [[BROADCAST_SPLATINSERT9]], <8 x i16> poison, <8 x i32> zeroinitializer
+; XOP-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]]
+; XOP: vec.epilog.vector.body:
+; XOP-NEXT: [[INDEX11:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT15:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ]
+; XOP-NEXT: [[TMP25:%.*]] = shl i64 [[INDEX11]], 1
+; XOP-NEXT: [[NEXT_GEP12:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[TMP25]]
+; XOP-NEXT: [[NEXT_GEP13:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[TMP25]]
+; XOP-NEXT: [[WIDE_LOAD14:%.*]] = load <8 x i16>, ptr [[NEXT_GEP12]], align 2
+; XOP-NEXT: [[TMP26:%.*]] = call <8 x i16> @llvm.uadd.sat.v8i16(<8 x i16> [[WIDE_LOAD14]], <8 x i16> [[BROADCAST_SPLAT10]])
+; XOP-NEXT: store <8 x i16> [[TMP26]], ptr [[NEXT_GEP13]], align 2
+; XOP-NEXT: [[INDEX_NEXT15]] = add nuw i64 [[INDEX11]], 8
+; XOP-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT15]], [[N_VEC8]]
+; XOP-NEXT: br i1 [[TMP27]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]]
+; XOP: vec.epilog.middle.block:
+; XOP-NEXT: [[CMP_N16:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC8]]
+; XOP-NEXT: br i1 [[CMP_N16]], label [[WHILE_END_LOOPEXIT]], label [[VEC_EPILOG_SCALAR_PH]]
+; XOP: vec.epilog.scalar.ph:
+; XOP-NEXT: [[BC_RESUME_VAL17:%.*]] = phi i32 [ [[TMP21]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP3]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[BLOCKSIZE]], [[ITER_CHECK]] ]
+; XOP-NEXT: [[BC_RESUME_VAL18:%.*]] = phi ptr [ [[TMP23]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP5]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PSRC]], [[ITER_CHECK]] ]
+; XOP-NEXT: [[BC_RESUME_VAL19:%.*]] = phi ptr [ [[TMP24]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[TMP6]], [[VEC_EPILOG_ITER_CHECK]] ], [ [[PDST]], [[ITER_CHECK]] ]
+; XOP-NEXT: br label [[WHILE_BODY:%.*]]
+; XOP: while.body:
+; XOP-NEXT: [[BLKCNT_09:%.*]] = phi i32 [ [[DEC:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL17]], [[VEC_EPILOG_SCALAR_PH]] ]
+; XOP-NEXT: [[PSRC_ADDR_08:%.*]] = phi ptr [ [[INCDEC_PTR:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL18]], [[VEC_EPILOG_SCALAR_PH]] ]
+; XOP-NEXT: [[PDST_ADDR_07:%.*]] = phi ptr [ [[INCDEC_PTR3:%.*]], [[WHILE_BODY]] ], [ [[BC_RESUME_VAL19]], [[VEC_EPILOG_SCALAR_PH]] ]
+; XOP-NEXT: [[INCDEC_PTR]] = getelementptr inbounds i16, ptr [[PSRC_ADDR_08]], i32 1
+; XOP-NEXT: [[TMP28:%.*]] = load i16, ptr [[PSRC_ADDR_08]], align 2
+; XOP-NEXT: [[TMP29:%.*]] = tail call i16 @llvm.uadd.sat.i16(i16 [[TMP28]], i16 [[OFFSET]])
+; XOP-NEXT: [[INCDEC_PTR3]] = getelementptr inbounds i16, ptr [[PDST_ADDR_07]], i32 1
+; XOP-NEXT: store i16 [[TMP29]], ptr [[PDST_ADDR_07]], align 2
+; XOP-NEXT: [[DEC]] = add i32 [[BLKCNT_09]], -1
+; XOP-NEXT: [[CMP_NOT:%.*]] = icmp eq i32 [[DEC]], 0
+; XOP-NEXT: br i1 [[CMP_NOT]], label [[WHILE_END_LOOPEXIT]], label [[WHILE_BODY]], !llvm.loop [[LOOP5:![0-9]+]]
+; XOP: while.end.loopexit:
+; XOP-NEXT: br label [[WHILE_END]]
+; XOP: while.end:
+; XOP-NEXT: ret void
;
entry:
%cmp.not6 = icmp eq i32 %blockSize, 0
@@ -314,41 +518,41 @@ define void @fshl(ptr nocapture readonly %pSrc, i8 signext %offset, ptr nocaptur
; XOP-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 8
; XOP-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]]
; XOP: vector.main.loop.iter.check:
-; XOP-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 128
+; XOP-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 [[TMP0]], 64
; XOP-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]]
; XOP: vector.ph:
-; XOP-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 127
+; XOP-NEXT: [[TMP1:%.*]] = and i64 [[TMP0]], 63
; XOP-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP1]]
; XOP-NEXT: [[TMP2:%.*]] = trunc i64 [[N_VEC]] to i32
; XOP-NEXT: [[TMP3:%.*]] = sub i32 [[BLOCKSIZE]], [[TMP2]]
; XOP-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[PSRC:%.*]], i64 [[N_VEC]]
; XOP-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[PDST:%.*]], i64 [[N_VEC]]
-; XOP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <32 x i8> poison, i8 [[OFFSET:%.*]], i64 0
-; XOP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <32 x i8> [[BROADCAST_SPLATINSERT]], <32 x i8> poison, <32 x i32> zeroinitializer
+; XOP-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i8> poison, i8 [[OFFSET:%.*]], i64 0
+; XOP-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i8> [[BROADCAST_SPLATINSERT]], <16 x i8> poison, <16 x i32> zeroinitializer
; XOP-NEXT: br label [[VECTOR_BODY:%.*]]
; XOP: vector.body:
; XOP-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
; XOP-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[PSRC]], i64 [[INDEX]]
; XOP-NEXT: [[NEXT_GEP2:%.*]] = getelementptr i8, ptr [[PDST]], i64 [[INDEX]]
+; XOP-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 16
; XOP-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 32
-; XOP-NEXT: [[TMP7:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 64
-; XOP-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 96
-; XOP-NEXT: [[WIDE_LOAD:%.*]] = load <32 x i8>, ptr [[NEXT_GEP]], align 2
-; XOP-NEXT: [[WIDE_LOAD3:%.*]] = load <32 x i8>, ptr [[TMP6]], align 2
-; XOP-NEXT: [[WIDE_LOAD4:%.*]] = load <32 x i8>, ptr [[TMP7]], align 2
-; XOP-NEXT: [[WIDE_LOAD5:%.*]] = load <32 x i8>, ptr [[TMP8]], align 2
-; XOP-NEXT: [[TMP9:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD]], <32 x i8> [[WIDE_LOAD]], <32 x i8> [[BROADCAST_SPLAT]])
-; XOP-NEXT: [[TMP10:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD3]], <32 x i8> [[WIDE_LOAD3]], <32 x i8> [[BROADCAST_SPLAT]])
-; XOP-NEXT: [[TMP11:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD4]], <32 x i8> [[WIDE_LOAD4]], <32 x i8> [[BROADCAST_SPLAT]])
-; XOP-NEXT: [[TMP12:%.*]] = call <32 x i8> @llvm.fshl.v32i8(<32 x i8> [[WIDE_LOAD5]], <32 x i8> [[WIDE_LOAD5]], <32 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[NEXT_GEP]], i64 48
+; XOP-NEXT: [[WIDE_LOAD:%.*]] = load <16 x i8>, ptr [[NEXT_GEP]], align 2
+; XOP-NEXT: [[WIDE_LOAD3:%.*]] = load <16 x i8>, ptr [[TMP7]], align 2
+; XOP-NEXT: [[WIDE_LOAD4:%.*]] = load <16 x i8>, ptr [[TMP6]], align 2
+; XOP-NEXT: [[WIDE_LOAD5:%.*]] = load <16 x i8>, ptr [[TMP8]], align 2
+; XOP-NEXT: [[TMP9:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD]], <16 x i8> [[WIDE_LOAD]], <16 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP10:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD3]], <16 x i8> [[WIDE_LOAD3]], <16 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP11:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD4]], <16 x i8> [[WIDE_LOAD4]], <16 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP12:%.*]] = call <16 x i8> @llvm.fshl.v16i8(<16 x i8> [[WIDE_LOAD5]], <16 x i8> [[WIDE_LOAD5]], <16 x i8> [[BROADCAST_SPLAT]])
+; XOP-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 16
; XOP-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 32
-; XOP-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 64
-; XOP-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 96
-; XOP-NEXT: store <32 x i8> [[TMP9]], ptr [[NEXT_GEP2]], align 2
-; XOP-NEXT: store <32 x i8> [[TMP10]], ptr [[TMP13]], align 2
-; XOP-NEXT: store <32 x i8> [[TMP11]], ptr [[TMP14]], align 2
-; XOP-NEXT: store <32 x i8> [[TMP12]], ptr [[TMP15]], align 2
-; XOP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 128
+; XOP-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[NEXT_GEP2]], i64 48
+; XOP-NEXT: store <16 x i8> [[TMP9]], ptr [[NEXT_GEP2]], align 2
+; XOP-NEXT: store <16 x i8> [[TMP10]], ptr [[TMP14]], align 2
+; XOP-NEXT: store <16 x i8> [[TMP11]], ptr [[TMP13]], align 2
+; XOP-NEXT: store <16 x i8> [[TMP12]], ptr [[TMP15]], align 2
+; XOP-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 64
; XOP-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]]
; XOP-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]]
; XOP: middle.block:
@@ -426,4 +630,5 @@ while.end:
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; CHECK: {{.*}}
; CHECK-COST: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll b/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
index 5f83d5e172c6e..a3a0d97f6add7 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fabs.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
@@ -50,11 +50,26 @@ define void @fabs_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fabs_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[TMP1]])
-; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 8
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fabs_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @src64, align 8
+; AVX128-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[TMP1]])
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 8
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[TMP3]])
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fabs_4f64(
+; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX256-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[TMP1]])
+; AVX256-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 8
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fabs_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[TMP1]])
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -87,6 +102,21 @@ define void @fabs_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fabs_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @src64, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[TMP1]])
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[TMP3]])
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[TMP5]])
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[TMP7]])
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fabs_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 4
; AVX256-NEXT: [[TMP2:%.*]] = call <4 x double> @llvm.fabs.v4f64(<4 x double> [[TMP1]])
@@ -161,11 +191,26 @@ define void @fabs_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fabs_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP1]])
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fabs_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP1]])
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP3]])
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fabs_8f32(
+; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP1]])
+; AVX256-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 4
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fabs_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP1]])
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -210,6 +255,21 @@ define void @fabs_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fabs_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP1]])
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP3]])
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP5]])
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = call <4 x float> @llvm.fabs.v4f32(<4 x float> [[TMP7]])
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fabs_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
; AVX256-NEXT: [[TMP2:%.*]] = call <8 x float> @llvm.fabs.v8f32(<8 x float> [[TMP1]])
@@ -277,3 +337,5 @@ define void @fabs_16f32() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll b/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
index fda4998772c83..37d821573714e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fcopysign.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
@@ -59,12 +59,30 @@ define void @fcopysign_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fcopysign_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
-; AVX-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.copysign.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; AVX-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fcopysign_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
+; AVX128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
+; AVX128-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.copysign.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; AVX128-NEXT: store <2 x double> [[TMP3]], ptr @dst64, align 8
+; AVX128-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.copysign.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP5]])
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fcopysign_4f64(
+; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX256-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.copysign.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
+; AVX256-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fcopysign_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX512-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.copysign.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
+; AVX512-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 8
@@ -105,6 +123,25 @@ define void @fcopysign_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fcopysign_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.copysign.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; AVX128-NEXT: store <2 x double> [[TMP3]], ptr @dst64, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.copysign.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP5]])
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP9:%.*]] = call <2 x double> @llvm.copysign.v2f64(<2 x double> [[TMP7]], <2 x double> [[TMP8]])
+; AVX128-NEXT: store <2 x double> [[TMP9]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP12:%.*]] = call <2 x double> @llvm.copysign.v2f64(<2 x double> [[TMP10]], <2 x double> [[TMP11]])
+; AVX128-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fcopysign_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
@@ -197,12 +234,30 @@ define void @fcopysign_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fcopysign_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; AVX-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fcopysign_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; AVX128-NEXT: store <4 x float> [[TMP3]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fcopysign_8f32(
+; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX256-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
+; AVX256-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fcopysign_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.copysign.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
+; AVX512-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
@@ -259,6 +314,25 @@ define void @fcopysign_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fcopysign_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; AVX128-NEXT: store <4 x float> [[TMP3]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP9:%.*]] = call <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP7]], <4 x float> [[TMP8]])
+; AVX128-NEXT: store <4 x float> [[TMP9]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP10:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP11:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP12:%.*]] = call <4 x float> @llvm.copysign.v4f32(<4 x float> [[TMP10]], <4 x float> [[TMP11]])
+; AVX128-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fcopysign_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
@@ -345,3 +419,5 @@ define void @fcopysign_16f32() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
index bec493efe4774..0dcb43e7a467a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
@@ -87,13 +87,13 @@ define void @fma_4f64() #0 {
; NO-FMA-NEXT: store double [[FMA3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; NO-FMA-NEXT: ret void
;
-; FMA-LABEL: @fma_4f64(
-; FMA-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
-; FMA-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
-; FMA-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
-; FMA-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
-; FMA-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
-; FMA-NEXT: ret void
+; FMA512-LABEL: @fma_4f64(
+; FMA512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; FMA512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; FMA512-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
+; FMA512-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
+; FMA512-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
+; FMA512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 8
@@ -162,19 +162,6 @@ define void @fma_8f64() #0 {
; NO-FMA-NEXT: store double [[FMA7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 4
; NO-FMA-NEXT: ret void
;
-; FMA256-LABEL: @fma_8f64(
-; FMA256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
-; FMA256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
-; FMA256-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 4
-; FMA256-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
-; FMA256-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 4
-; FMA256-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
-; FMA256-NEXT: [[TMP6:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
-; FMA256-NEXT: [[TMP7:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 4), align 4
-; FMA256-NEXT: [[TMP8:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x double> [[TMP7]])
-; FMA256-NEXT: store <4 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
-; FMA256-NEXT: ret void
-;
; FMA512-LABEL: @fma_8f64(
; FMA512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
@@ -325,13 +312,13 @@ define void @fma_8f32() #0 {
; NO-FMA-NEXT: store float [[FMA7]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 7), align 4
; NO-FMA-NEXT: ret void
;
-; FMA-LABEL: @fma_8f32(
-; FMA-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; FMA-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; FMA-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
-; FMA-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
-; FMA-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
-; FMA-NEXT: ret void
+; FMA512-LABEL: @fma_8f32(
+; FMA512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; FMA512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; FMA512-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
+; FMA512-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
+; FMA512-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
+; FMA512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
@@ -460,19 +447,6 @@ define void @fma_16f32() #0 {
; NO-FMA-NEXT: store float [[FMA15]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 15), align 4
; NO-FMA-NEXT: ret void
;
-; FMA256-LABEL: @fma_16f32(
-; FMA256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; FMA256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; FMA256-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
-; FMA256-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
-; FMA256-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
-; FMA256-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
-; FMA256-NEXT: [[TMP6:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
-; FMA256-NEXT: [[TMP7:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 8), align 4
-; FMA256-NEXT: [[TMP8:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP5]], <8 x float> [[TMP6]], <8 x float> [[TMP7]])
-; FMA256-NEXT: store <8 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
-; FMA256-NEXT: ret void
-;
; FMA512-LABEL: @fma_16f32(
; FMA512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
@@ -565,3 +539,5 @@ define void @fma_16f32() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; FMA256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
index fc2ac392b17b5..2bf2fcaad5cc2 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmaxnum.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
@@ -57,12 +57,30 @@ define void @fmaxnum_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fmaxnum_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
-; AVX-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; AVX-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fmaxnum_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
+; AVX128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
+; AVX128-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.maxnum.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; AVX128-NEXT: store <2 x double> [[TMP3]], ptr @dst64, align 8
+; AVX128-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.maxnum.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP5]])
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fmaxnum_4f64(
+; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX256-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
+; AVX256-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fmaxnum_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX512-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.maxnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
+; AVX512-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 8
@@ -103,6 +121,25 @@ define void @fmaxnum_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fmaxnum_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.maxnum.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; AVX128-NEXT: store <2 x double> [[TMP3]], ptr @dst64, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.maxnum.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP5]])
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP9:%.*]] = call <2 x double> @llvm.maxnum.v2f64(<2 x double> [[TMP7]], <2 x double> [[TMP8]])
+; AVX128-NEXT: store <2 x double> [[TMP9]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP12:%.*]] = call <2 x double> @llvm.maxnum.v2f64(<2 x double> [[TMP10]], <2 x double> [[TMP11]])
+; AVX128-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fmaxnum_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
@@ -195,12 +232,30 @@ define void @fmaxnum_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fmaxnum_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; AVX-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fmaxnum_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; AVX128-NEXT: store <4 x float> [[TMP3]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fmaxnum_8f32(
+; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX256-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
+; AVX256-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fmaxnum_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.maxnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
+; AVX512-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
@@ -257,6 +312,25 @@ define void @fmaxnum_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fmaxnum_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; AVX128-NEXT: store <4 x float> [[TMP3]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP9:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP7]], <4 x float> [[TMP8]])
+; AVX128-NEXT: store <4 x float> [[TMP9]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP10:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP11:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP12:%.*]] = call <4 x float> @llvm.maxnum.v4f32(<4 x float> [[TMP10]], <4 x float> [[TMP11]])
+; AVX128-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fmaxnum_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
@@ -524,3 +598,5 @@ define double @reduction_v4f64_wrong_fmf(ptr %p) {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
index d49c6bd5d6312..64731c2259269 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fminnum.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
@@ -57,12 +57,30 @@ define void @fminnum_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fminnum_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
-; AVX-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
-; AVX-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fminnum_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
+; AVX128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
+; AVX128-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.minnum.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; AVX128-NEXT: store <2 x double> [[TMP3]], ptr @dst64, align 8
+; AVX128-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.minnum.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP5]])
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fminnum_4f64(
+; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX256-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
+; AVX256-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fminnum_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX512-NEXT: [[TMP3:%.*]] = call <4 x double> @llvm.minnum.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]])
+; AVX512-NEXT: store <4 x double> [[TMP3]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 8
@@ -103,6 +121,25 @@ define void @fminnum_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fminnum_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <2 x double> @llvm.minnum.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]])
+; AVX128-NEXT: store <2 x double> [[TMP3]], ptr @dst64, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <2 x double> @llvm.minnum.v2f64(<2 x double> [[TMP4]], <2 x double> [[TMP5]])
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP9:%.*]] = call <2 x double> @llvm.minnum.v2f64(<2 x double> [[TMP7]], <2 x double> [[TMP8]])
+; AVX128-NEXT: store <2 x double> [[TMP9]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP12:%.*]] = call <2 x double> @llvm.minnum.v2f64(<2 x double> [[TMP10]], <2 x double> [[TMP11]])
+; AVX128-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fminnum_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
@@ -195,12 +232,30 @@ define void @fminnum_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fminnum_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
-; AVX-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fminnum_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; AVX128-NEXT: store <4 x float> [[TMP3]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fminnum_8f32(
+; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX256-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
+; AVX256-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fminnum_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = call <8 x float> @llvm.minnum.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]])
+; AVX512-NEXT: store <8 x float> [[TMP3]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
@@ -257,6 +312,25 @@ define void @fminnum_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fminnum_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]])
+; AVX128-NEXT: store <4 x float> [[TMP3]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP4]], <4 x float> [[TMP5]])
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP9:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP7]], <4 x float> [[TMP8]])
+; AVX128-NEXT: store <4 x float> [[TMP9]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP10:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP11:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP12:%.*]] = call <4 x float> @llvm.minnum.v4f32(<4 x float> [[TMP10]], <4 x float> [[TMP11]])
+; AVX128-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fminnum_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
@@ -504,3 +578,5 @@ define double @reduction_v4f64_not_fast(ptr %p) {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll b/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
index 5c1d6f59e0d49..a15c9a65f6037 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fmuladd.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX512
@@ -89,13 +89,34 @@ define void @fmuladd_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fmuladd_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
-; AVX-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
-; AVX-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
-; AVX-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fmuladd_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
+; AVX128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr @srcC64, align 8
+; AVX128-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x double> [[TMP3]])
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr @dst64, align 8
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP8:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP5]], <2 x double> [[TMP6]], <2 x double> [[TMP7]])
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fmuladd_4f64(
+; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX256-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
+; AVX256-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
+; AVX256-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fmuladd_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; AVX512-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
+; AVX512-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
+; AVX512-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @srcA64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 1), align 8
@@ -144,6 +165,29 @@ define void @fmuladd_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP16]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fmuladd_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr @srcC64, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x double> [[TMP3]])
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr @dst64, align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP5]], <2 x double> [[TMP6]], <2 x double> [[TMP7]])
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP9:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP12:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP9]], <2 x double> [[TMP10]], <2 x double> [[TMP11]])
+; AVX128-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP13:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP14:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP15:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP16:%.*]] = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> [[TMP13]], <2 x double> [[TMP14]], <2 x double> [[TMP15]])
+; AVX128-NEXT: store <2 x double> [[TMP16]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fmuladd_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
@@ -254,13 +298,34 @@ define void @fmuladd_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fmuladd_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
-; AVX-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
-; AVX-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
-; AVX-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128-LABEL: @fmuladd_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr @srcC32, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]], <4 x float> [[TMP3]])
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP5]], <4 x float> [[TMP6]], <4 x float> [[TMP7]])
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
+;
+; AVX256-LABEL: @fmuladd_8f32(
+; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX256-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
+; AVX256-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
+; AVX256-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
+; AVX256-NEXT: ret void
+;
+; AVX512-LABEL: @fmuladd_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; AVX512-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
+; AVX512-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
+; AVX512-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @srcA32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 1), align 4
@@ -329,6 +394,29 @@ define void @fmuladd_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP16]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; SSE-NEXT: ret void
;
+; AVX128-LABEL: @fmuladd_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr @srcC32, align 4
+; AVX128-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]], <4 x float> [[TMP3]])
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP5]], <4 x float> [[TMP6]], <4 x float> [[TMP7]])
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP9:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP10:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP11:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP12:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP9]], <4 x float> [[TMP10]], <4 x float> [[TMP11]])
+; AVX128-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
+; AVX128-NEXT: [[TMP13:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP14:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP15:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP16:%.*]] = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> [[TMP13]], <4 x float> [[TMP14]], <4 x float> [[TMP15]])
+; AVX128-NEXT: store <4 x float> [[TMP16]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
+; AVX128-NEXT: ret void
+;
; AVX256-LABEL: @fmuladd_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
; AVX256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
@@ -434,3 +522,5 @@ define void @fmuladd_16f32() #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
index 7c049376ca274..048fece81cfbd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -51,6 +51,33 @@ define void @fptosi_8f64_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @fptosi_8f64_8i64(
+; AVX128NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
+; AVX128NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptosi double [[A0]] to i64
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptosi double [[A1]] to i64
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptosi double [[A2]] to i64
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptosi double [[A3]] to i64
+; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptosi double [[A4]] to i64
+; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptosi double [[A5]] to i64
+; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptosi double [[A6]] to i64
+; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptosi double [[A7]] to i64
+; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @fptosi_8f64_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
; AVX256NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -130,11 +157,32 @@ define void @fptosi_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptosi_8f64_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @fptosi_8f64_8i32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptosi <4 x double> [[TMP3]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @fptosi_8f64_8i32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX256NODQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f64_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptosi_8f64_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -263,6 +311,33 @@ define void @fptosi_8f32_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @fptosi_8f32_8i64(
+; AVX128NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
+; AVX128NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
+; AVX128NODQ-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
+; AVX128NODQ-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
+; AVX128NODQ-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
+; AVX128NODQ-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptosi float [[A0]] to i64
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptosi float [[A1]] to i64
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptosi float [[A2]] to i64
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptosi float [[A3]] to i64
+; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptosi float [[A4]] to i64
+; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptosi float [[A5]] to i64
+; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptosi float [[A6]] to i64
+; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptosi float [[A7]] to i64
+; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @fptosi_8f32_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
; AVX256NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -342,11 +417,32 @@ define void @fptosi_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptosi_8f32_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @fptosi_8f32_8i32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @fptosi_8f32_8i32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX256NODQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f32_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptosi_8f32_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -489,4 +585,5 @@ define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3)
attributes #0 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
index a44801cfc6a8e..4685f11141164 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -51,6 +51,33 @@ define void @fptosi_8f64_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @fptosi_8f64_8i64(
+; AVX128NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
+; AVX128NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptosi double [[A0]] to i64
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptosi double [[A1]] to i64
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptosi double [[A2]] to i64
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptosi double [[A3]] to i64
+; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptosi double [[A4]] to i64
+; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptosi double [[A5]] to i64
+; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptosi double [[A6]] to i64
+; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptosi double [[A7]] to i64
+; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @fptosi_8f64_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
; AVX256NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -130,11 +157,32 @@ define void @fptosi_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptosi_8f64_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @fptosi_8f64_8i32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptosi <4 x double> [[TMP3]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @fptosi_8f64_8i32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX256NODQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f64_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptosi_8f64_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x double> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -263,6 +311,33 @@ define void @fptosi_8f32_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @fptosi_8f32_8i64(
+; AVX128NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
+; AVX128NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
+; AVX128NODQ-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
+; AVX128NODQ-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
+; AVX128NODQ-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
+; AVX128NODQ-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptosi float [[A0]] to i64
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptosi float [[A1]] to i64
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptosi float [[A2]] to i64
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptosi float [[A3]] to i64
+; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptosi float [[A4]] to i64
+; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptosi float [[A5]] to i64
+; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptosi float [[A6]] to i64
+; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptosi float [[A7]] to i64
+; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @fptosi_8f32_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
; AVX256NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -342,11 +417,32 @@ define void @fptosi_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptosi_8f32_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @fptosi_8f32_8i32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @fptosi_8f32_8i32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX256NODQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptosi_8f32_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptosi_8f32_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = fptosi <8 x float> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -489,4 +585,5 @@ define <4 x i32> @fptosi_4xf32_4i32(float %a0, float %a1, float %a2, float %a3)
attributes #0 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
index b6cd8a9c360e2..0f1475106c4fd 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -51,6 +51,33 @@ define void @fptoui_8f64_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @fptoui_8f64_8i64(
+; AVX128NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
+; AVX128NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptoui double [[A0]] to i64
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptoui double [[A1]] to i64
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptoui double [[A2]] to i64
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptoui double [[A3]] to i64
+; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptoui double [[A4]] to i64
+; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptoui double [[A5]] to i64
+; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptoui double [[A6]] to i64
+; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptoui double [[A7]] to i64
+; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @fptoui_8f64_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
; AVX256NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -130,11 +157,32 @@ define void @fptoui_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptoui_8f64_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
-; AVX-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @fptoui_8f64_8i32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptoui <4 x double> [[TMP1]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptoui <4 x double> [[TMP3]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @fptoui_8f64_8i32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i32>
+; AVX256NODQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptoui_8f64_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptoui_8f64_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
+; AVX512-NEXT: [[TMP2:%.*]] = fptoui <8 x double> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load double, ptr @src64, align 8
%a1 = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
@@ -263,6 +311,33 @@ define void @fptoui_8f32_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @fptoui_8f32_8i64(
+; AVX128NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
+; AVX128NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
+; AVX128NODQ-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
+; AVX128NODQ-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
+; AVX128NODQ-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
+; AVX128NODQ-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptoui float [[A0]] to i64
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptoui float [[A1]] to i64
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptoui float [[A2]] to i64
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptoui float [[A3]] to i64
+; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptoui float [[A4]] to i64
+; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptoui float [[A5]] to i64
+; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptoui float [[A6]] to i64
+; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptoui float [[A7]] to i64
+; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @fptoui_8f32_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
; AVX256NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -342,11 +417,32 @@ define void @fptoui_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX-LABEL: @fptoui_8f32_8i32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
-; AVX-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i32>
-; AVX-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @fptoui_8f32_8i32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptoui <4 x float> [[TMP1]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptoui <4 x float> [[TMP3]] to <4 x i32>
+; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @fptoui_8f32_8i32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i32>
+; AVX256NODQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @fptoui_8f32_8i32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX256DQ-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i32>
+; AVX256DQ-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @fptoui_8f32_8i32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
+; AVX512-NEXT: [[TMP2:%.*]] = fptoui <8 x float> [[TMP1]] to <8 x i32>
+; AVX512-NEXT: store <8 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX512-NEXT: ret void
;
%a0 = load float, ptr @src32, align 4
%a1 = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
@@ -445,4 +541,5 @@ define void @fptoui_8f32_8i8() #0 {
attributes #0 = { nounwind }
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX: {{.*}}
; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
index f20e90cc69a93..ba4b629eb09ad 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -34,6 +34,15 @@ define void @sitofp_2i64_2f64() #0 {
; SSE-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @sitofp_2i64_2f64(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @sitofp_2i64_2f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -80,6 +89,21 @@ define void @sitofp_4i64_4f64() #0 {
; SSE-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @sitofp_4i64_4f64(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @sitofp_4i64_4f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -150,6 +174,33 @@ define void @sitofp_8i64_8f64() #0 {
; SSE-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @sitofp_8i64_8f64(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: [[LD4:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[LD5:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: [[LD6:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: [[LD7:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX128NODQ-NEXT: [[CVT4:%.*]] = sitofp i64 [[LD4]] to double
+; AVX128NODQ-NEXT: [[CVT5:%.*]] = sitofp i64 [[LD5]] to double
+; AVX128NODQ-NEXT: [[CVT6:%.*]] = sitofp i64 [[LD6]] to double
+; AVX128NODQ-NEXT: [[CVT7:%.*]] = sitofp i64 [[LD7]] to double
+; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: store double [[CVT4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: store double [[CVT5]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: store double [[CVT6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @sitofp_8i64_8f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -245,11 +296,32 @@ define void @sitofp_4i32_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_4i32_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
-; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_4i32_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_4i32_4f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_4i32_4f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_4i32_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i32, ptr @src32, align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
@@ -282,14 +354,38 @@ define void @sitofp_8i32_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_8i32_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i32_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i32> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i32_8f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i32_8f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_8i32_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
@@ -350,11 +446,32 @@ define void @sitofp_4i16_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_4i16_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
-; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_4i16_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_4i16_4f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_4i16_4f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_4i16_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i16, ptr @src16, align 64
%ld1 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 1), align 2
@@ -387,14 +504,38 @@ define void @sitofp_8i16_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_8i16_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i16_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i16> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i16> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i16_8f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i16_8f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_8i16_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
@@ -455,11 +596,32 @@ define void @sitofp_4i8_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_4i8_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
-; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_4i8_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_4i8_4f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_4i8_4f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_4i8_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i8, ptr @src8, align 64
%ld1 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 1), align 1
@@ -492,14 +654,38 @@ define void @sitofp_8i8_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_8i8_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i8_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i8> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i8> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i8_8f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i8_8f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_8i8_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
@@ -548,6 +734,15 @@ define void @sitofp_2i64_2f32() #0 {
; SSE-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @sitofp_2i64_2f32(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; AVX128NODQ-NEXT: store float [[CVT0]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @sitofp_2i64_2f32(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -610,11 +805,32 @@ define void @sitofp_8i64_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_8i64_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i64_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i64> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i64_8f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i64_8f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i64_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -675,11 +891,32 @@ define void @sitofp_8i32_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_8i32_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i32_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i32_8f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i32_8f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i32_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i32, ptr @src32, align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
@@ -724,14 +961,38 @@ define void @sitofp_16i32_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_16i32_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <8 x i32> [[TMP3]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_16i32_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i32> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i32> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_16i32_16f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i32> [[TMP3]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_16i32_16f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i32> [[TMP3]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_16i32_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @src32, align 64
@@ -822,11 +1083,32 @@ define void @sitofp_8i16_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_8i16_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i16_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i16_8f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i16_8f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i16_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i16, ptr @src16, align 64
%ld1 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 1), align 2
@@ -871,14 +1153,38 @@ define void @sitofp_16i16_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_16i16_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <8 x i16> [[TMP3]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_16i16_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i16> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i16> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_16i16_16f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i16> [[TMP3]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_16i16_16f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i16> [[TMP3]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_16i16_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @src16, align 64
@@ -969,11 +1275,32 @@ define void @sitofp_8i8_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_8i8_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i8_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i8_8f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i8_8f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i8_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i8, ptr @src8, align 64
%ld1 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 1), align 1
@@ -1018,14 +1345,38 @@ define void @sitofp_16i8_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_16i8_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <8 x i8> [[TMP3]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_16i8_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i8> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i8> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_16i8_16f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i8> [[TMP3]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_16i8_16f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i8> [[TMP3]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_16i8_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @src8, align 64
@@ -1141,3 +1492,5 @@ define <4 x float> @sitofp_4xi32_4f32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
index 194dfd4c11541..32777e7e35e5c 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -34,6 +34,15 @@ define void @sitofp_2i64_2f64() #0 {
; SSE-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @sitofp_2i64_2f64(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @sitofp_2i64_2f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -80,6 +89,21 @@ define void @sitofp_4i64_4f64() #0 {
; SSE-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @sitofp_4i64_4f64(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @sitofp_4i64_4f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -150,6 +174,33 @@ define void @sitofp_8i64_8f64() #0 {
; SSE-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @sitofp_8i64_8f64(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: [[LD4:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[LD5:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: [[LD6:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: [[LD7:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128NODQ-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX128NODQ-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX128NODQ-NEXT: [[CVT4:%.*]] = sitofp i64 [[LD4]] to double
+; AVX128NODQ-NEXT: [[CVT5:%.*]] = sitofp i64 [[LD5]] to double
+; AVX128NODQ-NEXT: [[CVT6:%.*]] = sitofp i64 [[LD6]] to double
+; AVX128NODQ-NEXT: [[CVT7:%.*]] = sitofp i64 [[LD7]] to double
+; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
+; AVX128NODQ-NEXT: store double [[CVT4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: store double [[CVT5]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 5), align 8
+; AVX128NODQ-NEXT: store double [[CVT6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @sitofp_8i64_8f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -245,11 +296,32 @@ define void @sitofp_4i32_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_4i32_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
-; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_4i32_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_4i32_4f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_4i32_4f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_4i32_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i32, ptr @src32, align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
@@ -282,14 +354,38 @@ define void @sitofp_8i32_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_8i32_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i32_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 6), align 8
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i32> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i32_8f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i32_8f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_8i32_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
@@ -350,11 +446,32 @@ define void @sitofp_4i16_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_4i16_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
-; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_4i16_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_4i16_4f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_4i16_4f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_4i16_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i16, ptr @src16, align 64
%ld1 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 1), align 2
@@ -387,14 +504,38 @@ define void @sitofp_8i16_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_8i16_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i16_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i16> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i16> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i16_8f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i16_8f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_8i16_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
@@ -455,11 +596,32 @@ define void @sitofp_4i8_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_4i8_4f64(
-; AVX-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
-; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_4i8_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_4i8_4f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_4i8_4f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_4i8_4f64(
+; AVX512-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX512-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i8, ptr @src8, align 64
%ld1 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 1), align 1
@@ -492,14 +654,38 @@ define void @sitofp_8i8_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_8i8_8f64(
-; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x double>
-; AVX256-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i8_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i8> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i8> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i8_8f64(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x double>
+; AVX256NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i8_8f64(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x double>
+; AVX256DQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_8i8_8f64(
; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
@@ -548,6 +734,15 @@ define void @sitofp_2i64_2f32() #0 {
; SSE-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @sitofp_2i64_2f32(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; AVX128NODQ-NEXT: store float [[CVT0]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @sitofp_2i64_2f32(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -610,11 +805,32 @@ define void @sitofp_8i64_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_8i64_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i64_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i64> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i64_8f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i64_8f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i64_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i64> [[TMP1]] to <8 x float>
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -675,11 +891,32 @@ define void @sitofp_8i32_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_8i32_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i32_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i32_8f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i32_8f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i32_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i32, ptr @src32, align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
@@ -724,14 +961,38 @@ define void @sitofp_16i32_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_16i32_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <8 x i32> [[TMP3]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_16i32_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i32> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i32> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_16i32_16f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i32> [[TMP3]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_16i32_16f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i32> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i32> [[TMP3]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_16i32_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x i32>, ptr @src32, align 64
@@ -822,11 +1083,32 @@ define void @sitofp_8i16_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_8i16_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i16_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i16_8f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i16_8f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i16_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i16, ptr @src16, align 64
%ld1 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 1), align 2
@@ -871,14 +1153,38 @@ define void @sitofp_16i16_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_16i16_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <8 x i16> [[TMP3]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_16i16_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i16> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i16> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_16i16_16f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i16> [[TMP3]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_16i16_16f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i16> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i16> [[TMP3]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_16i16_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @src16, align 64
@@ -969,11 +1275,32 @@ define void @sitofp_8i8_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX-LABEL: @sitofp_8i8_8f32(
-; AVX-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
-; AVX-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
-; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_8i8_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_8i8_8f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_8i8_8f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: ret void
+;
+; AVX512-LABEL: @sitofp_8i8_8f32(
+; AVX512-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX512-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX512-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX512-NEXT: ret void
;
%ld0 = load i8, ptr @src8, align 64
%ld1 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 1), align 1
@@ -1018,14 +1345,38 @@ define void @sitofp_16i8_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX256-LABEL: @sitofp_16i8_16f32(
-; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
-; AVX256-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
-; AVX256-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
-; AVX256-NEXT: [[TMP4:%.*]] = sitofp <8 x i8> [[TMP3]] to <8 x float>
-; AVX256-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX256-NEXT: ret void
+; AVX128NODQ-LABEL: @sitofp_16i8_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i8> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i8> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
+; AVX256NODQ-LABEL: @sitofp_16i8_16f32(
+; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX256NODQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256NODQ-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX256NODQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i8> [[TMP3]] to <8 x float>
+; AVX256NODQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256NODQ-NEXT: ret void
+;
+; AVX256DQ-LABEL: @sitofp_16i8_16f32(
+; AVX256DQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
+; AVX256DQ-NEXT: [[TMP2:%.*]] = sitofp <8 x i8> [[TMP1]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
+; AVX256DQ-NEXT: [[TMP3:%.*]] = load <8 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX256DQ-NEXT: [[TMP4:%.*]] = sitofp <8 x i8> [[TMP3]] to <8 x float>
+; AVX256DQ-NEXT: store <8 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX256DQ-NEXT: ret void
;
; AVX512-LABEL: @sitofp_16i8_16f32(
; AVX512-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @src8, align 64
@@ -1191,3 +1542,5 @@ define <4 x float> @sitofp_4xi32_4f32(i32 %a0, i32 %a1, i32 %a2, i32 %a3) #0 {
}
attributes #0 = { nounwind }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; AVX256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
index 9b4123c0218d8..b843f19668eaf 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
@@ -1,6 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ,AVX1
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX128NODQ
+
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ,AVX1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -50,12 +51,29 @@ define void @uitofp_4i64_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_4i64_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX-LABEL: @uitofp_4i64_4f64(
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
; AVX-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
; AVX-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_4i64_4f64(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
%ld2 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
@@ -87,6 +105,21 @@ define void @uitofp_8i64_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_8i64_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i64> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i64> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX256-LABEL: @uitofp_8i64_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
; AVX256-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x double>
@@ -102,6 +135,20 @@ define void @uitofp_8i64_8f64() #0 {
; AVX512-NEXT: store <8 x double> [[TMP2]], ptr @dst64, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_8i64_8f64(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX25628NODQ-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX25628NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i64> [[TMP5]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX25628NODQ-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
+; AVX25628NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i64> [[TMP7]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
%ld2 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
@@ -136,6 +183,15 @@ define void @uitofp_2i32_2f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_2i32_2f64(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = uitofp i32 [[LD0]] to double
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = uitofp i32 [[LD1]] to double
+; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: ret void
+;
; AVX1-LABEL: @uitofp_2i32_2f64(
; AVX1-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 64
; AVX1-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
@@ -163,6 +219,14 @@ define void @uitofp_2i32_2f64() #0 {
; AVX512-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_2i32_2f64(
+; AVX25628NODQ-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 64
+; AVX25628NODQ-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
+; AVX25628NODQ-NEXT: [[CVT0:%.*]] = uitofp i32 [[LD0]] to double
+; AVX25628NODQ-NEXT: [[CVT1:%.*]] = uitofp i32 [[LD1]] to double
+; AVX25628NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX25628NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i32, ptr @src32, align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
%cvt0 = uitofp i32 %ld0 to double
@@ -182,6 +246,12 @@ define void @uitofp_4i32_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_4i32_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX128NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: ret void
+;
; AVX-LABEL: @uitofp_4i32_4f64(
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
; AVX-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
@@ -219,6 +289,15 @@ define void @uitofp_8i32_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_8i32_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX128NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x double>
+; AVX128NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: ret void
+;
; AVX256-LABEL: @uitofp_8i32_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
; AVX256-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
@@ -234,6 +313,14 @@ define void @uitofp_8i32_8f64() #0 {
; AVX512-NEXT: store <8 x double> [[TMP2]], ptr @dst64, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_8i32_8f64(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX25628NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x double>
+; AVX25628NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i32, ptr @src32, align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
%ld2 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
@@ -287,12 +374,29 @@ define void @uitofp_4i16_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_4i16_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX-LABEL: @uitofp_4i16_4f64(
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
; AVX-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x double>
; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
; AVX-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_4i16_4f64(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i16, ptr @src16, align 64
%ld1 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 1), align 2
%ld2 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
@@ -324,6 +428,21 @@ define void @uitofp_8i16_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_8i16_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i16> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i16> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX256-LABEL: @uitofp_8i16_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
; AVX256-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x double>
@@ -339,6 +458,20 @@ define void @uitofp_8i16_8f64() #0 {
; AVX512-NEXT: store <8 x double> [[TMP2]], ptr @dst64, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_8i16_8f64(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX25628NODQ-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX25628NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i16> [[TMP5]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX25628NODQ-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
+; AVX25628NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i16> [[TMP7]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i16, ptr @src16, align 64
%ld1 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 1), align 2
%ld2 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
@@ -392,12 +525,29 @@ define void @uitofp_4i8_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_4i8_4f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX-LABEL: @uitofp_4i8_4f64(
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
; AVX-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x double>
; AVX-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
; AVX-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_4i8_4f64(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i8, ptr @src8, align 64
%ld1 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 1), align 1
%ld2 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
@@ -429,6 +579,21 @@ define void @uitofp_8i8_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_8i8_8f64(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i8> [[TMP5]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i8> [[TMP7]] to <2 x double>
+; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX256-LABEL: @uitofp_8i8_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
; AVX256-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x double>
@@ -444,6 +609,20 @@ define void @uitofp_8i8_8f64() #0 {
; AVX512-NEXT: store <8 x double> [[TMP2]], ptr @dst64, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_8i8_8f64(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX25628NODQ-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX25628NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i8> [[TMP5]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX25628NODQ-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
+; AVX25628NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i8> [[TMP7]] to <2 x double>
+; AVX25628NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i8, ptr @src8, align 64
%ld1 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 1), align 1
%ld2 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
@@ -485,6 +664,15 @@ define void @uitofp_2i64_2f32() #0 {
; SSE-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_2i64_2f32(
+; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128NODQ-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to float
+; AVX128NODQ-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to float
+; AVX128NODQ-NEXT: store float [[CVT0]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
+; AVX128NODQ-NEXT: ret void
+;
; AVX256NODQ-LABEL: @uitofp_2i64_2f32(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
; AVX256NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
@@ -506,6 +694,14 @@ define void @uitofp_2i64_2f32() #0 {
; AVX512-NEXT: store <2 x float> [[TMP2]], ptr @dst32, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_2i64_2f32(
+; AVX25628NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX25628NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX25628NODQ-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to float
+; AVX25628NODQ-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to float
+; AVX25628NODQ-NEXT: store float [[CVT0]], ptr @dst32, align 64
+; AVX25628NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
%cvt0 = uitofp i64 %ld0 to float
@@ -547,12 +743,29 @@ define void @uitofp_8i64_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_8i64_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i64> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX-LABEL: @uitofp_8i64_8f32(
; AVX-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
; AVX-NEXT: [[TMP2:%.*]] = uitofp <8 x i64> [[TMP1]] to <8 x float>
; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
; AVX-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_8i64_8f32(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i64> [[TMP3]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i64, ptr @src64, align 64
%ld1 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
%ld2 = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
@@ -612,12 +825,29 @@ define void @uitofp_8i32_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_8i32_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX-LABEL: @uitofp_8i32_8f32(
; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
; AVX-NEXT: [[TMP2:%.*]] = uitofp <8 x i32> [[TMP1]] to <8 x float>
; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
; AVX-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_8i32_8f32(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i32, ptr @src32, align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
%ld2 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
@@ -661,6 +891,21 @@ define void @uitofp_16i32_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_16i32_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i32> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i32> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX256-LABEL: @uitofp_16i32_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
; AVX256-NEXT: [[TMP2:%.*]] = uitofp <8 x i32> [[TMP1]] to <8 x float>
@@ -676,6 +921,20 @@ define void @uitofp_16i32_16f32() #0 {
; AVX512-NEXT: store <16 x float> [[TMP2]], ptr @dst32, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_16i32_16f32(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX25628NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i32> [[TMP5]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX25628NODQ-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
+; AVX25628NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i32> [[TMP7]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 0 ), align 64
%ld1 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1 ), align 4
%ld2 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2 ), align 8
@@ -759,12 +1018,29 @@ define void @uitofp_8i16_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_8i16_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX-LABEL: @uitofp_8i16_8f32(
; AVX-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
; AVX-NEXT: [[TMP2:%.*]] = uitofp <8 x i16> [[TMP1]] to <8 x float>
; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
; AVX-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_8i16_8f32(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i16, ptr @src16, align 64
%ld1 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 1), align 2
%ld2 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
@@ -808,6 +1084,21 @@ define void @uitofp_16i16_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_16i16_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i16> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i16> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX256-LABEL: @uitofp_16i16_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
; AVX256-NEXT: [[TMP2:%.*]] = uitofp <8 x i16> [[TMP1]] to <8 x float>
@@ -823,6 +1114,20 @@ define void @uitofp_16i16_16f32() #0 {
; AVX512-NEXT: store <16 x float> [[TMP2]], ptr @dst32, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_16i16_16f32(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX25628NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i16> [[TMP5]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX25628NODQ-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
+; AVX25628NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i16> [[TMP7]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 0 ), align 64
%ld1 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 1 ), align 2
%ld2 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2 ), align 4
@@ -906,12 +1211,29 @@ define void @uitofp_8i8_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_8i8_8f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX-LABEL: @uitofp_8i8_8f32(
; AVX-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
; AVX-NEXT: [[TMP2:%.*]] = uitofp <8 x i8> [[TMP1]] to <8 x float>
; AVX-NEXT: store <8 x float> [[TMP2]], ptr @dst32, align 64
; AVX-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_8i8_8f32(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i8, ptr @src8, align 64
%ld1 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 1), align 1
%ld2 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
@@ -955,6 +1277,21 @@ define void @uitofp_16i8_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
+; AVX128NODQ-LABEL: @uitofp_16i8_16f32(
+; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i8> [[TMP5]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
+; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i8> [[TMP7]] to <4 x float>
+; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128NODQ-NEXT: ret void
+;
; AVX256-LABEL: @uitofp_16i8_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
; AVX256-NEXT: [[TMP2:%.*]] = uitofp <8 x i8> [[TMP1]] to <8 x float>
@@ -970,6 +1307,20 @@ define void @uitofp_16i8_16f32() #0 {
; AVX512-NEXT: store <16 x float> [[TMP2]], ptr @dst32, align 64
; AVX512-NEXT: ret void
;
+; AVX25628NODQ-LABEL: @uitofp_16i8_16f32(
+; AVX25628NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX25628NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX25628NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX25628NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX25628NODQ-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX25628NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i8> [[TMP5]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX25628NODQ-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
+; AVX25628NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i8> [[TMP7]] to <4 x float>
+; AVX25628NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX25628NODQ-NEXT: ret void
%ld0 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 0 ), align 64
%ld1 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 1 ), align 1
%ld2 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2 ), align 2
>From 5e4386840f7d76dedd471dd3a72211f33c2fefd0 Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Thu, 24 Sep 2026 23:12:37 +0530
Subject: [PATCH 05/10] [X86] Update tests for Bulldozer 128-bit vector
preference
---
llvm/test/Transforms/SLPVectorizer/X86/fma.ll | 90 +++-
.../SLPVectorizer/X86/fptosi-inseltpoison.ll | 138 +++---
.../Transforms/SLPVectorizer/X86/fptosi.ll | 138 +++---
.../Transforms/SLPVectorizer/X86/fptoui.ll | 138 +++---
.../SLPVectorizer/X86/sitofp-inseltpoison.ll | 394 +++++++++---------
.../Transforms/SLPVectorizer/X86/sitofp.ll | 394 +++++++++---------
.../Transforms/SLPVectorizer/X86/uitofp.ll | 340 +++++++--------
7 files changed, 860 insertions(+), 772 deletions(-)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
index 0dcb43e7a467a..dd8aa25c15738 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
@@ -42,6 +42,14 @@ define void @fma_2f64() #0 {
; NO-FMA-NEXT: store double [[FMA1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
; NO-FMA-NEXT: ret void
;
+; FMA128-LABEL: @fma_2f64(
+; FMA128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
+; FMA128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
+; FMA128-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr @srcC64, align 8
+; FMA128-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x double> [[TMP3]])
+; FMA128-NEXT: store <2 x double> [[TMP4]], ptr @dst64, align 8
+; FMA128-NEXT: ret void
+;
; FMA-LABEL: @fma_2f64(
; FMA-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
; FMA-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
@@ -87,6 +95,19 @@ define void @fma_4f64() #0 {
; NO-FMA-NEXT: store double [[FMA3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; NO-FMA-NEXT: ret void
;
+; FMA128-LABEL: @fma_4f64(
+; FMA128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
+; FMA128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
+; FMA128-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr @srcC64, align 8
+; FMA128-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x double> [[TMP3]])
+; FMA128-NEXT: store <2 x double> [[TMP4]], ptr @dst64, align 8
+; FMA128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 8
+; FMA128-NEXT: [[TMP6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 8
+; FMA128-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 2), align 8
+; FMA128-NEXT: [[TMP8:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP5]], <2 x double> [[TMP6]], <2 x double> [[TMP7]])
+; FMA128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
+; FMA128-NEXT: ret void
+;
; FMA512-LABEL: @fma_4f64(
; FMA512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
; FMA512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
@@ -162,6 +183,29 @@ define void @fma_8f64() #0 {
; NO-FMA-NEXT: store double [[FMA7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 4
; NO-FMA-NEXT: ret void
;
+; FMA128-LABEL: @fma_8f64(
+; FMA128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 4
+; FMA128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 4
+; FMA128-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr @srcC64, align 4
+; FMA128-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x double> [[TMP3]])
+; FMA128-NEXT: store <2 x double> [[TMP4]], ptr @dst64, align 4
+; FMA128-NEXT: [[TMP5:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 2), align 4
+; FMA128-NEXT: [[TMP6:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 2), align 4
+; FMA128-NEXT: [[TMP7:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 2), align 4
+; FMA128-NEXT: [[TMP8:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP5]], <2 x double> [[TMP6]], <2 x double> [[TMP7]])
+; FMA128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 4
+; FMA128-NEXT: [[TMP9:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP10:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP11:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP12:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP9]], <2 x double> [[TMP10]], <2 x double> [[TMP11]])
+; FMA128-NEXT: store <2 x double> [[TMP12]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP13:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 6), align 4
+; FMA128-NEXT: [[TMP14:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 6), align 4
+; FMA128-NEXT: [[TMP15:%.*]] = load <2 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 6), align 4
+; FMA128-NEXT: [[TMP16:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP13]], <2 x double> [[TMP14]], <2 x double> [[TMP15]])
+; FMA128-NEXT: store <2 x double> [[TMP16]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
+; FMA128-NEXT: ret void
+;
; FMA512-LABEL: @fma_8f64(
; FMA512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
@@ -237,6 +281,14 @@ define void @fma_4f32() #0 {
; NO-FMA-NEXT: store float [[FMA3]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 3), align 4
; NO-FMA-NEXT: ret void
;
+; FMA128-LABEL: @fma_4f32(
+; FMA128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; FMA128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; FMA128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr @srcC32, align 4
+; FMA128-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]], <4 x float> [[TMP3]])
+; FMA128-NEXT: store <4 x float> [[TMP4]], ptr @dst32, align 4
+; FMA128-NEXT: ret void
+;
; FMA-LABEL: @fma_4f32(
; FMA-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
; FMA-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
@@ -312,6 +364,19 @@ define void @fma_8f32() #0 {
; NO-FMA-NEXT: store float [[FMA7]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 7), align 4
; NO-FMA-NEXT: ret void
;
+; FMA128-LABEL: @fma_8f32(
+; FMA128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; FMA128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; FMA128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr @srcC32, align 4
+; FMA128-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]], <4 x float> [[TMP3]])
+; FMA128-NEXT: store <4 x float> [[TMP4]], ptr @dst32, align 4
+; FMA128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP6:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP7:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP8:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP5]], <4 x float> [[TMP6]], <4 x float> [[TMP7]])
+; FMA128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; FMA128-NEXT: ret void
+;
; FMA512-LABEL: @fma_8f32(
; FMA512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
@@ -447,6 +512,29 @@ define void @fma_16f32() #0 {
; NO-FMA-NEXT: store float [[FMA15]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 15), align 4
; NO-FMA-NEXT: ret void
;
+; FMA128-LABEL: @fma_16f32(
+; FMA128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
+; FMA128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
+; FMA128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr @srcC32, align 4
+; FMA128-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]], <4 x float> [[TMP3]])
+; FMA128-NEXT: store <4 x float> [[TMP4]], ptr @dst32, align 4
+; FMA128-NEXT: [[TMP5:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP6:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP7:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP8:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP5]], <4 x float> [[TMP6]], <4 x float> [[TMP7]])
+; FMA128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
+; FMA128-NEXT: [[TMP9:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
+; FMA128-NEXT: [[TMP10:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
+; FMA128-NEXT: [[TMP11:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 8), align 4
+; FMA128-NEXT: [[TMP12:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP9]], <4 x float> [[TMP10]], <4 x float> [[TMP11]])
+; FMA128-NEXT: store <4 x float> [[TMP12]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
+; FMA128-NEXT: [[TMP13:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 12), align 4
+; FMA128-NEXT: [[TMP14:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 12), align 4
+; FMA128-NEXT: [[TMP15:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 12), align 4
+; FMA128-NEXT: [[TMP16:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP13]], <4 x float> [[TMP14]], <4 x float> [[TMP15]])
+; FMA128-NEXT: store <4 x float> [[TMP16]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
+; FMA128-NEXT: ret void
+;
; FMA512-LABEL: @fma_16f32(
; FMA512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
index 048fece81cfbd..a979efe12cc6e 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -51,32 +51,32 @@ define void @fptosi_8f64_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptosi_8f64_8i64(
-; AVX128NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
-; AVX128NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptosi double [[A0]] to i64
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptosi double [[A1]] to i64
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptosi double [[A2]] to i64
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptosi double [[A3]] to i64
-; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptosi double [[A4]] to i64
-; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptosi double [[A5]] to i64
-; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptosi double [[A6]] to i64
-; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptosi double [[A7]] to i64
-; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
-; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptosi_8f64_8i64(
+; AVX128-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
+; AVX128-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
+; AVX128-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
+; AVX128-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
+; AVX128-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = fptosi double [[A0]] to i64
+; AVX128-NEXT: [[CVT1:%.*]] = fptosi double [[A1]] to i64
+; AVX128-NEXT: [[CVT2:%.*]] = fptosi double [[A2]] to i64
+; AVX128-NEXT: [[CVT3:%.*]] = fptosi double [[A3]] to i64
+; AVX128-NEXT: [[CVT4:%.*]] = fptosi double [[A4]] to i64
+; AVX128-NEXT: [[CVT5:%.*]] = fptosi double [[A5]] to i64
+; AVX128-NEXT: [[CVT6:%.*]] = fptosi double [[A6]] to i64
+; AVX128-NEXT: [[CVT7:%.*]] = fptosi double [[A7]] to i64
+; AVX128-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptosi_8f64_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
@@ -157,14 +157,14 @@ define void @fptosi_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptosi_8f64_8i32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptosi <4 x double> [[TMP3]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptosi_8f64_8i32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX128-NEXT: [[TMP2:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = fptosi <4 x double> [[TMP3]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptosi_8f64_8i32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
@@ -311,32 +311,32 @@ define void @fptosi_8f32_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptosi_8f32_8i64(
-; AVX128NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
-; AVX128NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
-; AVX128NODQ-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
-; AVX128NODQ-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
-; AVX128NODQ-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
-; AVX128NODQ-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptosi float [[A0]] to i64
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptosi float [[A1]] to i64
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptosi float [[A2]] to i64
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptosi float [[A3]] to i64
-; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptosi float [[A4]] to i64
-; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptosi float [[A5]] to i64
-; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptosi float [[A6]] to i64
-; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptosi float [[A7]] to i64
-; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
-; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptosi_8f32_8i64(
+; AVX128-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
+; AVX128-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
+; AVX128-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
+; AVX128-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
+; AVX128-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
+; AVX128-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
+; AVX128-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
+; AVX128-NEXT: [[CVT0:%.*]] = fptosi float [[A0]] to i64
+; AVX128-NEXT: [[CVT1:%.*]] = fptosi float [[A1]] to i64
+; AVX128-NEXT: [[CVT2:%.*]] = fptosi float [[A2]] to i64
+; AVX128-NEXT: [[CVT3:%.*]] = fptosi float [[A3]] to i64
+; AVX128-NEXT: [[CVT4:%.*]] = fptosi float [[A4]] to i64
+; AVX128-NEXT: [[CVT5:%.*]] = fptosi float [[A5]] to i64
+; AVX128-NEXT: [[CVT6:%.*]] = fptosi float [[A6]] to i64
+; AVX128-NEXT: [[CVT7:%.*]] = fptosi float [[A7]] to i64
+; AVX128-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptosi_8f32_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
@@ -417,14 +417,14 @@ define void @fptosi_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptosi_8f32_8i32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptosi_8f32_8i32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptosi_8f32_8i32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
index 4685f11141164..0d3687342e109 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -51,32 +51,32 @@ define void @fptosi_8f64_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptosi_8f64_8i64(
-; AVX128NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
-; AVX128NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptosi double [[A0]] to i64
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptosi double [[A1]] to i64
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptosi double [[A2]] to i64
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptosi double [[A3]] to i64
-; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptosi double [[A4]] to i64
-; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptosi double [[A5]] to i64
-; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptosi double [[A6]] to i64
-; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptosi double [[A7]] to i64
-; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
-; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptosi_8f64_8i64(
+; AVX128-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
+; AVX128-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
+; AVX128-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
+; AVX128-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
+; AVX128-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = fptosi double [[A0]] to i64
+; AVX128-NEXT: [[CVT1:%.*]] = fptosi double [[A1]] to i64
+; AVX128-NEXT: [[CVT2:%.*]] = fptosi double [[A2]] to i64
+; AVX128-NEXT: [[CVT3:%.*]] = fptosi double [[A3]] to i64
+; AVX128-NEXT: [[CVT4:%.*]] = fptosi double [[A4]] to i64
+; AVX128-NEXT: [[CVT5:%.*]] = fptosi double [[A5]] to i64
+; AVX128-NEXT: [[CVT6:%.*]] = fptosi double [[A6]] to i64
+; AVX128-NEXT: [[CVT7:%.*]] = fptosi double [[A7]] to i64
+; AVX128-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptosi_8f64_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
@@ -157,14 +157,14 @@ define void @fptosi_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptosi_8f64_8i32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptosi <4 x double> [[TMP3]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptosi_8f64_8i32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX128-NEXT: [[TMP2:%.*]] = fptosi <4 x double> [[TMP1]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = fptosi <4 x double> [[TMP3]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptosi_8f64_8i32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
@@ -311,32 +311,32 @@ define void @fptosi_8f32_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptosi_8f32_8i64(
-; AVX128NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
-; AVX128NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
-; AVX128NODQ-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
-; AVX128NODQ-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
-; AVX128NODQ-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
-; AVX128NODQ-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptosi float [[A0]] to i64
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptosi float [[A1]] to i64
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptosi float [[A2]] to i64
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptosi float [[A3]] to i64
-; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptosi float [[A4]] to i64
-; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptosi float [[A5]] to i64
-; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptosi float [[A6]] to i64
-; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptosi float [[A7]] to i64
-; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
-; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptosi_8f32_8i64(
+; AVX128-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
+; AVX128-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
+; AVX128-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
+; AVX128-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
+; AVX128-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
+; AVX128-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
+; AVX128-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
+; AVX128-NEXT: [[CVT0:%.*]] = fptosi float [[A0]] to i64
+; AVX128-NEXT: [[CVT1:%.*]] = fptosi float [[A1]] to i64
+; AVX128-NEXT: [[CVT2:%.*]] = fptosi float [[A2]] to i64
+; AVX128-NEXT: [[CVT3:%.*]] = fptosi float [[A3]] to i64
+; AVX128-NEXT: [[CVT4:%.*]] = fptosi float [[A4]] to i64
+; AVX128-NEXT: [[CVT5:%.*]] = fptosi float [[A5]] to i64
+; AVX128-NEXT: [[CVT6:%.*]] = fptosi float [[A6]] to i64
+; AVX128-NEXT: [[CVT7:%.*]] = fptosi float [[A7]] to i64
+; AVX128-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptosi_8f32_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
@@ -417,14 +417,14 @@ define void @fptosi_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptosi_8f32_8i32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptosi_8f32_8i32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = fptosi <4 x float> [[TMP1]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = fptosi <4 x float> [[TMP3]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptosi_8f32_8i32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
index 0f1475106c4fd..5e4d640f901ac 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -51,32 +51,32 @@ define void @fptoui_8f64_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptoui_8f64_8i64(
-; AVX128NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
-; AVX128NODQ-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptoui double [[A0]] to i64
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptoui double [[A1]] to i64
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptoui double [[A2]] to i64
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptoui double [[A3]] to i64
-; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptoui double [[A4]] to i64
-; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptoui double [[A5]] to i64
-; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptoui double [[A6]] to i64
-; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptoui double [[A7]] to i64
-; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
-; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptoui_8f64_8i64(
+; AVX128-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
+; AVX128-NEXT: [[A1:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[A2:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 2), align 8
+; AVX128-NEXT: [[A3:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 3), align 8
+; AVX128-NEXT: [[A4:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128-NEXT: [[A5:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 5), align 8
+; AVX128-NEXT: [[A6:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 6), align 8
+; AVX128-NEXT: [[A7:%.*]] = load double, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 7), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = fptoui double [[A0]] to i64
+; AVX128-NEXT: [[CVT1:%.*]] = fptoui double [[A1]] to i64
+; AVX128-NEXT: [[CVT2:%.*]] = fptoui double [[A2]] to i64
+; AVX128-NEXT: [[CVT3:%.*]] = fptoui double [[A3]] to i64
+; AVX128-NEXT: [[CVT4:%.*]] = fptoui double [[A4]] to i64
+; AVX128-NEXT: [[CVT5:%.*]] = fptoui double [[A5]] to i64
+; AVX128-NEXT: [[CVT6:%.*]] = fptoui double [[A6]] to i64
+; AVX128-NEXT: [[CVT7:%.*]] = fptoui double [[A7]] to i64
+; AVX128-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptoui_8f64_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load double, ptr @src64, align 8
@@ -157,14 +157,14 @@ define void @fptoui_8f64_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptoui_8f64_8i32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptoui <4 x double> [[TMP1]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptoui <4 x double> [[TMP3]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptoui_8f64_8i32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @src64, align 8
+; AVX128-NEXT: [[TMP2:%.*]] = fptoui <4 x double> [[TMP1]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @src64, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = fptoui <4 x double> [[TMP3]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptoui_8f64_8i32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @src64, align 8
@@ -311,32 +311,32 @@ define void @fptoui_8f32_8i64() #0 {
; SSE-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptoui_8f32_8i64(
-; AVX128NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
-; AVX128NODQ-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
-; AVX128NODQ-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
-; AVX128NODQ-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
-; AVX128NODQ-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
-; AVX128NODQ-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = fptoui float [[A0]] to i64
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = fptoui float [[A1]] to i64
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = fptoui float [[A2]] to i64
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = fptoui float [[A3]] to i64
-; AVX128NODQ-NEXT: [[CVT4:%.*]] = fptoui float [[A4]] to i64
-; AVX128NODQ-NEXT: [[CVT5:%.*]] = fptoui float [[A5]] to i64
-; AVX128NODQ-NEXT: [[CVT6:%.*]] = fptoui float [[A6]] to i64
-; AVX128NODQ-NEXT: [[CVT7:%.*]] = fptoui float [[A7]] to i64
-; AVX128NODQ-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
-; AVX128NODQ-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptoui_8f32_8i64(
+; AVX128-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
+; AVX128-NEXT: [[A1:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 1), align 4
+; AVX128-NEXT: [[A2:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 2), align 4
+; AVX128-NEXT: [[A3:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 3), align 4
+; AVX128-NEXT: [[A4:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[A5:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 5), align 4
+; AVX128-NEXT: [[A6:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 6), align 4
+; AVX128-NEXT: [[A7:%.*]] = load float, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 7), align 4
+; AVX128-NEXT: [[CVT0:%.*]] = fptoui float [[A0]] to i64
+; AVX128-NEXT: [[CVT1:%.*]] = fptoui float [[A1]] to i64
+; AVX128-NEXT: [[CVT2:%.*]] = fptoui float [[A2]] to i64
+; AVX128-NEXT: [[CVT3:%.*]] = fptoui float [[A3]] to i64
+; AVX128-NEXT: [[CVT4:%.*]] = fptoui float [[A4]] to i64
+; AVX128-NEXT: [[CVT5:%.*]] = fptoui float [[A5]] to i64
+; AVX128-NEXT: [[CVT6:%.*]] = fptoui float [[A6]] to i64
+; AVX128-NEXT: [[CVT7:%.*]] = fptoui float [[A7]] to i64
+; AVX128-NEXT: store i64 [[CVT0]], ptr @dst64, align 8
+; AVX128-NEXT: store i64 [[CVT1]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store i64 [[CVT2]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 2), align 8
+; AVX128-NEXT: store i64 [[CVT3]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: store i64 [[CVT4]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 4), align 8
+; AVX128-NEXT: store i64 [[CVT5]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 5), align 8
+; AVX128-NEXT: store i64 [[CVT6]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 6), align 8
+; AVX128-NEXT: store i64 [[CVT7]], ptr getelementptr inbounds ([8 x i64], ptr @dst64, i32 0, i64 7), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptoui_8f32_8i64(
; AVX256NODQ-NEXT: [[A0:%.*]] = load float, ptr @src32, align 4
@@ -417,14 +417,14 @@ define void @fptoui_8f32_8i32() #0 {
; SSE-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @fptoui_8f32_8i32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = fptoui <4 x float> [[TMP1]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = fptoui <4 x float> [[TMP3]] to <4 x i32>
-; AVX128NODQ-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @fptoui_8f32_8i32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @src32, align 4
+; AVX128-NEXT: [[TMP2:%.*]] = fptoui <4 x float> [[TMP1]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP2]], ptr @dst32, align 4
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr getelementptr inbounds ([16 x float], ptr @src32, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = fptoui <4 x float> [[TMP3]] to <4 x i32>
+; AVX128-NEXT: store <4 x i32> [[TMP4]], ptr getelementptr inbounds ([16 x i32], ptr @dst32, i32 0, i64 4), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @fptoui_8f32_8i32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @src32, align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
index ba4b629eb09ad..fe1f592b54152 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -34,14 +34,14 @@ define void @sitofp_2i64_2f64() #0 {
; SSE-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_2i64_2f64(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
-; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_2i64_2f64(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_2i64_2f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -89,20 +89,20 @@ define void @sitofp_4i64_4f64() #0 {
; SSE-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_4i64_4f64(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
-; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_4i64_4f64(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX128-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX128-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_4i64_4f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -174,32 +174,32 @@ define void @sitofp_8i64_8f64() #0 {
; SSE-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i64_8f64(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: [[LD4:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[LD5:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: [[LD6:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: [[LD7:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
-; AVX128NODQ-NEXT: [[CVT4:%.*]] = sitofp i64 [[LD4]] to double
-; AVX128NODQ-NEXT: [[CVT5:%.*]] = sitofp i64 [[LD5]] to double
-; AVX128NODQ-NEXT: [[CVT6:%.*]] = sitofp i64 [[LD6]] to double
-; AVX128NODQ-NEXT: [[CVT7:%.*]] = sitofp i64 [[LD7]] to double
-; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: store double [[CVT4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: store double [[CVT5]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: store double [[CVT6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i64_8f64(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
+; AVX128-NEXT: [[LD4:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[LD5:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 5), align 8
+; AVX128-NEXT: [[LD6:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
+; AVX128-NEXT: [[LD7:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 7), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX128-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX128-NEXT: [[CVT4:%.*]] = sitofp i64 [[LD4]] to double
+; AVX128-NEXT: [[CVT5:%.*]] = sitofp i64 [[LD5]] to double
+; AVX128-NEXT: [[CVT6:%.*]] = sitofp i64 [[LD6]] to double
+; AVX128-NEXT: [[CVT7:%.*]] = sitofp i64 [[LD7]] to double
+; AVX128-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: store double [[CVT4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: store double [[CVT5]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 5), align 8
+; AVX128-NEXT: store double [[CVT6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i64_8f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -296,14 +296,14 @@ define void @sitofp_4i32_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_4i32_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_4i32_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_4i32_4f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
@@ -354,20 +354,20 @@ define void @sitofp_8i32_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i32_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i32> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i32_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 6), align 8
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <2 x i32> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i32_8f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
@@ -446,14 +446,14 @@ define void @sitofp_4i16_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_4i16_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_4i16_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_4i16_4f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
@@ -504,20 +504,20 @@ define void @sitofp_8i16_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i16_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i16> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i16> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i16_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <2 x i16> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <2 x i16> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i16_8f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
@@ -596,14 +596,14 @@ define void @sitofp_4i8_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_4i8_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_4i8_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_4i8_4f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
@@ -654,20 +654,20 @@ define void @sitofp_8i8_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i8_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i8> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i8> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i8_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <2 x i8> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <2 x i8> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i8_8f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
@@ -734,14 +734,14 @@ define void @sitofp_2i64_2f32() #0 {
; SSE-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_2i64_2f32(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
-; AVX128NODQ-NEXT: store float [[CVT0]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_2i64_2f32(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; AVX128-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; AVX128-NEXT: store float [[CVT0]], ptr @dst32, align 64
+; AVX128-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_2i64_2f32(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -805,14 +805,14 @@ define void @sitofp_8i64_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i64_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i64> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i64_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i64> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i64_8f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
@@ -891,14 +891,14 @@ define void @sitofp_8i32_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i32_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i32_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i32_8f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
@@ -961,20 +961,20 @@ define void @sitofp_16i32_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_16i32_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i32> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i32> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_16i32_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <4 x i32> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <4 x i32> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_16i32_16f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
@@ -1083,14 +1083,14 @@ define void @sitofp_8i16_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i16_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i16_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i16_8f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
@@ -1153,20 +1153,20 @@ define void @sitofp_16i16_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_16i16_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i16> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i16> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_16i16_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <4 x i16> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <4 x i16> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_16i16_16f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
@@ -1275,14 +1275,14 @@ define void @sitofp_8i8_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i8_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i8_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i8_8f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
@@ -1345,20 +1345,20 @@ define void @sitofp_16i8_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_16i8_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i8> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i8> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_16i8_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <4 x i8> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <4 x i8> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_16i8_16f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
index 32777e7e35e5c..4275ac110ed5a 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
@@ -34,14 +34,14 @@ define void @sitofp_2i64_2f64() #0 {
; SSE-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_2i64_2f64(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
-; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_2i64_2f64(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_2i64_2f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -89,20 +89,20 @@ define void @sitofp_4i64_4f64() #0 {
; SSE-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_4i64_4f64(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
-; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_4i64_4f64(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX128-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX128-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_4i64_4f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -174,32 +174,32 @@ define void @sitofp_8i64_8f64() #0 {
; SSE-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i64_8f64(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: [[LD4:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[LD5:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: [[LD6:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: [[LD7:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
-; AVX128NODQ-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
-; AVX128NODQ-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
-; AVX128NODQ-NEXT: [[CVT4:%.*]] = sitofp i64 [[LD4]] to double
-; AVX128NODQ-NEXT: [[CVT5:%.*]] = sitofp i64 [[LD5]] to double
-; AVX128NODQ-NEXT: [[CVT6:%.*]] = sitofp i64 [[LD6]] to double
-; AVX128NODQ-NEXT: [[CVT7:%.*]] = sitofp i64 [[LD7]] to double
-; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
-; AVX128NODQ-NEXT: store double [[CVT4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: store double [[CVT5]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 5), align 8
-; AVX128NODQ-NEXT: store double [[CVT6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i64_8f64(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[LD2:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[LD3:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 3), align 8
+; AVX128-NEXT: [[LD4:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[LD5:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 5), align 8
+; AVX128-NEXT: [[LD6:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
+; AVX128-NEXT: [[LD7:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 7), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to double
+; AVX128-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to double
+; AVX128-NEXT: [[CVT2:%.*]] = sitofp i64 [[LD2]] to double
+; AVX128-NEXT: [[CVT3:%.*]] = sitofp i64 [[LD3]] to double
+; AVX128-NEXT: [[CVT4:%.*]] = sitofp i64 [[LD4]] to double
+; AVX128-NEXT: [[CVT5:%.*]] = sitofp i64 [[LD5]] to double
+; AVX128-NEXT: [[CVT6:%.*]] = sitofp i64 [[LD6]] to double
+; AVX128-NEXT: [[CVT7:%.*]] = sitofp i64 [[LD7]] to double
+; AVX128-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: store double [[CVT2]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: store double [[CVT3]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 3), align 8
+; AVX128-NEXT: store double [[CVT4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: store double [[CVT5]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 5), align 8
+; AVX128-NEXT: store double [[CVT6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: store double [[CVT7]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 7), align 8
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i64_8f64(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -296,14 +296,14 @@ define void @sitofp_4i32_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_4i32_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_4i32_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_4i32_4f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
@@ -354,20 +354,20 @@ define void @sitofp_8i32_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i32_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 6), align 8
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i32> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i32_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i32> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 2), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <2 x i32> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 6), align 8
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <2 x i32> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i32_8f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
@@ -446,14 +446,14 @@ define void @sitofp_4i16_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_4i16_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_4i16_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_4i16_4f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
@@ -504,20 +504,20 @@ define void @sitofp_8i16_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i16_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i16> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i16> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i16_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <2 x i16> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <2 x i16> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i16_8f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
@@ -596,14 +596,14 @@ define void @sitofp_4i8_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_4i8_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_4i8_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_4i8_4f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
@@ -654,20 +654,20 @@ define void @sitofp_8i8_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i8_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <2 x i8> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <2 x i8> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i8_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <2 x i8> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <2 x i8> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i8_8f64(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
@@ -734,14 +734,14 @@ define void @sitofp_2i64_2f32() #0 {
; SSE-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_2i64_2f32(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
-; AVX128NODQ-NEXT: store float [[CVT0]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_2i64_2f32(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = sitofp i64 [[LD0]] to float
+; AVX128-NEXT: [[CVT1:%.*]] = sitofp i64 [[LD1]] to float
+; AVX128-NEXT: store float [[CVT0]], ptr @dst32, align 64
+; AVX128-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_2i64_2f32(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -805,14 +805,14 @@ define void @sitofp_8i64_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i64_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i64> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i64_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i64> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i64_8f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
@@ -891,14 +891,14 @@ define void @sitofp_8i32_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i32_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i32_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i32_8f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
@@ -961,20 +961,20 @@ define void @sitofp_16i32_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_16i32_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i32> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i32> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_16i32_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <4 x i32> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <4 x i32> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_16i32_16f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
@@ -1083,14 +1083,14 @@ define void @sitofp_8i16_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i16_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i16_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i16_8f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
@@ -1153,20 +1153,20 @@ define void @sitofp_16i16_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_16i16_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i16> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i16> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_16i16_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <4 x i16> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <4 x i16> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_16i16_16f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
@@ -1275,14 +1275,14 @@ define void @sitofp_8i8_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_8i8_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_8i8_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_8i8_8f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
@@ -1345,20 +1345,20 @@ define void @sitofp_16i8_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @sitofp_16i8_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = sitofp <4 x i8> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = sitofp <4 x i8> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @sitofp_16i8_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = sitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = sitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = sitofp <4 x i8> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = sitofp <4 x i8> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @sitofp_16i8_16f32(
; AVX256NODQ-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
index b843f19668eaf..3763db4c8d157 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/uitofp.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX128NODQ
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ,AVX1
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ,AVX2
@@ -51,14 +51,14 @@ define void @uitofp_4i64_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_4i64_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_4i64_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX-LABEL: @uitofp_4i64_4f64(
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
@@ -105,20 +105,20 @@ define void @uitofp_8i64_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_8i64_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i64> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i64> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_8i64_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @src64, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <2 x i64> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <2 x i64> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP6:%.*]] = uitofp <2 x i64> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 6), align 16
+; AVX128-NEXT: [[TMP8:%.*]] = uitofp <2 x i64> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256-LABEL: @uitofp_8i64_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
@@ -183,14 +183,14 @@ define void @uitofp_2i32_2f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_2i32_2f64(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = uitofp i32 [[LD0]] to double
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = uitofp i32 [[LD1]] to double
-; AVX128NODQ-NEXT: store double [[CVT0]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_2i32_2f64(
+; AVX128-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i32, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 1), align 4
+; AVX128-NEXT: [[CVT0:%.*]] = uitofp i32 [[LD0]] to double
+; AVX128-NEXT: [[CVT1:%.*]] = uitofp i32 [[LD1]] to double
+; AVX128-NEXT: store double [[CVT0]], ptr @dst64, align 64
+; AVX128-NEXT: store double [[CVT1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
+; AVX128-NEXT: ret void
;
; AVX1-LABEL: @uitofp_2i32_2f64(
; AVX1-NEXT: [[LD0:%.*]] = load i32, ptr @src32, align 64
@@ -246,11 +246,11 @@ define void @uitofp_4i32_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_4i32_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
-; AVX128NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_4i32_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX128-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: ret void
;
; AVX-LABEL: @uitofp_4i32_4f64(
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
@@ -289,14 +289,14 @@ define void @uitofp_8i32_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_8i32_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
-; AVX128NODQ-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x double>
-; AVX128NODQ-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_8i32_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x double>
+; AVX128-NEXT: store <4 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x double>
+; AVX128-NEXT: store <4 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: ret void
;
; AVX256-LABEL: @uitofp_8i32_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
@@ -374,14 +374,14 @@ define void @uitofp_4i16_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_4i16_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i16> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_4i16_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX-LABEL: @uitofp_4i16_4f64(
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
@@ -428,20 +428,20 @@ define void @uitofp_8i16_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_8i16_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i16> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i16> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i16> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_8i16_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <2 x i16> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 2), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <2 x i16> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = uitofp <2 x i16> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 6), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = uitofp <2 x i16> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256-LABEL: @uitofp_8i16_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
@@ -525,14 +525,14 @@ define void @uitofp_4i8_4f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_4i8_4f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i8> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i8> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_4i8_4f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: ret void
;
; AVX-LABEL: @uitofp_4i8_4f64(
; AVX-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
@@ -579,20 +579,20 @@ define void @uitofp_8i8_8f64() #0 {
; SSE-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_8i8_8f64(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <2 x i8> [[TMP1]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <2 x i8> [[TMP3]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <2 x i8> [[TMP5]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <2 x i8> [[TMP7]] to <2 x double>
-; AVX128NODQ-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_8i8_8f64(
+; AVX128-NEXT: [[TMP1:%.*]] = load <2 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <2 x i8> [[TMP1]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP2]], ptr @dst64, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 2), align 2
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <2 x i8> [[TMP3]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP4]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP6:%.*]] = uitofp <2 x i8> [[TMP5]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP6]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <2 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 6), align 2
+; AVX128-NEXT: [[TMP8:%.*]] = uitofp <2 x i8> [[TMP7]] to <2 x double>
+; AVX128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 16
+; AVX128-NEXT: ret void
;
; AVX256-LABEL: @uitofp_8i8_8f64(
; AVX256-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
@@ -664,14 +664,14 @@ define void @uitofp_2i64_2f32() #0 {
; SSE-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_2i64_2f32(
-; AVX128NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
-; AVX128NODQ-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to float
-; AVX128NODQ-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to float
-; AVX128NODQ-NEXT: store float [[CVT0]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_2i64_2f32(
+; AVX128-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
+; AVX128-NEXT: [[LD1:%.*]] = load i64, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 1), align 8
+; AVX128-NEXT: [[CVT0:%.*]] = uitofp i64 [[LD0]] to float
+; AVX128-NEXT: [[CVT1:%.*]] = uitofp i64 [[LD1]] to float
+; AVX128-NEXT: store float [[CVT0]], ptr @dst32, align 64
+; AVX128-NEXT: store float [[CVT1]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 1), align 4
+; AVX128-NEXT: ret void
;
; AVX256NODQ-LABEL: @uitofp_2i64_2f32(
; AVX256NODQ-NEXT: [[LD0:%.*]] = load i64, ptr @src64, align 64
@@ -743,14 +743,14 @@ define void @uitofp_8i64_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_8i64_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i64> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_8i64_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @src64, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i64> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @src64, i32 0, i64 4), align 32
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <4 x i64> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX-LABEL: @uitofp_8i64_8f32(
; AVX-NEXT: [[TMP1:%.*]] = load <8 x i64>, ptr @src64, align 64
@@ -825,14 +825,14 @@ define void @uitofp_8i32_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_8i32_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_8i32_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX-LABEL: @uitofp_8i32_8f32(
; AVX-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
@@ -891,20 +891,20 @@ define void @uitofp_16i32_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_16i32_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i32> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i32> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_16i32_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @src32, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i32> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <4 x i32> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP6:%.*]] = uitofp <4 x i32> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @src32, i32 0, i64 12), align 16
+; AVX128-NEXT: [[TMP8:%.*]] = uitofp <4 x i32> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256-LABEL: @uitofp_16i32_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @src32, align 64
@@ -1018,14 +1018,14 @@ define void @uitofp_8i16_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_8i16_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i16> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_8i16_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX-LABEL: @uitofp_8i16_8f32(
; AVX-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
@@ -1084,20 +1084,20 @@ define void @uitofp_16i16_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_16i16_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i16> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i16> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i16> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_16i16_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i16>, ptr @src16, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i16> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 4), align 8
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <4 x i16> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 8), align 16
+; AVX128-NEXT: [[TMP6:%.*]] = uitofp <4 x i16> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @src16, i32 0, i64 12), align 8
+; AVX128-NEXT: [[TMP8:%.*]] = uitofp <4 x i16> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256-LABEL: @uitofp_16i16_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @src16, align 64
@@ -1211,14 +1211,14 @@ define void @uitofp_8i8_8f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_8i8_8f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i8> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_8i8_8f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: ret void
;
; AVX-LABEL: @uitofp_8i8_8f32(
; AVX-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
@@ -1277,20 +1277,20 @@ define void @uitofp_16i8_16f32() #0 {
; SSE-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
; SSE-NEXT: ret void
;
-; AVX128NODQ-LABEL: @uitofp_16i8_16f32(
-; AVX128NODQ-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
-; AVX128NODQ-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
-; AVX128NODQ-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
-; AVX128NODQ-NEXT: [[TMP4:%.*]] = uitofp <4 x i8> [[TMP3]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
-; AVX128NODQ-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
-; AVX128NODQ-NEXT: [[TMP6:%.*]] = uitofp <4 x i8> [[TMP5]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
-; AVX128NODQ-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
-; AVX128NODQ-NEXT: [[TMP8:%.*]] = uitofp <4 x i8> [[TMP7]] to <4 x float>
-; AVX128NODQ-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
-; AVX128NODQ-NEXT: ret void
+; AVX128-LABEL: @uitofp_16i8_16f32(
+; AVX128-NEXT: [[TMP1:%.*]] = load <4 x i8>, ptr @src8, align 64
+; AVX128-NEXT: [[TMP2:%.*]] = uitofp <4 x i8> [[TMP1]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP2]], ptr @dst32, align 64
+; AVX128-NEXT: [[TMP3:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 4), align 4
+; AVX128-NEXT: [[TMP4:%.*]] = uitofp <4 x i8> [[TMP3]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP4]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 16
+; AVX128-NEXT: [[TMP5:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 8), align 8
+; AVX128-NEXT: [[TMP6:%.*]] = uitofp <4 x i8> [[TMP5]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP6]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 32
+; AVX128-NEXT: [[TMP7:%.*]] = load <4 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @src8, i32 0, i64 12), align 4
+; AVX128-NEXT: [[TMP8:%.*]] = uitofp <4 x i8> [[TMP7]] to <4 x float>
+; AVX128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 16
+; AVX128-NEXT: ret void
;
; AVX256-LABEL: @uitofp_16i8_16f32(
; AVX256-NEXT: [[TMP1:%.*]] = load <8 x i8>, ptr @src8, align 64
>From f4e7ba35d7f0ed16ef5602b55e9eec350e2799e1 Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Thu, 24 Sep 2026 23:48:09 +0530
Subject: [PATCH 06/10] [X86] Clean up Bulldozer test prefixes
---
llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll | 2 +-
llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
index 5e4d640f901ac..b08f5a1474ca8 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptoui.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
index fe1f592b54152..3f1ef46618792 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/sitofp-inseltpoison.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
>From bfeb7b369113dee2fa95e2c8c471868bb0ba6fec Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Fri, 25 Sep 2026 15:16:26 +0530
Subject: [PATCH 07/10] [X86] Update Bulldozer test expectations
---
llvm/test/Transforms/SLPVectorizer/X86/fma.ll | 18 +---
.../SLPVectorizer/X86/fptosi-inseltpoison.ll | 2 +-
.../Transforms/SLPVectorizer/X86/fptosi.ll | 2 +-
.../SLPVectorizer/X86/shift-ashr.ll | 98 ++++++++++++-------
4 files changed, 68 insertions(+), 52 deletions(-)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
index dd8aa25c15738..5d30f5431fe04 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=FMA128
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA128,FMA256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
@@ -42,14 +42,6 @@ define void @fma_2f64() #0 {
; NO-FMA-NEXT: store double [[FMA1]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 1), align 8
; NO-FMA-NEXT: ret void
;
-; FMA128-LABEL: @fma_2f64(
-; FMA128-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
-; FMA128-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
-; FMA128-NEXT: [[TMP3:%.*]] = load <2 x double>, ptr @srcC64, align 8
-; FMA128-NEXT: [[TMP4:%.*]] = call <2 x double> @llvm.fma.v2f64(<2 x double> [[TMP1]], <2 x double> [[TMP2]], <2 x double> [[TMP3]])
-; FMA128-NEXT: store <2 x double> [[TMP4]], ptr @dst64, align 8
-; FMA128-NEXT: ret void
-;
; FMA-LABEL: @fma_2f64(
; FMA-NEXT: [[TMP1:%.*]] = load <2 x double>, ptr @srcA64, align 8
; FMA-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @srcB64, align 8
@@ -281,14 +273,6 @@ define void @fma_4f32() #0 {
; NO-FMA-NEXT: store float [[FMA3]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 3), align 4
; NO-FMA-NEXT: ret void
;
-; FMA128-LABEL: @fma_4f32(
-; FMA128-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
-; FMA128-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
-; FMA128-NEXT: [[TMP3:%.*]] = load <4 x float>, ptr @srcC32, align 4
-; FMA128-NEXT: [[TMP4:%.*]] = call <4 x float> @llvm.fma.v4f32(<4 x float> [[TMP1]], <4 x float> [[TMP2]], <4 x float> [[TMP3]])
-; FMA128-NEXT: store <4 x float> [[TMP4]], ptr @dst32, align 4
-; FMA128-NEXT: ret void
-;
; FMA-LABEL: @fma_4f32(
; FMA-NEXT: [[TMP1:%.*]] = load <4 x float>, ptr @srcA32, align 4
; FMA-NEXT: [[TMP2:%.*]] = load <4 x float>, ptr @srcB32, align 4
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
index a979efe12cc6e..be66c141fd32d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi-inseltpoison.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
index 0d3687342e109..4bc99c2475a7d 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fptosi.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,SSE
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX128
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256NODQ
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=CHECK,AVX,AVX256,AVX256DQ
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll b/llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
index dad69dbb39106..fdbe643a93446 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/shift-ashr.ll
@@ -9,7 +9,7 @@
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m7 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX,AVX2
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=AVX512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=c86-4g-m8 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=AVX,AVX2
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -mattr=-prefer-128-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver4 -passes=slp-vectorizer -S | FileCheck %s --check-prefix=XOP
@a64 = common global [8 x i64] zeroinitializer, align 64
@b64 = common global [8 x i64] zeroinitializer, align 64
@@ -114,14 +114,22 @@ define void @ashr_v8i64() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @ashr_v8i64(
-; XOP-NEXT: [[TMP1:%.*]] = load <4 x i64>, ptr @a64, align 8
-; XOP-NEXT: [[TMP2:%.*]] = load <4 x i64>, ptr @b64, align 8
-; XOP-NEXT: [[TMP3:%.*]] = ashr <4 x i64> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <4 x i64> [[TMP3]], ptr @c64, align 8
-; XOP-NEXT: [[TMP4:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 4), align 8
-; XOP-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 4), align 8
-; XOP-NEXT: [[TMP6:%.*]] = ashr <4 x i64> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <4 x i64> [[TMP6]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP1:%.*]] = load <2 x i64>, ptr @a64, align 8
+; XOP-NEXT: [[TMP2:%.*]] = load <2 x i64>, ptr @b64, align 8
+; XOP-NEXT: [[TMP3:%.*]] = ashr <2 x i64> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <2 x i64> [[TMP3]], ptr @c64, align 8
+; XOP-NEXT: [[TMP4:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP5:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP6:%.*]] = ashr <2 x i64> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <2 x i64> [[TMP6]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 2), align 8
+; XOP-NEXT: [[TMP7:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP8:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP9:%.*]] = ashr <2 x i64> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <2 x i64> [[TMP9]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 4), align 8
+; XOP-NEXT: [[TMP10:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @a64, i32 0, i64 6), align 8
+; XOP-NEXT: [[TMP11:%.*]] = load <2 x i64>, ptr getelementptr inbounds ([8 x i64], ptr @b64, i32 0, i64 6), align 8
+; XOP-NEXT: [[TMP12:%.*]] = ashr <2 x i64> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <2 x i64> [[TMP12]], ptr getelementptr inbounds ([8 x i64], ptr @c64, i32 0, i64 6), align 8
; XOP-NEXT: ret void
;
%a0 = load i64, ptr @a64, align 8
@@ -198,14 +206,22 @@ define void @ashr_v16i32() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @ashr_v16i32(
-; XOP-NEXT: [[TMP1:%.*]] = load <8 x i32>, ptr @a32, align 4
-; XOP-NEXT: [[TMP2:%.*]] = load <8 x i32>, ptr @b32, align 4
-; XOP-NEXT: [[TMP3:%.*]] = ashr <8 x i32> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <8 x i32> [[TMP3]], ptr @c32, align 4
-; XOP-NEXT: [[TMP4:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 8), align 4
-; XOP-NEXT: [[TMP5:%.*]] = load <8 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 8), align 4
-; XOP-NEXT: [[TMP6:%.*]] = ashr <8 x i32> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <8 x i32> [[TMP6]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP1:%.*]] = load <4 x i32>, ptr @a32, align 4
+; XOP-NEXT: [[TMP2:%.*]] = load <4 x i32>, ptr @b32, align 4
+; XOP-NEXT: [[TMP3:%.*]] = ashr <4 x i32> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <4 x i32> [[TMP3]], ptr @c32, align 4
+; XOP-NEXT: [[TMP4:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP5:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP6:%.*]] = ashr <4 x i32> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <4 x i32> [[TMP6]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 4), align 4
+; XOP-NEXT: [[TMP7:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP8:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP9:%.*]] = ashr <4 x i32> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <4 x i32> [[TMP9]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 8), align 4
+; XOP-NEXT: [[TMP10:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 12), align 4
+; XOP-NEXT: [[TMP11:%.*]] = load <4 x i32>, ptr getelementptr inbounds ([16 x i32], ptr @b32, i32 0, i64 12), align 4
+; XOP-NEXT: [[TMP12:%.*]] = ashr <4 x i32> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <4 x i32> [[TMP12]], ptr getelementptr inbounds ([16 x i32], ptr @c32, i32 0, i64 12), align 4
; XOP-NEXT: ret void
;
%a0 = load i32, ptr getelementptr inbounds ([16 x i32], ptr @a32, i32 0, i64 0 ), align 4
@@ -314,14 +330,22 @@ define void @ashr_v32i16() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @ashr_v32i16(
-; XOP-NEXT: [[TMP1:%.*]] = load <16 x i16>, ptr @a16, align 2
-; XOP-NEXT: [[TMP2:%.*]] = load <16 x i16>, ptr @b16, align 2
-; XOP-NEXT: [[TMP3:%.*]] = ashr <16 x i16> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <16 x i16> [[TMP3]], ptr @c16, align 2
-; XOP-NEXT: [[TMP4:%.*]] = load <16 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 16), align 2
-; XOP-NEXT: [[TMP5:%.*]] = load <16 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 16), align 2
-; XOP-NEXT: [[TMP6:%.*]] = ashr <16 x i16> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <16 x i16> [[TMP6]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP1:%.*]] = load <8 x i16>, ptr @a16, align 2
+; XOP-NEXT: [[TMP2:%.*]] = load <8 x i16>, ptr @b16, align 2
+; XOP-NEXT: [[TMP3:%.*]] = ashr <8 x i16> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <8 x i16> [[TMP3]], ptr @c16, align 2
+; XOP-NEXT: [[TMP4:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP5:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP6:%.*]] = ashr <8 x i16> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <8 x i16> [[TMP6]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 8), align 2
+; XOP-NEXT: [[TMP7:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP8:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP9:%.*]] = ashr <8 x i16> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <8 x i16> [[TMP9]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 16), align 2
+; XOP-NEXT: [[TMP10:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 24), align 2
+; XOP-NEXT: [[TMP11:%.*]] = load <8 x i16>, ptr getelementptr inbounds ([32 x i16], ptr @b16, i32 0, i64 24), align 2
+; XOP-NEXT: [[TMP12:%.*]] = ashr <8 x i16> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <8 x i16> [[TMP12]], ptr getelementptr inbounds ([32 x i16], ptr @c16, i32 0, i64 24), align 2
; XOP-NEXT: ret void
;
%a0 = load i16, ptr getelementptr inbounds ([32 x i16], ptr @a16, i32 0, i64 0 ), align 2
@@ -494,14 +518,22 @@ define void @ashr_v64i8() {
; AVX512-NEXT: ret void
;
; XOP-LABEL: @ashr_v64i8(
-; XOP-NEXT: [[TMP1:%.*]] = load <32 x i8>, ptr @a8, align 1
-; XOP-NEXT: [[TMP2:%.*]] = load <32 x i8>, ptr @b8, align 1
-; XOP-NEXT: [[TMP3:%.*]] = ashr <32 x i8> [[TMP1]], [[TMP2]]
-; XOP-NEXT: store <32 x i8> [[TMP3]], ptr @c8, align 1
-; XOP-NEXT: [[TMP4:%.*]] = load <32 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 32), align 1
-; XOP-NEXT: [[TMP5:%.*]] = load <32 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 32), align 1
-; XOP-NEXT: [[TMP6:%.*]] = ashr <32 x i8> [[TMP4]], [[TMP5]]
-; XOP-NEXT: store <32 x i8> [[TMP6]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP1:%.*]] = load <16 x i8>, ptr @a8, align 1
+; XOP-NEXT: [[TMP2:%.*]] = load <16 x i8>, ptr @b8, align 1
+; XOP-NEXT: [[TMP3:%.*]] = ashr <16 x i8> [[TMP1]], [[TMP2]]
+; XOP-NEXT: store <16 x i8> [[TMP3]], ptr @c8, align 1
+; XOP-NEXT: [[TMP4:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP5:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP6:%.*]] = ashr <16 x i8> [[TMP4]], [[TMP5]]
+; XOP-NEXT: store <16 x i8> [[TMP6]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 16), align 1
+; XOP-NEXT: [[TMP7:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP8:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP9:%.*]] = ashr <16 x i8> [[TMP7]], [[TMP8]]
+; XOP-NEXT: store <16 x i8> [[TMP9]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 32), align 1
+; XOP-NEXT: [[TMP10:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 48), align 1
+; XOP-NEXT: [[TMP11:%.*]] = load <16 x i8>, ptr getelementptr inbounds ([64 x i8], ptr @b8, i32 0, i64 48), align 1
+; XOP-NEXT: [[TMP12:%.*]] = ashr <16 x i8> [[TMP10]], [[TMP11]]
+; XOP-NEXT: store <16 x i8> [[TMP12]], ptr getelementptr inbounds ([64 x i8], ptr @c8, i32 0, i64 48), align 1
; XOP-NEXT: ret void
;
%a0 = load i8, ptr getelementptr inbounds ([64 x i8], ptr @a8, i32 0, i64 0 ), align 1
>From 95eda2e3b3a559c81764c4a37bb44def275f322b Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Fri, 25 Sep 2026 15:41:57 +0530
Subject: [PATCH 08/10] [X86] Clean up Bulldozer FMA test
---
llvm/test/Transforms/SLPVectorizer/X86/fma.ll | 46 +++++++++++++++++--
.../SLPVectorizer/X86/reorder_repeated_ops.ll | 2 +-
2 files changed, 44 insertions(+), 4 deletions(-)
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
index 5d30f5431fe04..97cb4ef620a50 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/fma.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
; RUN: opt < %s -mtriple=x86_64-unknown -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=corei7-avx -passes=slp-vectorizer -S | FileCheck %s --check-prefix=NO-FMA
-; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA128,FMA256
+; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=bdver1 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA128
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=core-avx2 -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=-prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA512
; RUN: opt < %s -mtriple=x86_64-unknown -mcpu=skylake-avx512 -mattr=+prefer-256-bit -passes=slp-vectorizer -S | FileCheck %s --check-prefixes=FMA,FMA256
@@ -100,6 +100,14 @@ define void @fma_4f64() #0 {
; FMA128-NEXT: store <2 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 2), align 8
; FMA128-NEXT: ret void
;
+; FMA256-LABEL: @fma_4f64(
+; FMA256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
+; FMA256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
+; FMA256-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 8
+; FMA256-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
+; FMA256-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 8
+; FMA256-NEXT: ret void
+;
; FMA512-LABEL: @fma_4f64(
; FMA512-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 8
; FMA512-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 8
@@ -198,6 +206,19 @@ define void @fma_8f64() #0 {
; FMA128-NEXT: store <2 x double> [[TMP16]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 6), align 4
; FMA128-NEXT: ret void
;
+; FMA256-LABEL: @fma_8f64(
+; FMA256-NEXT: [[TMP1:%.*]] = load <4 x double>, ptr @srcA64, align 4
+; FMA256-NEXT: [[TMP2:%.*]] = load <4 x double>, ptr @srcB64, align 4
+; FMA256-NEXT: [[TMP3:%.*]] = load <4 x double>, ptr @srcC64, align 4
+; FMA256-NEXT: [[TMP4:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP1]], <4 x double> [[TMP2]], <4 x double> [[TMP3]])
+; FMA256-NEXT: store <4 x double> [[TMP4]], ptr @dst64, align 4
+; FMA256-NEXT: [[TMP5:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcA64, i32 0, i64 4), align 4
+; FMA256-NEXT: [[TMP6:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcB64, i32 0, i64 4), align 4
+; FMA256-NEXT: [[TMP7:%.*]] = load <4 x double>, ptr getelementptr inbounds ([8 x double], ptr @srcC64, i32 0, i64 4), align 4
+; FMA256-NEXT: [[TMP8:%.*]] = call <4 x double> @llvm.fma.v4f64(<4 x double> [[TMP5]], <4 x double> [[TMP6]], <4 x double> [[TMP7]])
+; FMA256-NEXT: store <4 x double> [[TMP8]], ptr getelementptr inbounds ([8 x double], ptr @dst64, i32 0, i64 4), align 4
+; FMA256-NEXT: ret void
+;
; FMA512-LABEL: @fma_8f64(
; FMA512-NEXT: [[TMP1:%.*]] = load <8 x double>, ptr @srcA64, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <8 x double>, ptr @srcB64, align 4
@@ -361,6 +382,14 @@ define void @fma_8f32() #0 {
; FMA128-NEXT: store <4 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 4), align 4
; FMA128-NEXT: ret void
;
+; FMA256-LABEL: @fma_8f32(
+; FMA256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; FMA256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; FMA256-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
+; FMA256-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
+; FMA256-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
+; FMA256-NEXT: ret void
+;
; FMA512-LABEL: @fma_8f32(
; FMA512-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
@@ -519,6 +548,19 @@ define void @fma_16f32() #0 {
; FMA128-NEXT: store <4 x float> [[TMP16]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 12), align 4
; FMA128-NEXT: ret void
;
+; FMA256-LABEL: @fma_16f32(
+; FMA256-NEXT: [[TMP1:%.*]] = load <8 x float>, ptr @srcA32, align 4
+; FMA256-NEXT: [[TMP2:%.*]] = load <8 x float>, ptr @srcB32, align 4
+; FMA256-NEXT: [[TMP3:%.*]] = load <8 x float>, ptr @srcC32, align 4
+; FMA256-NEXT: [[TMP4:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP1]], <8 x float> [[TMP2]], <8 x float> [[TMP3]])
+; FMA256-NEXT: store <8 x float> [[TMP4]], ptr @dst32, align 4
+; FMA256-NEXT: [[TMP5:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcA32, i32 0, i64 8), align 4
+; FMA256-NEXT: [[TMP6:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcB32, i32 0, i64 8), align 4
+; FMA256-NEXT: [[TMP7:%.*]] = load <8 x float>, ptr getelementptr inbounds ([16 x float], ptr @srcC32, i32 0, i64 8), align 4
+; FMA256-NEXT: [[TMP8:%.*]] = call <8 x float> @llvm.fma.v8f32(<8 x float> [[TMP5]], <8 x float> [[TMP6]], <8 x float> [[TMP7]])
+; FMA256-NEXT: store <8 x float> [[TMP8]], ptr getelementptr inbounds ([16 x float], ptr @dst32, i32 0, i64 8), align 4
+; FMA256-NEXT: ret void
+;
; FMA512-LABEL: @fma_16f32(
; FMA512-NEXT: [[TMP1:%.*]] = load <16 x float>, ptr @srcA32, align 4
; FMA512-NEXT: [[TMP2:%.*]] = load <16 x float>, ptr @srcB32, align 4
@@ -611,5 +653,3 @@ define void @fma_16f32() #0 {
}
attributes #0 = { nounwind }
-;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
-; FMA256: {{.*}}
diff --git a/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll b/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
index f6c6372b4915b..5f2199aef17ee 100644
--- a/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
+++ b/llvm/test/Transforms/SLPVectorizer/X86/reorder_repeated_ops.ll
@@ -6,7 +6,7 @@ target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
define void @hoge(i1 %arg) {
; CHECK-LABEL: @hoge(
; CHECK-NEXT: bb:
-; CHECK-NEXT: br i1 [[ARG:%.*]], label [[BB1:%.*]], label [[BB2:%.*]]
+; CHECK-NEXT: br i1 %arg, label [[BB1:%.*]], label [[BB2:%.*]]
; CHECK: bb1:
; CHECK-NEXT: ret void
; CHECK: bb2:
>From 48aa22259fbcce328c8a3c9c7c7b4c1e650979c4 Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Mon, 28 Sep 2026 14:03:19 +0530
Subject: [PATCH 09/10] [X86] Add Bulldozer release note
---
llvm/docs/ReleaseNotes.md | 1 +
1 file changed, 1 insertion(+)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 055f3d5ca89a6..2da4fe973aa48 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -288,6 +288,7 @@ Makes programs 10x faster by doing Special New Thing.
* Added assembler and code generation support for the `AVX10_V2_AUX`
instruction set.
+* Added a 128-bit vector width preference for AMD Bulldozer CPUs.
### Changes to the OCaml bindings
>From 84c7a0b3eaac90af973d746a80925fbfea5e2839 Mon Sep 17 00:00:00 2001
From: Aman Chadha <aman.chadha.mmi at gmail.com>
Date: Mon, 28 Sep 2026 21:19:48 +0530
Subject: [PATCH 10/10] [X86] Refine Bulldozer release note
---
llvm/docs/ReleaseNotes.md | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/llvm/docs/ReleaseNotes.md b/llvm/docs/ReleaseNotes.md
index 2da4fe973aa48..3bd164b71c31a 100644
--- a/llvm/docs/ReleaseNotes.md
+++ b/llvm/docs/ReleaseNotes.md
@@ -288,7 +288,8 @@ Makes programs 10x faster by doing Special New Thing.
* Added assembler and code generation support for the `AVX10_V2_AUX`
instruction set.
-* Added a 128-bit vector width preference for AMD Bulldozer CPUs.
+* AMD Bulldozer CPUs (bdver1/2/3/4) now only vectorize to 128-bit vector widths
+ by default to improve multi-threaded performance.
### Changes to the OCaml bindings
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