[llvm] [AArch64] Add custom v2i32->v2i16 store lowering. (PR #223659)
David Green via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 28 05:56:59 PDT 2026
https://github.com/davemgreen updated https://github.com/llvm/llvm-project/pull/223659
>From 2e7cc489776e093b0ca8a7acc9b2c68f5b157bf5 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Tue, 15 Sep 2026 12:24:04 +0100
Subject: [PATCH 1/2] [AArch64] Add custom v2i32->v2i16 store lowering.
This extends the existing v4i16->v4i8 lowering to handle v2i32->v2i16 stores
too, which in general helps keep the number of instructions down.
---
.../Target/AArch64/AArch64ISelLowering.cpp | 24 +++---
llvm/test/CodeGen/AArch64/add.ll | 5 +-
llvm/test/CodeGen/AArch64/andorxor.ll | 25 +++---
llvm/test/CodeGen/AArch64/arm64-rev.ll | 8 +-
.../CodeGen/AArch64/arm64-storebytesmerge.ll | 2 +-
llvm/test/CodeGen/AArch64/bitcast.ll | 11 +--
llvm/test/CodeGen/AArch64/ctlz.ll | 5 +-
llvm/test/CodeGen/AArch64/ctpop.ll | 5 +-
llvm/test/CodeGen/AArch64/cttz.ll | 5 +-
llvm/test/CodeGen/AArch64/ldst-opt.ll | 5 +-
llvm/test/CodeGen/AArch64/mul.ll | 5 +-
llvm/test/CodeGen/AArch64/neon-rshrn.ll | 9 +-
llvm/test/CodeGen/AArch64/neon-truncstore.ll | 18 ++--
llvm/test/CodeGen/AArch64/sadd_sat_vec.ll | 5 +-
llvm/test/CodeGen/AArch64/shufflevector.ll | 14 ++--
llvm/test/CodeGen/AArch64/ssub_sat_vec.ll | 5 +-
llvm/test/CodeGen/AArch64/store.ll | 20 +++--
llvm/test/CodeGen/AArch64/sub.ll | 5 +-
llvm/test/CodeGen/AArch64/uadd_sat_vec.ll | 5 +-
llvm/test/CodeGen/AArch64/usub_sat_vec.ll | 5 +-
.../AArch64/vec3-loads-ext-trunc-stores.ll | 83 ++++++++++---------
21 files changed, 125 insertions(+), 144 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index 99be309f6bc9d..a7bbc8684faee 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1513,6 +1513,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
}
setTruncStoreAction(MVT::v4i16, MVT::v4i8, Custom);
+ setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
setOperationAction(ISD::BITCAST, MVT::i2, Custom);
setOperationAction(ISD::BITCAST, MVT::i4, Custom);
@@ -7785,7 +7786,8 @@ static SDValue LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST,
EVT VT, EVT MemVT,
SelectionDAG &DAG) {
assert(VT.isVector() && "VT should be a vector type");
- assert(MemVT == MVT::v4i8 && VT == MVT::v4i16);
+ assert((MemVT == MVT::v4i8 && VT == MVT::v4i16) ||
+ (MemVT == MVT::v2i16 && VT == MVT::v2i32));
SDValue Value = ST->getValue();
@@ -7796,19 +7798,18 @@ static SDValue LowerTruncateVectorStore(SDLoc DL, StoreSDNode *ST,
// xtn v0.8b, v0.8h
// str s0, [x0]
- SDValue Poison = DAG.getPOISON(MVT::i16);
- SDValue PoisonVec =
- DAG.getBuildVector(MVT::v4i16, DL, {Poison, Poison, Poison, Poison});
-
+ SDValue PoisonVec = DAG.getPOISON(VT);
+ EVT DblVT = VT.getDoubleNumVectorElementsVT(*DAG.getContext());
+ EVT DblMemVT = MemVT.getDoubleNumVectorElementsVT(*DAG.getContext());
SDValue TruncExt =
- DAG.getNode(ISD::CONCAT_VECTORS, DL, MVT::v8i16, Value, PoisonVec);
- SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::v8i8, TruncExt);
+ DAG.getNode(ISD::CONCAT_VECTORS, DL, DblVT, Value, PoisonVec);
+ SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, DblMemVT, TruncExt);
Trunc = DAG.getNode(ISD::BITCAST, DL, MVT::v2i32, Trunc);
SDValue ExtractTrunc = DAG.getExtractVectorElt(DL, MVT::i32, Trunc, 0);
- return DAG.getStore(ST->getChain(), DL, ExtractTrunc,
- ST->getBasePtr(), ST->getMemOperand());
+ return DAG.getStore(ST->getChain(), DL, ExtractTrunc, ST->getBasePtr(),
+ ST->getMemOperand());
}
static SDValue LowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) {
@@ -8073,8 +8074,9 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
return scalarizeVectorStore(StoreNode, DAG);
}
- if (StoreNode->isTruncatingStore() && VT == MVT::v4i16 &&
- MemVT == MVT::v4i8) {
+ if (StoreNode->isTruncatingStore() &&
+ ((VT == MVT::v4i16 && MemVT == MVT::v4i8) ||
+ (VT == MVT::v2i32 && MemVT == MVT::v2i16))) {
return LowerTruncateVectorStore(Dl, StoreNode, VT, MemVT, DAG);
}
} else if (MemVT == MVT::i128 && StoreNode->isVolatile()) {
diff --git a/llvm/test/CodeGen/AArch64/add.ll b/llvm/test/CodeGen/AArch64/add.ll
index f71c58f16bf36..40c3e6560edcb 100644
--- a/llvm/test/CodeGen/AArch64/add.ll
+++ b/llvm/test/CodeGen/AArch64/add.ll
@@ -198,9 +198,8 @@ define void @v2i16(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/andorxor.ll b/llvm/test/CodeGen/AArch64/andorxor.ll
index 6e1f7710b4cd8..adf560cc97362 100644
--- a/llvm/test/CodeGen/AArch64/andorxor.ll
+++ b/llvm/test/CodeGen/AArch64/andorxor.ll
@@ -608,11 +608,10 @@ define void @and_v2i16(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h
-; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-SD-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-SD-NEXT: and v0.8b, v0.8b, v1.8b
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: and_v2i16:
@@ -641,12 +640,11 @@ define void @or_v2i16(ptr %p1, ptr %p2) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-SD-NEXT: orr v0.8b, v0.8b, v1.8b
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: or_v2i16:
@@ -675,12 +673,11 @@ define void @xor_v2i16(ptr %p1, ptr %p2) {
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
-; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
+; CHECK-SD-NEXT: zip1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: zip1 v1.4h, v1.4h, v1.4h
; CHECK-SD-NEXT: eor v0.8b, v0.8b, v1.8b
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: xor_v2i16:
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index 5980e3214d0da..42afc0831d914 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -464,9 +464,11 @@ define void @test_vrev64(ptr nocapture %source, ptr nocapture %dst) nounwind ssp
; CHECK-SD-LABEL: test_vrev64:
; CHECK-SD: // %bb.0: // %entry
; CHECK-SD-NEXT: ldr q0, [x0]
-; CHECK-SD-NEXT: mov h1, v0[5]
-; CHECK-SD-NEXT: st1.h { v0 }[6], [x1]
-; CHECK-SD-NEXT: str h1, [x1, #2]
+; CHECK-SD-NEXT: mov h1, v0[6]
+; CHECK-SD-NEXT: umov.h w8, v0[5]
+; CHECK-SD-NEXT: mov.s v1[1], w8
+; CHECK-SD-NEXT: xtn.4h v0, v1
+; CHECK-SD-NEXT: str s0, [x1]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: test_vrev64:
diff --git a/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll b/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
index 1486b3a8b9cff..ddbd6fc839441 100644
--- a/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-storebytesmerge.ll
@@ -8,7 +8,7 @@
; CHECK: str x30, [sp, #-16]!
; CHECK: adrp x8, q
; CHECK: ldr x8, [x8, :lo12:q]
-; CHECK: stp xzr, xzr, [x8]
+; CHECK: str q0, [x8]
; CHECK: bl f
@q = external dso_local unnamed_addr global ptr, align 8
diff --git a/llvm/test/CodeGen/AArch64/bitcast.ll b/llvm/test/CodeGen/AArch64/bitcast.ll
index f293934572b16..efac5578b8df6 100644
--- a/llvm/test/CodeGen/AArch64/bitcast.ll
+++ b/llvm/test/CodeGen/AArch64/bitcast.ll
@@ -86,10 +86,8 @@ define i32 @bitcast_v2i16_i32(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [sp, #12]
-; CHECK-SD-NEXT: str h1, [sp, #14]
-; CHECK-SD-NEXT: ldr w0, [sp, #12]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
;
@@ -372,10 +370,7 @@ define <4 x i8> @bitcast_v2i16_v4i8(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [sp, #12]
-; CHECK-SD-NEXT: str h1, [sp, #14]
-; CHECK-SD-NEXT: ldr s0, [sp, #12]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
; CHECK-SD-NEXT: ushll v0.8h, v0.8b, #0
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 killed $q0
; CHECK-SD-NEXT: add sp, sp, #16
diff --git a/llvm/test/CodeGen/AArch64/ctlz.ll b/llvm/test/CodeGen/AArch64/ctlz.ll
index 968fd6d7c9813..0b8e18482f1ea 100644
--- a/llvm/test/CodeGen/AArch64/ctlz.ll
+++ b/llvm/test/CodeGen/AArch64/ctlz.ll
@@ -133,9 +133,8 @@ define void @v2i16(ptr %p1) {
; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-SD-NEXT: clz v1.2s, v1.2s
; CHECK-SD-NEXT: sub v0.2s, v1.2s, v0.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/ctpop.ll b/llvm/test/CodeGen/AArch64/ctpop.ll
index 00d3542988272..345449b3149a7 100644
--- a/llvm/test/CodeGen/AArch64/ctpop.ll
+++ b/llvm/test/CodeGen/AArch64/ctpop.ll
@@ -131,9 +131,8 @@ define void @v2i16(ptr %p1) {
; CHECK-SD-NEXT: cnt v0.8b, v0.8b
; CHECK-SD-NEXT: uaddlp v0.4h, v0.8b
; CHECK-SD-NEXT: uaddlp v0.2s, v0.4h
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/cttz.ll b/llvm/test/CodeGen/AArch64/cttz.ll
index a7cb028537088..8f46f389cb68e 100644
--- a/llvm/test/CodeGen/AArch64/cttz.ll
+++ b/llvm/test/CodeGen/AArch64/cttz.ll
@@ -191,9 +191,8 @@ define void @v2i16(ptr %p1) {
; CHECK-SD-NEXT: rev32 v0.8b, v0.8b
; CHECK-SD-NEXT: rbit v0.8b, v0.8b
; CHECK-SD-NEXT: clz v0.2s, v0.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/ldst-opt.ll b/llvm/test/CodeGen/AArch64/ldst-opt.ll
index e002f3fba9d5b..6bb9bcc32be7c 100644
--- a/llvm/test/CodeGen/AArch64/ldst-opt.ll
+++ b/llvm/test/CodeGen/AArch64/ldst-opt.ll
@@ -2260,9 +2260,8 @@ define void @trunc_splat_zero(ptr %ptr) {
define void @trunc_splat(ptr %ptr) {
; CHECK-LABEL: trunc_splat:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov w8, #42 // =0x2a
-; CHECK-NEXT: movk w8, #42, lsl #16
-; CHECK-NEXT: str w8, [x0]
+; CHECK-NEXT: movi v0.8h, #42
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
store <2 x i16> <i16 42, i16 42>, ptr %ptr, align 4
ret void
diff --git a/llvm/test/CodeGen/AArch64/mul.ll b/llvm/test/CodeGen/AArch64/mul.ll
index dfd6f9801e54b..c89d1c290fa16 100644
--- a/llvm/test/CodeGen/AArch64/mul.ll
+++ b/llvm/test/CodeGen/AArch64/mul.ll
@@ -211,9 +211,8 @@ define void @v2i16(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: umull v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: xtn v0.4h, v0.4s
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/neon-rshrn.ll b/llvm/test/CodeGen/AArch64/neon-rshrn.ll
index 4cc8df59c95db..599709f0741f1 100644
--- a/llvm/test/CodeGen/AArch64/neon-rshrn.ll
+++ b/llvm/test/CodeGen/AArch64/neon-rshrn.ll
@@ -865,12 +865,9 @@ entry:
define void @rshrn_v2i32_4(<2 x i32> %a, ptr %p) {
; CHECK-LABEL: rshrn_v2i32_4:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: movi v1.2s, #8
-; CHECK-NEXT: add v0.2s, v0.2s, v1.2s
-; CHECK-NEXT: ushr v0.2s, v0.2s, #4
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: rshrn v0.4h, v0.4s, #4
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
entry:
%b = add <2 x i32> %a, <i32 8, i32 8>
diff --git a/llvm/test/CodeGen/AArch64/neon-truncstore.ll b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
index 88e1deff375c1..16636e6f91be7 100644
--- a/llvm/test/CodeGen/AArch64/neon-truncstore.ll
+++ b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
@@ -41,10 +41,8 @@ define void @v8i64_v8i32(<8 x i64> %a, ptr %result) {
define void @v2i32_v2i16(<2 x i32> %a, ptr %result) {
; CHECK-LABEL: v2i32_v2i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%b = trunc <2 x i32> %a to <2 x i16>
store <2 x i16> %b, ptr %result
@@ -213,9 +211,9 @@ define void @v32i16_v32i8(<32 x i16> %a, ptr %result) {
define void @extract_v2i16_v8i16(<8 x i16> %a, ptr %p) {
; CHECK-LABEL: extract_v2i16_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov h1, v0.h[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
+; CHECK-NEXT: xtn v0.4h, v0.4s
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%c = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
store <2 x i16> %c, ptr %p
@@ -235,10 +233,8 @@ define void @extract_v4i16_v8i16(<8 x i16> %a, ptr %p) {
define void @extract_v2i16_v4i16(<4 x i16> %a, ptr %p) {
; CHECK-LABEL: extract_v2i16_v4i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: ushll v0.4s, v0.4h, #0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%c = shufflevector <4 x i16> %a, <4 x i16> poison, <2 x i32> <i32 0, i32 1>
store <2 x i16> %c, ptr %p
diff --git a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
index 8d3a9ee8beba4..2021d7ed468a7 100644
--- a/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/sadd_sat_vec.ll
@@ -203,9 +203,8 @@ define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
; CHECK-SD-NEXT: sqadd v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #16
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x2]
-; CHECK-SD-NEXT: str h1, [x2, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x2]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/shufflevector.ll b/llvm/test/CodeGen/AArch64/shufflevector.ll
index 9fd5e65086782..59e406f64b14b 100644
--- a/llvm/test/CodeGen/AArch64/shufflevector.ll
+++ b/llvm/test/CodeGen/AArch64/shufflevector.ll
@@ -287,10 +287,8 @@ define i32 @shufflevector_v2i16(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: ext v0.8b, v0.8b, v1.8b, #4
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [sp, #12]
-; CHECK-SD-NEXT: str h1, [sp, #14]
-; CHECK-SD-NEXT: ldr w0, [sp, #12]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
;
@@ -491,11 +489,9 @@ define i32 @shufflevector_v2i16_zeroes(<2 x i16> %a, <2 x i16> %b){
; CHECK-SD-NEXT: sub sp, sp, #16
; CHECK-SD-NEXT: .cfi_def_cfa_offset 16
; CHECK-SD-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-SD-NEXT: dup v1.2s, v0.s[0]
-; CHECK-SD-NEXT: str h0, [sp, #12]
-; CHECK-SD-NEXT: mov s1, v1.s[1]
-; CHECK-SD-NEXT: str h1, [sp, #14]
-; CHECK-SD-NEXT: ldr w0, [sp, #12]
+; CHECK-SD-NEXT: dup v0.2s, v0.s[0]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: fmov w0, s0
; CHECK-SD-NEXT: add sp, sp, #16
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
index f4359edcc1bbd..1f92884f02f71 100644
--- a/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/ssub_sat_vec.ll
@@ -203,9 +203,8 @@ define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-SD-NEXT: shl v0.2s, v0.2s, #16
; CHECK-SD-NEXT: sqsub v0.2s, v0.2s, v1.2s
; CHECK-SD-NEXT: ushr v0.2s, v0.2s, #16
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x2]
-; CHECK-SD-NEXT: str h1, [x2, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x2]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/store.ll b/llvm/test/CodeGen/AArch64/store.ll
index 5daf8c2317ca0..821ab104b9ae4 100644
--- a/llvm/test/CodeGen/AArch64/store.ll
+++ b/llvm/test/CodeGen/AArch64/store.ll
@@ -169,13 +169,19 @@ define void @store_v32i8(<32 x i8> %a, ptr %ptr){
}
define void @store_v2i16(<2 x i16> %a, ptr %ptr){
-; CHECK-LABEL: store_v2i16:
-; CHECK: // %bb.0:
-; CHECK-NEXT: // kill: def $d0 killed $d0 def $q0
-; CHECK-NEXT: mov s1, v0.s[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
-; CHECK-NEXT: ret
+; CHECK-SD-LABEL: store_v2i16:
+; CHECK-SD: // %bb.0:
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
+; CHECK-SD-NEXT: ret
+;
+; CHECK-GI-LABEL: store_v2i16:
+; CHECK-GI: // %bb.0:
+; CHECK-GI-NEXT: // kill: def $d0 killed $d0 def $q0
+; CHECK-GI-NEXT: mov s1, v0.s[1]
+; CHECK-GI-NEXT: str h0, [x0]
+; CHECK-GI-NEXT: str h1, [x0, #2]
+; CHECK-GI-NEXT: ret
store <2 x i16> %a, ptr %ptr
ret void
}
diff --git a/llvm/test/CodeGen/AArch64/sub.ll b/llvm/test/CodeGen/AArch64/sub.ll
index 4516cf821af20..70f7e43b73584 100644
--- a/llvm/test/CodeGen/AArch64/sub.ll
+++ b/llvm/test/CodeGen/AArch64/sub.ll
@@ -198,9 +198,8 @@ define void @v2i16(ptr %p1, ptr %p2) {
; CHECK-SD-NEXT: ldr s0, [x0]
; CHECK-SD-NEXT: ldr s1, [x1]
; CHECK-SD-NEXT: usubl v0.4s, v0.4h, v1.4h
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x0]
-; CHECK-SD-NEXT: str h1, [x0, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x0]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
index 3f9f420d8f2bb..6768c733af47f 100644
--- a/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/uadd_sat_vec.ll
@@ -192,9 +192,8 @@ define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-SD-NEXT: movi d2, #0x00ffff0000ffff
; CHECK-SD-NEXT: uaddl v0.4s, v0.4h, v1.4h
; CHECK-SD-NEXT: umin v0.2s, v0.2s, v2.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x2]
-; CHECK-SD-NEXT: str h1, [x2, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x2]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
index c8f59a95addb3..04a67ecf534c6 100644
--- a/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
+++ b/llvm/test/CodeGen/AArch64/usub_sat_vec.ll
@@ -192,9 +192,8 @@ define void @v2i16(ptr %px, ptr %py, ptr %pz) nounwind {
; CHECK-SD-NEXT: ushll v0.4s, v0.4h, #0
; CHECK-SD-NEXT: ushll v1.4s, v1.4h, #0
; CHECK-SD-NEXT: uqsub v0.2s, v0.2s, v1.2s
-; CHECK-SD-NEXT: mov s1, v0.s[1]
-; CHECK-SD-NEXT: str h0, [x2]
-; CHECK-SD-NEXT: str h1, [x2, #2]
+; CHECK-SD-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; CHECK-SD-NEXT: str s0, [x2]
; CHECK-SD-NEXT: ret
;
; CHECK-GI-LABEL: v2i16:
diff --git a/llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll b/llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
index b58af24483b25..0d58deda34b8e 100644
--- a/llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
+++ b/llvm/test/CodeGen/AArch64/vec3-loads-ext-trunc-stores.ll
@@ -15,9 +15,9 @@ define <16 x i8> @load_v3i8(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: umov w8, v0.h[0]
@@ -51,10 +51,10 @@ define <4 x i32> @load_v3i8_to_4xi32(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: ldrsb w8, [x0, #2]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: mov v0.h[1], v0.h[1]
@@ -87,10 +87,10 @@ define <4 x i32> @load_v3i8_to_4xi32_align_2(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: ldrsb w8, [x0, #2]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: mov v0.h[1], v0.h[1]
@@ -148,10 +148,11 @@ define <4 x i32> @load_v3i8_to_4xi32_const_offset_1(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldurh w8, [x0, #1]
-; BE-NEXT: strh w8, [sp, #12]
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: add x8, x0, #1
+; BE-NEXT: ld1 { v0.h }[0], [x8]
; BE-NEXT: ldrsb w8, [x0, #3]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: mov v0.h[1], v0.h[1]
@@ -185,10 +186,11 @@ define <4 x i32> @load_v3i8_to_4xi32_const_offset_3(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldurh w8, [x0, #3]
-; BE-NEXT: strh w8, [sp, #12]
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: add x8, x0, #3
+; BE-NEXT: ld1 { v0.h }[0], [x8]
; BE-NEXT: ldrsb w8, [x0, #5]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: mov v0.h[1], v0.h[1]
@@ -211,10 +213,9 @@ define <4 x i32> @volatile_load_v3i8_to_4xi32(ptr %src) {
; CHECK: ; %bb.0:
; CHECK-NEXT: sub sp, sp, #16
; CHECK-NEXT: .cfi_def_cfa_offset 16
-; CHECK-NEXT: ldrh w8, [x0]
-; CHECK-NEXT: strh w8, [sp, #12]
-; CHECK-NEXT: ldr s0, [sp, #12]
+; CHECK-NEXT: ld1.h { v0 }[0], [x0]
; CHECK-NEXT: ldrsb w8, [x0, #2]
+; CHECK-NEXT: uzp1.4h v0, v0, v0
; CHECK-NEXT: ushll.8h v0, v0, #0
; CHECK-NEXT: mov.h v0[1], v0[1]
; CHECK-NEXT: mov.h v0[2], w8
@@ -227,10 +228,10 @@ define <4 x i32> @volatile_load_v3i8_to_4xi32(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: ldrsb w8, [x0, #2]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: mov v0.h[1], v0.h[1]
@@ -284,10 +285,10 @@ define <3 x i32> @load_v3i8_zext_to_3xi32(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: add x8, x0, #2
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: ld1 { v0.b }[4], [x8]
@@ -319,10 +320,10 @@ define <3 x i32> @load_v3i8_sext_to_3xi32(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: add x8, x0, #2
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: ld1 { v0.b }[4], [x8]
@@ -440,10 +441,10 @@ define void @load_ext_to_64bits(ptr %src, ptr %dst) {
; BE: // %bb.0: // %entry
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: add x8, x0, #2
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: ld1 { v0.b }[4], [x8]
@@ -543,10 +544,10 @@ define void @load_ext_add_to_64bits(ptr %src, ptr %dst) {
; BE: // %bb.0: // %entry
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w8, [x0]
-; BE-NEXT: strh w8, [sp, #12]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: add x8, x0, #2
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: ld1 { v0.b }[4], [x8]
@@ -803,13 +804,13 @@ define void @load_v3i8_zext_to_3xi32_add_trunc_store(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w9, [x0]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: adrp x8, .LCPI22_0
; BE-NEXT: add x8, x8, :lo12:.LCPI22_0
-; BE-NEXT: ld1 { v1.4h }, [x8]
-; BE-NEXT: strh w9, [sp, #12]
; BE-NEXT: add x9, x0, #2
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: ld1 { v1.4h }, [x8]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: ld1 { v0.b }[4], [x9]
@@ -856,13 +857,13 @@ define void @load_v3i8_sext_to_3xi32_add_trunc_store(ptr %src) {
; BE: // %bb.0:
; BE-NEXT: sub sp, sp, #16
; BE-NEXT: .cfi_def_cfa_offset 16
-; BE-NEXT: ldrh w9, [x0]
+; BE-NEXT: ld1 { v0.h }[0], [x0]
; BE-NEXT: adrp x8, .LCPI23_0
; BE-NEXT: add x8, x8, :lo12:.LCPI23_0
-; BE-NEXT: ld1 { v1.4h }, [x8]
-; BE-NEXT: strh w9, [sp, #12]
; BE-NEXT: add x9, x0, #2
-; BE-NEXT: ldr s0, [sp, #12]
+; BE-NEXT: ld1 { v1.4h }, [x8]
+; BE-NEXT: uzp1 v0.4h, v0.4h, v0.4h
+; BE-NEXT: rev32 v0.8h, v0.8h
; BE-NEXT: rev32 v0.8b, v0.8b
; BE-NEXT: ushll v0.8h, v0.8b, #0
; BE-NEXT: ld1 { v0.b }[4], [x9]
>From 69bfcd9ea0d13e368ac5c0c611eea77aa2dc72f9 Mon Sep 17 00:00:00 2001
From: David Green <david.green at arm.com>
Date: Mon, 28 Sep 2026 13:56:33 +0100
Subject: [PATCH 2/2] Update tests after other patches.
---
llvm/test/CodeGen/AArch64/arm64-rev.ll | 7 ++-----
llvm/test/CodeGen/AArch64/ldst-opt.ll | 2 +-
llvm/test/CodeGen/AArch64/lowmaskedlanes.ll | 5 ++---
llvm/test/CodeGen/AArch64/neon-truncstore.ll | 2 --
4 files changed, 5 insertions(+), 11 deletions(-)
diff --git a/llvm/test/CodeGen/AArch64/arm64-rev.ll b/llvm/test/CodeGen/AArch64/arm64-rev.ll
index 42afc0831d914..a3c727c64ec02 100644
--- a/llvm/test/CodeGen/AArch64/arm64-rev.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-rev.ll
@@ -463,11 +463,8 @@ define <8 x i16> @test_vrev32Q16_undef(ptr %A) nounwind {
define void @test_vrev64(ptr nocapture %source, ptr nocapture %dst) nounwind ssp {
; CHECK-SD-LABEL: test_vrev64:
; CHECK-SD: // %bb.0: // %entry
-; CHECK-SD-NEXT: ldr q0, [x0]
-; CHECK-SD-NEXT: mov h1, v0[6]
-; CHECK-SD-NEXT: umov.h w8, v0[5]
-; CHECK-SD-NEXT: mov.s v1[1], w8
-; CHECK-SD-NEXT: xtn.4h v0, v1
+; CHECK-SD-NEXT: ldr d0, [x0, #8]
+; CHECK-SD-NEXT: mov.h v0[0], v0[2]
; CHECK-SD-NEXT: str s0, [x1]
; CHECK-SD-NEXT: ret
;
diff --git a/llvm/test/CodeGen/AArch64/ldst-opt.ll b/llvm/test/CodeGen/AArch64/ldst-opt.ll
index 6bb9bcc32be7c..1d51ce9b553b3 100644
--- a/llvm/test/CodeGen/AArch64/ldst-opt.ll
+++ b/llvm/test/CodeGen/AArch64/ldst-opt.ll
@@ -2260,7 +2260,7 @@ define void @trunc_splat_zero(ptr %ptr) {
define void @trunc_splat(ptr %ptr) {
; CHECK-LABEL: trunc_splat:
; CHECK: // %bb.0:
-; CHECK-NEXT: movi v0.8h, #42
+; CHECK-NEXT: movi v0.4h, #42
; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
store <2 x i16> <i16 42, i16 42>, ptr %ptr, align 4
diff --git a/llvm/test/CodeGen/AArch64/lowmaskedlanes.ll b/llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
index e8de2bdcfb98d..6cc3fc585fe43 100644
--- a/llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
+++ b/llvm/test/CodeGen/AArch64/lowmaskedlanes.ll
@@ -216,9 +216,8 @@ define void @store_low2_v8i16(ptr %p, <8 x i16> %a) vscale_range(2, 2) {
define void @store_low2_nxv8i16(ptr %p, <vscale x 8 x i16> %a) {
; CHECK-LABEL: store_low2_nxv8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: mov z1.h, z0.h[1]
-; CHECK-NEXT: str h0, [x0]
-; CHECK-NEXT: str h1, [x0, #2]
+; CHECK-NEXT: mov v0.h[1], v0.h[1]
+; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%m = tail call <vscale x 8 x i1> @llvm.get.active.lane.mask.nxv8i1.i32(i32 0, i32 2)
tail call void @llvm.masked.store(<vscale x 8 x i16> %a, ptr align 1 %p, <vscale x 8 x i1> %m)
diff --git a/llvm/test/CodeGen/AArch64/neon-truncstore.ll b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
index 16636e6f91be7..712f20e5df0c7 100644
--- a/llvm/test/CodeGen/AArch64/neon-truncstore.ll
+++ b/llvm/test/CodeGen/AArch64/neon-truncstore.ll
@@ -211,8 +211,6 @@ define void @v32i16_v32i8(<32 x i16> %a, ptr %result) {
define void @extract_v2i16_v8i16(<8 x i16> %a, ptr %p) {
; CHECK-LABEL: extract_v2i16_v8i16:
; CHECK: // %bb.0:
-; CHECK-NEXT: zip1 v0.8h, v0.8h, v0.8h
-; CHECK-NEXT: xtn v0.4h, v0.4s
; CHECK-NEXT: str s0, [x0]
; CHECK-NEXT: ret
%c = shufflevector <8 x i16> %a, <8 x i16> poison, <2 x i32> <i32 0, i32 1>
More information about the llvm-commits
mailing list