[llvm] eac5920 - [GlobalISel] Support GISelValueTracking for G_FREEZE. (#223696)
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Mon Sep 28 04:42:18 PDT 2026
Author: Vikash Gupta
Date: 2026-09-28T17:12:11+05:30
New Revision: eac59201583b098cbd6b4b4619d165e90f50937d
URL: https://github.com/llvm/llvm-project/commit/eac59201583b098cbd6b4b4619d165e90f50937d
DIFF: https://github.com/llvm/llvm-project/commit/eac59201583b098cbd6b4b4619d165e90f50937d.diff
LOG: [GlobalISel] Support GISelValueTracking for G_FREEZE. (#223696)
Port the SDAG FREEZE handling to GlobalISel. Look through G_FREEZE in
computeKnownBits, computeNumSignBits, and computeKnownFPClass when the
source is guaranteed not undef or poison.
Part of #150515.
---------
Co-authored-by: Matt Arsenault <arsenm2 at gmail.com>
Added:
llvm/test/CodeGen/AArch64/GlobalISel/knownbits-freeze.mir
Modified:
llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
index 1a3bcd8e579ee..71b68e223959e 100644
--- a/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
+++ b/llvm/lib/CodeGen/GlobalISel/GISelValueTracking.cpp
@@ -326,6 +326,14 @@ void GISelValueTracking::computeKnownBitsImpl(Register R, KnownBits &Known,
Known = Known.trunc(BitWidth);
break;
}
+ case TargetOpcode::G_FREEZE: {
+ Register Src = MI.getOperand(1).getReg();
+ // freeze of undef/poison is an arbitrary noundef bit pattern, so the known
+ // bits of the source only carry over when it cannot be undef or poison.
+ if (isGuaranteedNotToBeUndefOrPoison(Src, MRI, Depth + 1))
+ computeKnownBitsImpl(Src, Known, DemandedElts, Depth + 1);
+ break;
+ }
case TargetOpcode::COPY:
case TargetOpcode::G_PHI:
case TargetOpcode::PHI: {
@@ -2253,6 +2261,14 @@ void GISelValueTracking::computeKnownFPClass(Register R,
}
break;
}
+ case TargetOpcode::G_FREEZE: {
+ Register Src = MI.getOperand(1).getReg();
+ if (isGuaranteedNotToBeUndefOrPoison(Src, MRI, Depth + 1)) {
+ computeKnownFPClass(Src, DemandedElts, InterestedClasses, Known,
+ Depth + 1);
+ }
+ break;
+ }
case TargetOpcode::COPY: {
Register Src = MI.getOperand(1).getReg();
@@ -2472,6 +2488,12 @@ unsigned GISelValueTracking::computeNumSignBits(Register R,
return 1;
}
+ case TargetOpcode::G_FREEZE: {
+ Register Src = MI.getOperand(1).getReg();
+ if (isGuaranteedNotToBeUndefOrPoison(Src, MRI, Depth + 1))
+ return computeNumSignBits(Src, DemandedElts, Depth + 1);
+ break;
+ }
case TargetOpcode::G_SEXT: {
Register Src = MI.getOperand(1).getReg();
LLT SrcTy = MRI.getType(Src);
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-freeze.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-freeze.mir
new file mode 100644
index 0000000000000..3756c282387ee
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownbits-freeze.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_givaluetracking_test_checks.py UTC_ARGS: --version 5
+# RUN: llc -mtriple=aarch64 -passes="print<gisel-value-tracking>" -filetype=null %s 2>&1 | FileCheck %s
+
+---
+name: FreezeAnd
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @FreezeAnd
+ ; CHECK-NEXT: %0:_ KnownBits:00000000000000001111111111111111 SignBits:16 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000111111110000 SignBits:20 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000111111110000 SignBits:20 IsKnownNeverZero:1
+ ; CHECK-NEXT: %3:_ KnownBits:00000000000000000000111111110000 SignBits:20 IsKnownNeverZero:1
+ %0:_(i32) = G_CONSTANT i32 65535
+ %1:_(i32) = G_CONSTANT i32 4080
+ %2:_(i32) = G_AND %0, %1
+ %3:_(i32) = G_FREEZE %2
+...
+---
+name: FreezeCopy
+body: |
+ bb.1:
+ liveins: $w0
+ ; CHECK-LABEL: name: @FreezeCopy
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ %0:_(i32) = COPY $w0
+ %3:_(i32) = G_FREEZE %0
+...
+---
+name: FreezeCopyAnd
+body: |
+ bb.1:
+ liveins: $w0
+ ; CHECK-LABEL: name: @FreezeCopyAnd
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000111111110000 SignBits:20 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000????????0000 SignBits:20 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ %0:_(i32) = COPY $w0
+ %1:_(i32) = G_CONSTANT i32 4080
+ %2:_(i32) = G_AND %0, %1
+ %3:_(i32) = G_FREEZE %2
+...
+---
+name: FreezeNeg1
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @FreezeNeg1
+ ; CHECK-NEXT: %0:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
+ ; CHECK-NEXT: %1:_ KnownBits:11111111 SignBits:8 IsKnownNeverZero:1
+ %0:_(i8) = G_CONSTANT i8 -1
+ %1:_(i8) = G_FREEZE %0
+...
+---
+name: FreezeUndef
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @FreezeUndef
+ ; CHECK-NEXT: %0:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:???????? SignBits:1 IsKnownNeverZero:0
+ %0:_(i8) = G_IMPLICIT_DEF
+ %1:_(i8) = G_FREEZE %0
+...
+---
+name: FreezeAndUndef
+body: |
+ bb.1:
+ ; CHECK-LABEL: name: @FreezeAndUndef
+ ; CHECK-NEXT: %0:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ ; CHECK-NEXT: %1:_ KnownBits:00000000000000000000111111110000 SignBits:20 IsKnownNeverZero:1
+ ; CHECK-NEXT: %2:_ KnownBits:00000000000000000000????????0000 SignBits:20 IsKnownNeverZero:0
+ ; CHECK-NEXT: %3:_ KnownBits:???????????????????????????????? SignBits:1 IsKnownNeverZero:0
+ %0:_(i32) = G_IMPLICIT_DEF
+ %1:_(i32) = G_CONSTANT i32 4080
+ %2:_(i32) = G_AND %0, %1
+ %3:_(i32) = G_FREEZE %2
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir b/llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir
index f0ab44d53a763..0e301d0a4b974 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/knownfpclass-ops.mir
@@ -12,6 +12,32 @@ body: |
%copy:_(s32) = COPY %def
...
---
+name: FreezeNegZero
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @FreezeNegZero
+ ; CHECK-NEXT: %neg0:_ FPClasses:(nzero) SignBitKnown:1
+ ; CHECK-NEXT: %fr:_ FPClasses:(nzero) SignBitKnown:1
+ ; CHECK-NEXT: %copy:_ FPClasses:(nzero) SignBitKnown:1
+ %neg0:_(s32) = G_FCONSTANT float -0.0
+ %fr:_(s32) = G_FREEZE %neg0
+ %copy:_(s32) = COPY %fr
+...
+---
+name: FreezeFabsUndef
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: @FreezeFabsUndef
+ ; CHECK-NEXT: %def:_ FPClasses:(all) SignBitKnown:?
+ ; CHECK-NEXT: %fabs:_ FPClasses:(nan pinf pzero psub pnorm) SignBitKnown:0
+ ; CHECK-NEXT: %fr:_ FPClasses:(all) SignBitKnown:?
+ ; CHECK-NEXT: %copy:_ FPClasses:(all) SignBitKnown:?
+ %def:_(s32) = G_IMPLICIT_DEF
+ %fabs:_(s32) = G_FABS %def
+ %fr:_(s32) = G_FREEZE %fabs
+ %copy:_(s32) = COPY %fr
+...
+---
name: ScalableFAbs
body: |
bb.0:
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