[llvm] [TableGen] Support MachineInstr rewriting in CompressInstEmitter (PR #224212)

[Jiaxun Yang via llvm-commits]

FlyGoat wrote:

Hi @lenary,

I just took a second look of Mips case and it turns out for Mips we can do instructruction compression at same stage as well. We just need some special handling for delay slots (or don't do compression for branch instructions).

Should I persuade that route?

Thanks

https://github.com/llvm/llvm-project/pull/224212