[llvm] [AArch64] ISel support for nxv1i1 vector_reverse (PR #226939)

[Gaëtan Bossu via llvm-commits]

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@@ -13425,6 +13428,18 @@ SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op,
   return SDValue();
 }
 
+SDValue AArch64TargetLowering::LowerVECTOR_REVERSE(SDValue Op,
+                                                   SelectionDAG &DAG) const {
+  assert(Op.getValueType() == MVT::nxv1i1 && "Unexpected vector type!");
+
+  SDLoc DL(Op);
+  // Select nxv1i1 vector_reverse by widening to nxv2i1.
+  SDValue Widened = DAG.getInsertSubvector(DL, DAG.getPOISON(MVT::nxv2i1),
+                                           Op.getOperand(0), 0);
+  SDValue Reversed = DAG.getNode(ISD::VECTOR_REVERSE, DL, MVT::nxv2i1, Widened);
+  return DAG.getExtractSubvector(DL, MVT::nxv1i1, Reversed, 1);
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gbossu wrote:

Checking: We could potentially do a `REV P.d` followed by `TRN2` to duplicate the upper bits to lower bits, but that means that some of the "undefined bits" would be non-zero in the physical register. IIRC, we need to ensure that those bits are zero when constructing a predicate. I.e. for a nxv1i1 type, only `vscale x 1` bits are defined while the rest are zero.

https://github.com/llvm/llvm-project/pull/226939