[llvm] [AArch64] ISel support for nxv1i1 vector_reverse (PR #226939)

[Gaëtan Bossu via llvm-commits]

https://github.com/gbossu created https://github.com/llvm/llvm-project/pull/226939

Follow-up from https://github.com/llvm/llvm-project/pull/214471 which introduced a compilation error in LLVM-test-suite.

>From 24d5e049094543fc5bd11b73f53e23c3d9a54b5d Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ga=C3=ABtan=20Bossu?= <gaetan.bossu at arm.com>
Date: Mon, 28 Sep 2026 09:43:23 +0000
Subject: [PATCH] [AArch64] ISel support for nxv1i1 vector_reverse

---
 .../Target/AArch64/AArch64ISelLowering.cpp    | 15 ++++++++++++++
 llvm/lib/Target/AArch64/AArch64ISelLowering.h |  1 +
 .../named-vector-shuffle-reverse-sve.ll       | 20 +++++++++++++++++++
 3 files changed, 36 insertions(+)

diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index e159aea0868d5..733bdf676e507 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -1677,6 +1677,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
     }
 
     setOperationAction(ISD::GET_ACTIVE_LANE_MASK, MVT::nxv1i1, Custom);
+    setOperationAction(ISD::VECTOR_REVERSE, MVT::nxv1i1, Custom);
 
     if (Subtarget->isSVEorStreamingSVEAvailable() &&
         (Subtarget->hasSVE2p1() || Subtarget->hasSME2()))
@@ -8887,6 +8888,8 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op,
     return LowerVECTOR_REPEAT(Op, DAG);
   case ISD::VECTOR_SHUFFLE:
     return LowerVECTOR_SHUFFLE(Op, DAG);
+  case ISD::VECTOR_REVERSE:
+    return LowerVECTOR_REVERSE(Op, DAG);
   case ISD::SPLAT_VECTOR:
     return LowerSPLAT_VECTOR(Op, DAG);
   case ISD::EXTRACT_SUBVECTOR:
@@ -13425,6 +13428,18 @@ SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op,
   return SDValue();
 }
 
+SDValue AArch64TargetLowering::LowerVECTOR_REVERSE(SDValue Op,
+                                                   SelectionDAG &DAG) const {
+  assert(Op.getValueType() == MVT::nxv1i1 && "Unexpected vector type!");
+
+  SDLoc DL(Op);
+  // Select nxv1i1 vector_reverse by widening to nxv2i1.
+  SDValue Widened = DAG.getInsertSubvector(DL, DAG.getPOISON(MVT::nxv2i1),
+                                           Op.getOperand(0), 0);
+  SDValue Reversed = DAG.getNode(ISD::VECTOR_REVERSE, DL, MVT::nxv2i1, Widened);
+  return DAG.getExtractSubvector(DL, MVT::nxv1i1, Reversed, 1);
+}
+
 SDValue AArch64TargetLowering::LowerSELECT_CC(SDValue Op,
                                               SelectionDAG &DAG) const {
   ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(4))->get();
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
index e1ac77334d2c7..027831aedb7eb 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h
@@ -767,6 +767,7 @@ class AArch64TargetLowering : public TargetLowering {
   SDValue LowerZERO_EXTEND_VECTOR_INREG(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVECTOR_REPEAT(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) const;
+  SDValue LowerVECTOR_REVERSE(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerDUPQLane(SDValue Op, SelectionDAG &DAG) const;
   SDValue LowerToPredicatedOp(SDValue Op, SelectionDAG &DAG,
diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
index 669a49330856d..e55778e7f15a5 100644
--- a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
+++ b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll
@@ -8,6 +8,26 @@ target triple = "aarch64-unknown-linux-gnu"
 ; VECTOR_REVERSE - PPR
 ;
 
+define <vscale x 1 x i1> @reverse_nxv1i1(<vscale x 1 x i1> %a) #0 {
+; CHECK-SELDAG-LABEL: reverse_nxv1i1:
+; CHECK-SELDAG:       // %bb.0:
+; CHECK-SELDAG-NEXT:    uzp1 p0.d, p0.d, p0.d
+; CHECK-SELDAG-NEXT:    rev p0.d, p0.d
+; CHECK-SELDAG-NEXT:    punpkhi p0.h, p0.b
+; CHECK-SELDAG-NEXT:    ret
+;
+; CHECK-FASTISEL-LABEL: reverse_nxv1i1:
+; CHECK-FASTISEL:       // %bb.0:
+; CHECK-FASTISEL-NEXT:    // implicit-def: $p1
+; CHECK-FASTISEL-NEXT:    uzp1 p0.d, p0.d, p1.d
+; CHECK-FASTISEL-NEXT:    rev p0.d, p0.d
+; CHECK-FASTISEL-NEXT:    punpkhi p0.h, p0.b
+; CHECK-FASTISEL-NEXT:    ret
+
+  %res = call <vscale x 1 x i1> @llvm.vector.reverse.nxv1i1(<vscale x 1 x i1> %a)
+  ret <vscale x 1 x i1> %res
+}
+
 define <vscale x 2 x i1> @reverse_nxv2i1(<vscale x 2 x i1> %a) #0 {
 ; CHECK-LABEL: reverse_nxv2i1:
 ; CHECK:       // %bb.0: