[llvm] 7cb518a - TargetMachine: Remove pointer-size query methods (#226404)
via llvm-commits
llvm-commits at lists.llvm.org
Mon Sep 28 00:12:35 PDT 2026
Author: Matt Arsenault
Date: 2026-09-28T09:12:28+02:00
New Revision: 7cb518a5a1acf0c2c1df7b5ed207518c45046916
URL: https://github.com/llvm/llvm-project/commit/7cb518a5a1acf0c2c1df7b5ed207518c45046916
DIFF: https://github.com/llvm/llvm-project/commit/7cb518a5a1acf0c2c1df7b5ed207518c45046916.diff
LOG: TargetMachine: Remove pointer-size query methods (#226404)
Remove the shim methods from the TargetMachine's copy of the DataLayout,
which will soon be eliminated. The Module owns the authoritative DataLayout,
so callers should read the value from the contextual Module.
Completely unreasonably, Mips's ABI name can change the pointer size which
we probably should just not support. Many other triple checks will never be
correct. This avoids potential mismatches in these contexts, but I still expect
this to be widely broken.
Some of the TargetLowering constructor changes and AMDGPULegalizerInfo
changes are kind of annoying. We could pass in the DataLayout through the
subtarget constructors but it didn't seem worth the effort and the information
should be derivable from the triple anyway.
Co-authored-by: Claude (Claude-Opus-4.8) <noreply at anthropic.com>
Added:
Modified:
llvm/include/llvm/CodeGen/AsmPrinter.h
llvm/include/llvm/CodeGen/BasicTTIImpl.h
llvm/include/llvm/CodeGen/TargetLowering.h
llvm/include/llvm/Target/TargetMachine.h
llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
llvm/lib/CodeGen/CodeGenPrepare.cpp
llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/CodeGen/TargetLoweringBase.cpp
llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
llvm/lib/Target/AArch64/AArch64TargetMachine.h
llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
llvm/lib/Target/AMDGPU/SIISelLowering.h
llvm/lib/Target/ARM/ARMInstructionSelector.cpp
llvm/lib/Target/ARM/ARMTargetMachine.h
llvm/lib/Target/AVR/AVRTargetMachine.h
llvm/lib/Target/Hexagon/HexagonTargetMachine.h
llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
llvm/lib/Target/Mips/MipsTargetMachine.h
llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
llvm/lib/Target/PowerPC/PPCTargetMachine.h
llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
llvm/lib/Target/RISCV/RISCVTargetMachine.h
llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
llvm/lib/Target/Sparc/SparcISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
llvm/lib/Target/SystemZ/SystemZXPLINKAsmPrinter.cpp
llvm/lib/Target/VE/VEISelLowering.cpp
llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
llvm/lib/Target/X86/X86ISelLowering.cpp
llvm/lib/Target/X86/X86TargetMachine.cpp
llvm/lib/Target/X86/X86TargetMachine.h
Removed:
################################################################################
diff --git a/llvm/include/llvm/CodeGen/AsmPrinter.h b/llvm/include/llvm/CodeGen/AsmPrinter.h
index f6c19280030a9..7c51b447c8b6f 100644
--- a/llvm/include/llvm/CodeGen/AsmPrinter.h
+++ b/llvm/include/llvm/CodeGen/AsmPrinter.h
@@ -111,6 +111,9 @@ class LLVM_ABI AsmPrinter : public MachineFunctionPass {
/// This is a pointer to the current MachineModuleInfo.
MachineModuleInfo *MMI = nullptr;
+ /// The pointer size in bytes for the default address space
+ unsigned PointerSize = 0;
+
/// This is a pointer to the current MachineDominatorTree.
MachineDominatorTree *MDT = nullptr;
@@ -352,8 +355,8 @@ class LLVM_ABI AsmPrinter : public MachineFunctionPass {
/// Return information about data layout.
const DataLayout &getDataLayout() const;
- /// Return the pointer size from the TargetMachine
- unsigned getPointerSize() const;
+ /// Return the pointer size in bytes from the target triple.
+ unsigned getPointerSize() const { return PointerSize; }
/// Return information about subtarget.
const MCSubtargetInfo &getSubtargetInfo() const;
diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
index 9fffe55325421..93bb8656d7517 100644
--- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h
+++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h
@@ -443,7 +443,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
}
bool isNoopAddrSpaceCast(unsigned FromAS, unsigned ToAS) const override {
- return getTLI()->getTargetMachine().isNoopAddrSpaceCast(FromAS, ToAS);
+ return getTLI()->getTargetMachine().isNoopAddrSpaceCast(DL, FromAS, ToAS);
}
unsigned getAssumedAddrSpace(const Value *V) const override {
@@ -1333,7 +1333,7 @@ class BasicTTIImplBase : public TargetTransformInfoImplCRTPBase<T> {
}
break;
case Instruction::AddrSpaceCast:
- if (TLI->isFreeAddrSpaceCast(Src->getPointerAddressSpace(),
+ if (TLI->isFreeAddrSpaceCast(DL, Src->getPointerAddressSpace(),
Dst->getPointerAddressSpace()))
return 0;
break;
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index 283b0f811dc2f..18255b429d995 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -2241,7 +2241,8 @@ class LLVM_ABI TargetLoweringBase {
/// Returns true if a cast from SrcAS to DestAS is "cheap", such that e.g. we
/// are happy to sink it into basic blocks. A cast may be free, but not
/// necessarily a no-op. e.g. a free truncate from a 64-bit to 32-bit pointer.
- virtual bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const;
+ virtual bool isFreeAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
+ unsigned DestAS) const;
/// Return true if the pointer arguments to CI should be aligned by aligning
/// the object whose address is being passed. If so then MinSize is set to the
diff --git a/llvm/include/llvm/Target/TargetMachine.h b/llvm/include/llvm/Target/TargetMachine.h
index 5b1dede9d7893..7c52c72cc400e 100644
--- a/llvm/include/llvm/Target/TargetMachine.h
+++ b/llvm/include/llvm/Target/TargetMachine.h
@@ -377,7 +377,8 @@ class LLVM_ABI TargetMachine {
}
/// Returns true if a cast between SrcAS and DestAS is a noop.
- virtual bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const {
+ virtual bool isNoopAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
+ unsigned DestAS) const {
return false;
}
diff --git a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
index 8c30f91ac0855..dab57e744db08 100644
--- a/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
+++ b/llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp
@@ -407,6 +407,7 @@ AsmPrinter::AsmPrinter(TargetMachine &tm, std::unique_ptr<MCStreamer> Streamer,
char &ID)
: MachineFunctionPass(ID), TM(tm), MAI(tm.getMCAsmInfo()),
OutContext(Streamer->getContext()), OutStreamer(std::move(Streamer)),
+ PointerSize(tm.getTargetTriple().getArchPointerBitWidth() / 8),
SM(*this) {
VerboseAsm = OutStreamer->isVerboseAsm();
DwarfUsesRelocationsAcrossSections =
@@ -487,12 +488,6 @@ const DataLayout &AsmPrinter::getDataLayout() const {
return MMI->getModule()->getDataLayout();
}
-// Do not use the cached DataLayout because some client use it without a Module
-// (dsymutil, llvm-dwarfdump).
-unsigned AsmPrinter::getPointerSize() const {
- return TM.getPointerSize(0); // FIXME: Default address space
-}
-
const MCSubtargetInfo &AsmPrinter::getSubtargetInfo() const {
assert(MF && "getSubtargetInfo requires a valid MachineFunction!");
return MF->getSubtarget<MCSubtargetInfo>();
@@ -524,6 +519,7 @@ void AsmPrinter::getAnalysisUsage(AnalysisUsage &AU) const {
bool AsmPrinter::doInitialization(Module &M) {
MMI = GetMMI();
+ PointerSize = M.getDataLayout().getPointerSize(0);
HasSplitStack = false;
HasNoSplitStack = false;
DbgInfoAvailable = !M.debug_compile_units().empty();
@@ -1731,7 +1727,9 @@ void AsmPrinter::emitStackSizeSection(const MachineFunction &MF) {
const MCSymbol *FunctionSymbol = getFunctionBegin();
uint64_t StackSize =
FrameInfo.getStackSize() + FrameInfo.getUnsafeStackSize();
- OutStreamer->emitSymbolValue(FunctionSymbol, TM.getProgramPointerSize());
+ const DataLayout &DL = getDataLayout();
+ OutStreamer->emitSymbolValue(FunctionSymbol,
+ DL.getPointerSize(DL.getProgramAddressSpace()));
OutStreamer->emitULEB128IntValue(StackSize);
OutStreamer->popSection();
@@ -1837,9 +1835,11 @@ void AsmPrinter::emitCallGraphSection(const MachineFunction &MF,
// 6) For each unique direct callee, the callee's PC.
// 7) Number of unique indirect target type IDs, if at least one exists.
// 8) Each unique indirect target type id.
+ const DataLayout &DL = getDataLayout();
+ unsigned ProgramPointerSize = DL.getPointerSize(DL.getProgramAddressSpace());
OutStreamer->emitInt8(CallGraphSectionFormatVersion::V_0);
OutStreamer->emitInt8(static_cast<uint8_t>(CGFlags));
- OutStreamer->emitSymbolValue(getSymbol(&F), TM.getProgramPointerSize());
+ OutStreamer->emitSymbolValue(getSymbol(&F), ProgramPointerSize);
const auto *TypeId = extractNumericCGTypeId(F);
if (IsIndirectTarget && TypeId)
OutStreamer->emitInt64(TypeId->getZExtValue());
@@ -1849,7 +1849,7 @@ void AsmPrinter::emitCallGraphSection(const MachineFunction &MF,
if (DirectCallees.size() > 0) {
OutStreamer->emitULEB128IntValue(DirectCallees.size());
for (const auto &CalleeSymbol : DirectCallees)
- OutStreamer->emitSymbolValue(CalleeSymbol, TM.getProgramPointerSize());
+ OutStreamer->emitSymbolValue(CalleeSymbol, ProgramPointerSize);
FuncCGInfo.DirectCallees.clear();
}
if (IndirectCalleeTypeIDs.size() > 0) {
@@ -3564,10 +3564,12 @@ void AsmPrinter::emitJumpTableSizesSection(const MachineJumpTableInfo &MJTI,
OutStreamer->switchSection(JumpTableSizesSection);
+ const DataLayout &DL = getDataLayout();
+ unsigned ProgramPointerSize = DL.getPointerSize(DL.getProgramAddressSpace());
for (unsigned JTI = 0, E = JT.size(); JTI != E; ++JTI) {
const std::vector<MachineBasicBlock *> &JTBBs = JT[JTI].MBBs;
- OutStreamer->emitSymbolValue(GetJTISymbol(JTI), TM.getProgramPointerSize());
- OutStreamer->emitIntValue(JTBBs.size(), TM.getProgramPointerSize());
+ OutStreamer->emitSymbolValue(GetJTISymbol(JTI), ProgramPointerSize);
+ OutStreamer->emitIntValue(JTBBs.size(), ProgramPointerSize);
}
}
@@ -3966,7 +3968,7 @@ const MCExpr *AsmPrinter::lowerConstant(const Constant *CV,
const Constant *Op = CE->getOperand(0);
unsigned DstAS = CE->getType()->getPointerAddressSpace();
unsigned SrcAS = Op->getType()->getPointerAddressSpace();
- if (TM.isNoopAddrSpaceCast(SrcAS, DstAS))
+ if (TM.isNoopAddrSpaceCast(getDataLayout(), SrcAS, DstAS))
return lowerConstant(Op);
break; // Error
diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp
index ff40f210c5790..d554a32a5d3ae 100644
--- a/llvm/lib/CodeGen/CodeGenPrepare.cpp
+++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp
@@ -1545,7 +1545,7 @@ static bool OptimizeNoopCopyExpression(CastInst *CI, const TargetLowering &TLI,
// Sink only "cheap" (or nop) address-space casts. This is a weaker condition
// than sinking only nop casts, but is helpful on some platforms.
if (auto *ASC = dyn_cast<AddrSpaceCastInst>(CI)) {
- if (!TLI.isFreeAddrSpaceCast(ASC->getSrcAddressSpace(),
+ if (!TLI.isFreeAddrSpaceCast(DL, ASC->getSrcAddressSpace(),
ASC->getDestAddressSpace()))
return false;
}
@@ -5245,7 +5245,7 @@ bool AddressingModeMatcher::matchOperationAddr(User *AddrInst, unsigned Opcode,
unsigned SrcAS =
AddrInst->getOperand(0)->getType()->getPointerAddressSpace();
unsigned DestAS = AddrInst->getType()->getPointerAddressSpace();
- if (TLI.getTargetMachine().isNoopAddrSpaceCast(SrcAS, DestAS))
+ if (TLI.getTargetMachine().isNoopAddrSpaceCast(DL, SrcAS, DestAS))
return matchAddr(AddrInst->getOperand(0), Depth);
return false;
}
diff --git a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
index 1b760a70608dd..3cc232c40e791 100644
--- a/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
+++ b/llvm/lib/CodeGen/LiveDebugValues/InstrRefBasedImpl.cpp
@@ -1320,7 +1320,7 @@ MLocTracker::emitLoc(const SmallVectorImpl<ResolvedDbgOp> &DbgOps,
// manifests as too-little or too-much memory being read from the stack.
// However we can't solve that without putting more type information in
// debug-info.
- if (ValueSizeInBits > MF.getTarget().getPointerSizeInBits(0))
+ if (ValueSizeInBits > MF.getDataLayout().getPointerSizeInBits(0))
UseDerefSize = false;
SmallVector<uint64_t, 5> OffsetOps;
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 541c378a2eda1..f0b1613e73f7b 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -10005,10 +10005,10 @@ static SDValue getMemsetStores(SelectionDAG &DAG, const SDLoc &dl,
}
static void checkAddrSpaceIsValidForLibcall(const TargetLowering *TLI,
- unsigned AS) {
+ const DataLayout &DL, unsigned AS) {
// Lowering memcpy / memset / memmove intrinsics to calls is only valid if all
// pointer operands can be losslessly bitcasted to pointers of address space 0
- if (AS != 0 && !TLI->getTargetMachine().isNoopAddrSpaceCast(AS, 0)) {
+ if (AS != 0 && !TLI->getTargetMachine().isNoopAddrSpaceCast(DL, AS, 0)) {
report_fatal_error("cannot lower memory intrinsic in address space " +
Twine(AS));
}
@@ -10176,8 +10176,10 @@ SDValue SelectionDAG::getMemcpy(
DstMemCacheHint, SrcMemCacheHint);
}
- checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace());
- checkAddrSpaceIsValidForLibcall(TLI, SrcPtrInfo.getAddrSpace());
+ checkAddrSpaceIsValidForLibcall(TLI, getDataLayout(),
+ DstPtrInfo.getAddrSpace());
+ checkAddrSpaceIsValidForLibcall(TLI, getDataLayout(),
+ SrcPtrInfo.getAddrSpace());
// FIXME: If the memcpy is volatile (isVol), lowering it to a plain libc
// memcpy is not guaranteed to be safe. libc memcpys aren't required to
@@ -10291,8 +10293,10 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, const SDLoc &dl, SDValue Dst,
return Result;
}
- checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace());
- checkAddrSpaceIsValidForLibcall(TLI, SrcPtrInfo.getAddrSpace());
+ checkAddrSpaceIsValidForLibcall(TLI, getDataLayout(),
+ DstPtrInfo.getAddrSpace());
+ checkAddrSpaceIsValidForLibcall(TLI, getDataLayout(),
+ SrcPtrInfo.getAddrSpace());
// FIXME: If the memmove is volatile, lowering it to plain libc memmove may
// not be safe. See memcpy above for more details.
@@ -10414,7 +10418,8 @@ SDValue SelectionDAG::getMemset(SDValue Chain, const SDLoc &dl, SDValue Dst,
return Result;
}
- checkAddrSpaceIsValidForLibcall(TLI, DstPtrInfo.getAddrSpace());
+ checkAddrSpaceIsValidForLibcall(TLI, getDataLayout(),
+ DstPtrInfo.getAddrSpace());
// Emit a library call.
auto &Ctx = *getContext();
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
index b47f2c541e042..f7eec8c5088d4 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -4177,7 +4177,7 @@ void SelectionDAGBuilder::visitAddrSpaceCast(const User &I) {
unsigned SrcAS = SV->getType()->getPointerAddressSpace();
unsigned DestAS = I.getType()->getPointerAddressSpace();
- if (!TM.isNoopAddrSpaceCast(SrcAS, DestAS)) {
+ if (!TM.isNoopAddrSpaceCast(DAG.getDataLayout(), SrcAS, DestAS)) {
SDNodeFlags Flags;
if (const auto *ASC = dyn_cast<AddrSpaceCastInst>(&I))
Flags.setNonNull(ASC->hasNonNull());
diff --git a/llvm/lib/CodeGen/TargetLoweringBase.cpp b/llvm/lib/CodeGen/TargetLoweringBase.cpp
index 6f758bcffa81d..90a27a4a57cf2 100644
--- a/llvm/lib/CodeGen/TargetLoweringBase.cpp
+++ b/llvm/lib/CodeGen/TargetLoweringBase.cpp
@@ -1067,9 +1067,10 @@ bool TargetLoweringBase::canOpTrap(unsigned Op, EVT VT) const {
}
}
-bool TargetLoweringBase::isFreeAddrSpaceCast(unsigned SrcAS,
+bool TargetLoweringBase::isFreeAddrSpaceCast(const DataLayout &DL,
+ unsigned SrcAS,
unsigned DestAS) const {
- return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
+ return TM.isNoopAddrSpaceCast(DL, SrcAS, DestAS);
}
unsigned TargetLoweringBase::getBitWidthForCttzElements(
diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
index c98d607c4a22c..e159aea0868d5 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp
@@ -7822,8 +7822,8 @@ static SDValue LowerADDRSPACECAST(SDValue Op, SelectionDAG &DAG) {
unsigned DestAS = N->getDestAddressSpace();
assert(SrcAS != DestAS &&
"addrspacecast must be between
diff erent address spaces");
- assert(TLI.getTargetMachine().getPointerSize(SrcAS) !=
- TLI.getTargetMachine().getPointerSize(DestAS) &&
+ assert(DAG.getDataLayout().getPointerSize(SrcAS) !=
+ DAG.getDataLayout().getPointerSize(DestAS) &&
"addrspacecast must be between
diff erent ptr sizes");
(void)TLI;
diff --git a/llvm/lib/Target/AArch64/AArch64TargetMachine.h b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
index 28b9a0144abfe..42fa55639d5d7 100644
--- a/llvm/lib/Target/AArch64/AArch64TargetMachine.h
+++ b/llvm/lib/Target/AArch64/AArch64TargetMachine.h
@@ -70,8 +70,9 @@ class AArch64TargetMachine : public CodeGenTargetMachineImpl {
SMRange &SourceRange) const override;
/// Returns true if a cast between SrcAS and DestAS is a noop.
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
- return getPointerSize(SrcAS) == getPointerSize(DestAS);
+ bool isNoopAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
+ unsigned DestAS) const override {
+ return DL.getPointerSize(SrcAS) == DL.getPointerSize(DestAS);
}
ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext *C) const override;
diff --git a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
index c922d14576af8..e759f6eb64860 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp
@@ -696,21 +696,17 @@ AMDGPULegalizerInfo::AMDGPULegalizerInfo(const GCNSubtarget &ST_,
: ST(ST_) {
using namespace TargetOpcode;
- auto GetAddrSpacePtr = [&TM](unsigned AS) {
- return LLT::pointer(AS, TM.getPointerSizeInBits(AS));
- };
-
- const LLT GlobalPtr = GetAddrSpacePtr(AMDGPUAS::GLOBAL_ADDRESS);
- const LLT ConstantPtr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS);
- const LLT Constant32Ptr = GetAddrSpacePtr(AMDGPUAS::CONSTANT_ADDRESS_32BIT);
- const LLT LocalPtr = GetAddrSpacePtr(AMDGPUAS::LOCAL_ADDRESS);
- const LLT RegionPtr = GetAddrSpacePtr(AMDGPUAS::REGION_ADDRESS);
- const LLT FlatPtr = GetAddrSpacePtr(AMDGPUAS::FLAT_ADDRESS);
- const LLT PrivatePtr = GetAddrSpacePtr(AMDGPUAS::PRIVATE_ADDRESS);
- const LLT BufferFatPtr = GetAddrSpacePtr(AMDGPUAS::BUFFER_FAT_POINTER);
- const LLT RsrcPtr = GetAddrSpacePtr(AMDGPUAS::BUFFER_RESOURCE);
+ const LLT GlobalPtr = LLT::pointer(AMDGPUAS::GLOBAL_ADDRESS, 64);
+ const LLT ConstantPtr = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS, 64);
+ const LLT Constant32Ptr = LLT::pointer(AMDGPUAS::CONSTANT_ADDRESS_32BIT, 32);
+ const LLT LocalPtr = LLT::pointer(AMDGPUAS::LOCAL_ADDRESS, 32);
+ const LLT RegionPtr = LLT::pointer(AMDGPUAS::REGION_ADDRESS, 32);
+ const LLT FlatPtr = LLT::pointer(AMDGPUAS::FLAT_ADDRESS, 64);
+ const LLT PrivatePtr = LLT::pointer(AMDGPUAS::PRIVATE_ADDRESS, 32);
+ const LLT BufferFatPtr = LLT::pointer(AMDGPUAS::BUFFER_FAT_POINTER, 160);
+ const LLT RsrcPtr = LLT::pointer(AMDGPUAS::BUFFER_RESOURCE, 128);
const LLT BufferStridedPtr =
- GetAddrSpacePtr(AMDGPUAS::BUFFER_STRIDED_POINTER);
+ LLT::pointer(AMDGPUAS::BUFFER_STRIDED_POINTER, 192);
const LLT CodePtr = FlatPtr;
@@ -2590,7 +2586,7 @@ bool AMDGPULegalizerInfo::legalizeAddrSpaceCast(
// flag; otherwise we need to guess.
const bool IsNonNull = MI.getFlag(MachineInstr::MIFlag::NonNull);
- if (TM.isNoopAddrSpaceCast(SrcAS, DestAS)) {
+ if (TM.isNoopAddrSpaceCast(MF.getDataLayout(), SrcAS, DestAS)) {
MI.setDesc(B.getTII().get(TargetOpcode::G_BITCAST));
return true;
}
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
index b47a000a1c980..72c028edbaef5 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp
@@ -1199,7 +1199,8 @@ void AMDGPUTargetMachine::registerPassBuilderCallbacks(PassBuilder &PB) {
});
}
-bool AMDGPUTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
+bool AMDGPUTargetMachine::isNoopAddrSpaceCast(const DataLayout &DL,
+ unsigned SrcAS,
unsigned DestAS) const {
return AMDGPU::isFlatGlobalAddrSpace(SrcAS) &&
AMDGPU::isFlatGlobalAddrSpace(DestAS);
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
index 35ca216eee079..878eb7ddb0afd 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
+++ b/llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.h
@@ -59,7 +59,8 @@ class AMDGPUTargetMachine : public CodeGenTargetMachineImpl {
void registerPassBuilderCallbacks(PassBuilder &PB) override;
void registerDefaultAliasAnalyses(AAManager &) override;
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
+ bool isNoopAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
+ unsigned DestAS) const override;
unsigned getAssumedAddrSpace(const Value *V) const override;
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
index 25fcaa0ac8c4b..382427a2c4011 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -2433,7 +2433,7 @@ bool SITargetLowering::isNonGlobalAddrSpace(unsigned AS) {
AS == AMDGPUAS::PRIVATE_ADDRESS;
}
-bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
+bool SITargetLowering::isFreeAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
unsigned DestAS) const {
if (SrcAS == AMDGPUAS::FLAT_ADDRESS) {
if (DestAS == AMDGPUAS::PRIVATE_ADDRESS &&
@@ -2449,7 +2449,7 @@ bool SITargetLowering::isFreeAddrSpaceCast(unsigned SrcAS,
const GCNTargetMachine &TM =
static_cast<const GCNTargetMachine &>(getTargetMachine());
- return TM.isNoopAddrSpaceCast(SrcAS, DestAS);
+ return TM.isNoopAddrSpaceCast(DL, SrcAS, DestAS);
}
TargetLoweringBase::LegalizeTypeAction
@@ -3665,7 +3665,8 @@ SDValue SITargetLowering::LowerFormalArguments(
const GCNTargetMachine &TM =
static_cast<const GCNTargetMachine &>(getTargetMachine());
- if (!TM.isNoopAddrSpaceCast(AMDGPUAS::CONSTANT_ADDRESS,
+ if (!TM.isNoopAddrSpaceCast(DAG.getDataLayout(),
+ AMDGPUAS::CONSTANT_ADDRESS,
Arg.Flags.getPointerAddrSpace())) {
Ptr = DAG.getAddrSpaceCast(DL, VT, Ptr, AMDGPUAS::CONSTANT_ADDRESS,
Arg.Flags.getPointerAddrSpace());
diff --git a/llvm/lib/Target/AMDGPU/SIISelLowering.h b/llvm/lib/Target/AMDGPU/SIISelLowering.h
index fc52aa4eeb5a4..2ce36586402b6 100644
--- a/llvm/lib/Target/AMDGPU/SIISelLowering.h
+++ b/llvm/lib/Target/AMDGPU/SIISelLowering.h
@@ -403,7 +403,8 @@ class SITargetLowering final : public AMDGPUTargetLowering {
static bool isNonGlobalAddrSpace(unsigned AS);
- bool isFreeAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
+ bool isFreeAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
+ unsigned DestAS) const override;
TargetLoweringBase::LegalizeTypeAction
getPreferredVectorAction(MVT VT) const override;
diff --git a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
index c2ee75205d888..ec5d34407e71b 100644
--- a/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
+++ b/llvm/lib/Target/ARM/ARMInstructionSelector.cpp
@@ -649,10 +649,11 @@ bool ARMInstructionSelector::selectGlobal(MachineInstrBuilder &MIB,
MIB.add(predOps(ARMCC::AL));
};
- auto addGOTMemOperand = [this, &MF, Alignment](MachineInstrBuilder &MIB) {
+ auto addGOTMemOperand = [&MF, Alignment](MachineInstrBuilder &MIB) {
+ const DataLayout &DL = MF.getDataLayout();
MIB.addMemOperand(MF.getMachineMemOperand(
MachinePointerInfo::getGOT(MF), MachineMemOperand::MOLoad,
- TM.getProgramPointerSize(), Alignment));
+ DL.getPointerSize(DL.getProgramAddressSpace()), Alignment));
};
if (TM.isPositionIndependent()) {
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 51960634bf993..3a9be67159702 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -77,7 +77,8 @@ class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
const TargetSubtargetInfo *STI) const override;
/// Returns true if a cast between SrcAS and DestAS is a noop.
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+ bool isNoopAddrSpaceCast(const DataLayout &, unsigned SrcAS,
+ unsigned DestAS) const override {
// Addrspacecasts are always noops.
return true;
}
diff --git a/llvm/lib/Target/AVR/AVRTargetMachine.h b/llvm/lib/Target/AVR/AVRTargetMachine.h
index 9452b3d8cd8a5..6837b9cfdd74c 100644
--- a/llvm/lib/Target/AVR/AVRTargetMachine.h
+++ b/llvm/lib/Target/AVR/AVRTargetMachine.h
@@ -50,13 +50,14 @@ class AVRTargetMachine : public CodeGenTargetMachineImpl {
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
- bool isNoopAddrSpaceCast(unsigned SrcAs, unsigned DestAs) const override {
+ bool isNoopAddrSpaceCast(const DataLayout &DL, unsigned SrcAs,
+ unsigned DestAs) const override {
// While AVR has
diff erent address spaces, they are all represented by
// 16-bit pointers that can be freely casted between (of course, a pointer
// must be cast back to its original address space to be dereferenceable).
// To be safe, also check the pointer size in case we implement __memx
// pointers.
- return getPointerSize(SrcAs) == getPointerSize(DestAs);
+ return DL.getPointerSize(SrcAs) == DL.getPointerSize(DestAs);
}
private:
diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
index 5d4a461e4db92..ebb2446fdaa9f 100644
--- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
+++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.h
@@ -58,7 +58,8 @@ class HexagonTargetMachine : public CodeGenTargetMachineImpl {
SMDiagnostic &Error,
SMRange &SourceRange) const override;
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+ bool isNoopAddrSpaceCast(const DataLayout &, unsigned SrcAS,
+ unsigned DestAS) const override {
return true;
}
ScheduleDAGInstrs *
diff --git a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
index acd3a4a9555b3..5bcfa67fdfa9c 100644
--- a/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
+++ b/llvm/lib/Target/LoongArch/LoongArchTargetMachine.h
@@ -47,7 +47,8 @@ class LoongArchTargetMachine : public CodeGenTargetMachineImpl {
const TargetSubtargetInfo *STI) const override;
// Addrspacecasts are always noops.
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+ bool isNoopAddrSpaceCast(const DataLayout &, unsigned SrcAS,
+ unsigned DestAS) const override {
return true;
}
};
diff --git a/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp b/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
index 13feb873166fe..716a0a6c1c1fa 100644
--- a/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
+++ b/llvm/lib/Target/MSP430/MSP430AsmPrinter.cpp
@@ -175,7 +175,9 @@ void MSP430AsmPrinter::EmitInterruptVectorSection(MachineFunction &ISR) {
OutStreamer->switchSection(IV);
const MCSymbol *FunctionSymbol = getSymbol(F);
- OutStreamer->emitSymbolValue(FunctionSymbol, TM.getProgramPointerSize());
+ const DataLayout &DL = getDataLayout();
+ OutStreamer->emitSymbolValue(FunctionSymbol,
+ DL.getPointerSize(DL.getProgramAddressSpace()));
OutStreamer->switchSection(Cur);
}
diff --git a/llvm/lib/Target/Mips/MipsTargetMachine.h b/llvm/lib/Target/Mips/MipsTargetMachine.h
index 4923ad62f33ac..5f4ca639408d9 100644
--- a/llvm/lib/Target/Mips/MipsTargetMachine.h
+++ b/llvm/lib/Target/Mips/MipsTargetMachine.h
@@ -56,7 +56,8 @@ class MipsTargetMachine : public CodeGenTargetMachineImpl {
const TargetSubtargetInfo *STI) const override;
/// Returns true if a cast between SrcAS and DestAS is a noop.
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+ bool isNoopAddrSpaceCast(const DataLayout &, unsigned SrcAS,
+ unsigned DestAS) const override {
// Mips doesn't have any special address spaces so we just reserve
// the first 256 for software use (e.g. OpenCL) and treat casts
// between them as noops.
diff --git a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
index a7d7b55c81fff..55344ce5e1eb1 100644
--- a/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
+++ b/llvm/lib/Target/NVPTX/NVPTXAsmPrinter.cpp
@@ -1815,7 +1815,8 @@ NVPTXAsmPrinter::getPTXFundamentalTypeStr(Type *Ty, bool useB4PTR) const {
case Type::DoubleTyID:
return "f64";
case Type::PointerTyID: {
- unsigned PtrSize = TM.getPointerSizeInBits(Ty->getPointerAddressSpace());
+ unsigned PtrSize =
+ getDataLayout().getPointerSizeInBits(Ty->getPointerAddressSpace());
assert((PtrSize == 64 || PtrSize == 32) && "Unexpected pointer size");
if (PtrSize == 64)
diff --git a/llvm/lib/Target/PowerPC/PPCTargetMachine.h b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
index 660f47b355648..07fa52ba50ad5 100644
--- a/llvm/lib/Target/PowerPC/PPCTargetMachine.h
+++ b/llvm/lib/Target/PowerPC/PPCTargetMachine.h
@@ -77,7 +77,8 @@ class PPCTargetMachine final : public CodeGenTargetMachineImpl {
return (TT.getArch() == Triple::ppc64 || TT.getArch() == Triple::ppc64le);
};
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override {
+ bool isNoopAddrSpaceCast(const DataLayout &, unsigned SrcAS,
+ unsigned DestAS) const override {
// Addrspacecasts are always noops.
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
index df2626026c85e..685bb91583cf5 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp
@@ -272,7 +272,8 @@ RISCVTargetMachine::getTargetTransformInfo(const Function &F) const {
// for all memory accesses, so it is reasonable to assume that an
// implementation has no-op address space casts. If an implementation makes a
// change to this, they can override it here.
-bool RISCVTargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
+bool RISCVTargetMachine::isNoopAddrSpaceCast(const DataLayout &DL,
+ unsigned SrcAS,
unsigned DstAS) const {
return true;
}
diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.h b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
index fdc76454b08d9..69a27a81aa6bf 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetMachine.h
+++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.h
@@ -49,7 +49,8 @@ class RISCVTargetMachine : public CodeGenTargetMachineImpl {
TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DstAS) const override;
+ bool isNoopAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
+ unsigned DstAS) const override;
yaml::MachineFunctionInfo *createDefaultFuncInfoYAML() const override;
yaml::MachineFunctionInfo *
diff --git a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
index a377c260a5fa1..74cd939d592c9 100644
--- a/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
+++ b/llvm/lib/Target/SPIRV/SPIRVSubtarget.cpp
@@ -54,7 +54,7 @@ SPIRVSubtarget::SPIRVSubtarget(const Triple &TT, const std::string &CPU,
const std::string &FS,
const SPIRVTargetMachine &TM)
: SPIRVGenSubtargetInfo(TT, CPU, /*TuneCPU=*/CPU, FS),
- PointerSize(TM.getPointerSizeInBits(/* AS= */ 0)),
+ PointerSize(TT.getArch() == Triple::spirv32 ? 32 : 64),
InstrInfo(initSubtargetDependencies(CPU, FS)), FrameLowering(*this),
TLInfo(TM, *this), TargetTriple(TT) {
switch (TT.getSubArch()) {
diff --git a/llvm/lib/Target/Sparc/SparcISelLowering.cpp b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
index 66638f599559a..3156d3695c1ca 100644
--- a/llvm/lib/Target/Sparc/SparcISelLowering.cpp
+++ b/llvm/lib/Target/Sparc/SparcISelLowering.cpp
@@ -1642,7 +1642,7 @@ static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
SparcTargetLowering::SparcTargetLowering(const TargetMachine &TM,
const SparcSubtarget &STI)
: TargetLowering(TM, STI), Subtarget(&STI) {
- MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
+ MVT PtrVT = Subtarget->is64Bit() ? MVT::i64 : MVT::i32;
// Instructions which use registers as conditionals examine all the
// bits (as does the pseudo SELECT_CC expansion). I don't think it
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index 145db33a41c74..488d65566b655 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -64,8 +64,7 @@ SystemZFrameLowering::SystemZFrameLowering(StackDirection D, Align StackAl,
std::unique_ptr<SystemZFrameLowering>
SystemZFrameLowering::create(const SystemZSubtarget &STI) {
- unsigned PtrSz =
- STI.getTargetLowering()->getTargetMachine().getPointerSize(0);
+ unsigned PtrSz = 8;
if (STI.isTargetXPLINK64())
return std::make_unique<SystemZXPLINKFrameLowering>(PtrSz);
return std::make_unique<SystemZELFFrameLowering>(PtrSz);
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 039aff408b517..a6cc3e94b7e7d 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -93,7 +93,7 @@ static MachineOperand earlyUseOperand(MachineOperand Op) {
SystemZTargetLowering::SystemZTargetLowering(const TargetMachine &TM,
const SystemZSubtarget &STI)
: TargetLowering(TM, STI), Subtarget(STI) {
- MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
+ MVT PtrVT = MVT::i64;
auto *Regs = STI.getSpecialRegisters();
@@ -4556,7 +4556,7 @@ SDValue SystemZTargetLowering::lowerVACOPY(SDValue Op,
SDLoc DL(Op);
uint32_t Sz =
- Subtarget.isTargetXPLINK64() ? getTargetMachine().getPointerSize(0) : 32;
+ Subtarget.isTargetXPLINK64() ? DAG.getDataLayout().getPointerSize(0) : 32;
return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr, DAG.getIntPtrConstant(Sz, DL),
Align(8), Align(8), /*isVolatile*/ false,
/*AlwaysInline*/ false,
diff --git a/llvm/lib/Target/SystemZ/SystemZXPLINKAsmPrinter.cpp b/llvm/lib/Target/SystemZ/SystemZXPLINKAsmPrinter.cpp
index 3ab3dfc4a0bcb..47703b152c8da 100644
--- a/llvm/lib/Target/SystemZ/SystemZXPLINKAsmPrinter.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZXPLINKAsmPrinter.cpp
@@ -36,8 +36,7 @@ using namespace llvm;
SystemZXPLINKAsmPrinter::SystemZXPLINKAsmPrinter(
TargetMachine &TM, std::unique_ptr<MCStreamer> Streamer)
- : SystemZAsmPrinter(TM, std::move(Streamer)),
- ADATable(TM.getPointerSize(0)) {}
+ : SystemZAsmPrinter(TM, std::move(Streamer)), ADATable(8) {}
bool SystemZXPLINKAsmPrinter::doInitialization(Module &M) {
SM.reset();
diff --git a/llvm/lib/Target/VE/VEISelLowering.cpp b/llvm/lib/Target/VE/VEISelLowering.cpp
index 1f9173dc481cf..0d60fb036b28c 100644
--- a/llvm/lib/Target/VE/VEISelLowering.cpp
+++ b/llvm/lib/Target/VE/VEISelLowering.cpp
@@ -99,7 +99,6 @@ void VETargetLowering::initRegisterClasses() {
}
void VETargetLowering::initSPUActions() {
- const auto &TM = getTargetMachine();
/// Load & Store {
// VE doesn't have i1 sign extending load.
@@ -125,7 +124,7 @@ void VETargetLowering::initSPUActions() {
/// } Load & Store
// Custom legalize address nodes into LO/HI parts.
- MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
+ MVT PtrVT = MVT::i64;
setOperationAction(ISD::BlockAddress, PtrVT, Custom);
setOperationAction(ISD::GlobalAddress, PtrVT, Custom);
setOperationAction(ISD::GlobalTLSAddress, PtrVT, Custom);
diff --git a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
index 78ab184af6c19..b78a3f46d6817 100644
--- a/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
+++ b/llvm/lib/Target/X86/GISel/X86LegalizerInfo.cpp
@@ -51,7 +51,7 @@ X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI,
bool HasLZCNT = Subtarget.hasLZCNT();
bool HasBMI = Subtarget.hasBMI();
- const LLT p0 = LLT::pointer(0, TM.getPointerSizeInBits(0));
+ const LLT p0 = LLT::pointer(0, Subtarget.isTarget64BitLP64() ? 64 : 32);
const LLT s1 = LLT::scalar(1);
const LLT s8 = LLT::scalar(8);
const LLT s16 = LLT::scalar(16);
diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp
index e2f3b5f3cd3d5..3464d87baa873 100644
--- a/llvm/lib/Target/X86/X86ISelLowering.cpp
+++ b/llvm/lib/Target/X86/X86ISelLowering.cpp
@@ -132,7 +132,7 @@ X86TargetLowering::X86TargetLowering(const X86TargetMachine &TM,
const X86Subtarget &STI)
: TargetLowering(TM, STI), Subtarget(STI) {
bool UseX87 = !Subtarget.useSoftFloat() && Subtarget.hasX87();
- MVT PtrVT = MVT::getIntegerVT(TM.getPointerSizeInBits(0));
+ MVT PtrVT = Subtarget.isTarget64BitLP64() ? MVT::i64 : MVT::i32;
// Set up the TargetLowering object.
diff --git a/llvm/lib/Target/X86/X86TargetMachine.cpp b/llvm/lib/Target/X86/X86TargetMachine.cpp
index 3fbbc6d9f6b31..72dab51b67ece 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.cpp
+++ b/llvm/lib/Target/X86/X86TargetMachine.cpp
@@ -317,10 +317,10 @@ bool X86TargetMachine::parseMachineFunctionInfo(
return false;
}
-bool X86TargetMachine::isNoopAddrSpaceCast(unsigned SrcAS,
+bool X86TargetMachine::isNoopAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
unsigned DestAS) const {
assert(SrcAS != DestAS && "Expected
diff erent address spaces!");
- if (getPointerSize(SrcAS) != getPointerSize(DestAS))
+ if (DL.getPointerSize(SrcAS) != DL.getPointerSize(DestAS))
return false;
return SrcAS < 256 && DestAS < 256;
}
diff --git a/llvm/lib/Target/X86/X86TargetMachine.h b/llvm/lib/Target/X86/X86TargetMachine.h
index 056d82f3742fe..361541d4482a1 100644
--- a/llvm/lib/Target/X86/X86TargetMachine.h
+++ b/llvm/lib/Target/X86/X86TargetMachine.h
@@ -79,7 +79,8 @@ class X86TargetMachine final : public CodeGenTargetMachineImpl {
bool isJIT() const { return IsJIT; }
- bool isNoopAddrSpaceCast(unsigned SrcAS, unsigned DestAS) const override;
+ bool isNoopAddrSpaceCast(const DataLayout &DL, unsigned SrcAS,
+ unsigned DestAS) const override;
ScheduleDAGInstrs *
createMachineScheduler(MachineSchedContext *C) const override;
ScheduleDAGInstrs *
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