[llvm] 70f22b8 - CodeGen: Fix SplitCriticalEdge using wrong VNInfo for subranges (#226214)

[via llvm-commits]

Author: Matt Arsenault
Date: 2026-09-28T08:52:33+02:00
New Revision: 70f22b8e024924ff69674da78a61da4c200b0e3c

URL: https://github.com/llvm/llvm-project/commit/70f22b8e024924ff69674da78a61da4c200b0e3c
DIFF: https://github.com/llvm/llvm-project/commit/70f22b8e024924ff69674da78a61da4c200b0e3c.diff

LOG: CodeGen: Fix SplitCriticalEdge using wrong VNInfo for subranges (#226214)

This fixes verifier errors when LiveIntervals is run before phi
elimination.

When extending a live interval across a newly split critical edge for a
PHI source operand, the subrange segments were added using the VNInfo of
the main range instead of the subrange's own value. Look up the
subrange's value at the predecessor's last index, as the other subrange
loop in the same function already does, and skip subranges with no value
there.

Co-authored-by: Claude Opus 5 <noreply at anthropic.com>

Added: 
    llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir

Modified: 
    llvm/lib/CodeGen/MachineBasicBlock.cpp

Removed: 
    


################################################################################
diff  --git a/llvm/lib/CodeGen/MachineBasicBlock.cpp b/llvm/lib/CodeGen/MachineBasicBlock.cpp
index 39c286f7d3510..fa708fee5f769 100644
--- a/llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ b/llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1352,8 +1352,10 @@ MachineBasicBlock *MachineBasicBlock::SplitCriticalEdge(
           assert(VNI &&
                  "PHI sources should be live out of their predecessors.");
           LI.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
-          for (auto &SR : LI.subranges())
-            SR.addSegment(LiveInterval::Segment(StartIndex, EndIndex, VNI));
+          for (auto &SR : LI.subranges()) {
+            if (VNInfo *SRVNI = SR.getVNInfoAt(PrevIndex))
+              SR.addSegment(LiveInterval::Segment(StartIndex, EndIndex, SRVNI));
+          }
         }
       }
     }

diff  --git a/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir b/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
new file mode 100644
index 0000000000000..385153eb1b88d
--- /dev/null
+++ b/llvm/test/CodeGen/AMDGPU/phi-elimination-split-critical-edge-subranges.mir
@@ -0,0 +1,68 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
+# RUN: llc -mtriple=amdgpu9.00 -passes='require<live-intervals>,phi-node-elimination' -o - %s | FileCheck %s
+
+# Splitting the critical edge from %bb.1 to %bb.2 must extend the
+# subranges of the PHI source using the value numbers of the
+# subranges, not the value number of the main range.
+
+---
+name:            split_critical_edge_subranges
+tracksRegLiveness: true
+body:             |
+  ; CHECK-LABEL: name: split_critical_edge_subranges
+  ; CHECK: bb.0:
+  ; CHECK-NEXT:   successors: %bb.1(0x40000000), %bb.4(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[V_MOV_B32_e32_:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+  ; CHECK-NEXT:   [[V_MOV_B32_e32_1:%[0-9]+]]:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+  ; CHECK-NEXT:   [[REG_SEQUENCE:%[0-9]+]]:vreg_64 = REG_SEQUENCE [[V_MOV_B32_e32_]], %subreg.sub0, [[V_MOV_B32_e32_1]], %subreg.sub1
+  ; CHECK-NEXT:   $scc = IMPLICIT_DEF
+  ; CHECK-NEXT:   S_CBRANCH_SCC0 %bb.1, implicit $scc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.4:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
+  ; CHECK-NEXT:   S_BRANCH %bb.2
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.1:
+  ; CHECK-NEXT:   successors: %bb.5(0x40000000), %bb.3(0x40000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   $scc = IMPLICIT_DEF
+  ; CHECK-NEXT:   S_CBRANCH_SCC1 %bb.3, implicit $scc
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.5:
+  ; CHECK-NEXT:   successors: %bb.2(0x80000000)
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT:   [[COPY:%[0-9]+]]:vreg_64 = COPY [[REG_SEQUENCE]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.2:
+  ; CHECK-NEXT:   [[COPY1:%[0-9]+]]:vreg_64 = COPY [[COPY]]
+  ; CHECK-NEXT:   S_ENDPGM 0, implicit [[COPY1]]
+  ; CHECK-NEXT: {{  $}}
+  ; CHECK-NEXT: bb.3:
+  ; CHECK-NEXT:   S_ENDPGM 0, implicit [[REG_SEQUENCE]].sub0
+  bb.0:
+    successors: %bb.1, %bb.2
+
+    %0:vgpr_32 = V_MOV_B32_e32 0, implicit $exec
+    %1:vgpr_32 = V_MOV_B32_e32 1, implicit $exec
+    %2:vreg_64 = REG_SEQUENCE %0, %subreg.sub0, %1, %subreg.sub1
+    $scc = IMPLICIT_DEF
+    S_CBRANCH_SCC1 %bb.2, implicit $scc
+    S_BRANCH %bb.1
+
+  bb.1:
+    successors: %bb.2, %bb.3
+
+    $scc = IMPLICIT_DEF
+    S_CBRANCH_SCC1 %bb.3, implicit $scc
+    S_BRANCH %bb.2
+
+  bb.2:
+    %3:vreg_64 = PHI %2, %bb.0, %2, %bb.1
+    S_ENDPGM 0, implicit %3
+
+  bb.3:
+    S_ENDPGM 0, implicit %2.sub0
+...