[llvm] [DAG] NFC: Reword SCALAR_TO_VECTOR poison comment in SimplifyDemandedBits (PR #226003)
Cyrus Ding via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 27 18:29:50 PDT 2026
https://github.com/dingcyrus updated https://github.com/llvm/llvm-project/pull/226003
>From efd72ff219a87ad2f830101ca198e9077ca3b364 Mon Sep 17 00:00:00 2001
From: Cyrus Ding <785101675 at qq.com>
Date: Thu, 24 Sep 2026 10:58:11 +0800
Subject: [PATCH 1/3] [DAG] NFC: Reword SCALAR_TO_VECTOR poison comment in
SimplifyDemandedBits
The previous wording ("poison, not undef") could be read as a lattice
claim, which is incorrect under the poison-refines-undef reading; the
intent was operational: the upper elements must not be treated as undef
by undef-keyed folds. Reword to state the operational rule and the reason:
KnownUndef-driven folds substitute a chosen concrete value for undef bits
(e.g. zext(undef) -> 0 via DemandedElts.isSubsetOf(KnownUndef), and the
x86 shuffle AND(0, undef) -> 0 combine), which is invalid for poison since
consuming a poison lane yields poison.
Addresses review feedback on #217185.
No functional change.
---
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 7c97dfb2c806a1..1b48a9bbce0628 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3354,7 +3354,9 @@ bool TargetLowering::SimplifyDemandedVectorElts(
case ISD::SCALAR_TO_VECTOR: {
if (!DemandedElts[0])
return TLO.CombineTo(Op, TLO.DAG.getPOISON(VT));
- // Upper elements are poison, not undef - don't mark them as KnownUndef.
+ // Upper elements are poison; do not mark them as KnownUndef. Undef-driven
+ // folds that pick a concrete value for undef bits (e.g. zext(undef) -> 0,
+ // AND(0, undef) -> 0) are invalid for poison, which must propagate.
break;
}
case ISD::BITCAST: {
>From 6881cb674a65acc98b91d17e704a28cc62834c77 Mon Sep 17 00:00:00 2001
From: Cyrus Ding <785101675 at qq.com>
Date: Mon, 28 Sep 2026 09:28:56 +0800
Subject: [PATCH 2/3] [DAG] Document that SimplifyDemandedVectorElts KnownUndef
excludes poison (NFC)
Requested in review on #226003: the rule that KnownUndef only reports
known-undef elements - and never elements that are (only) known to be
poison - is general to SimplifyDemandedVectorElts and
SimplifyDemandedVectorEltsForTargetNode, so document it on both
declarations in TargetLowering.h: undef-keyed folds substitute a chosen
concrete value for the reported elements, which is invalid for poison
since consuming a poison element yields poison.
No functional change.
---
llvm/include/llvm/CodeGen/TargetLowering.h | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h
index c08d0e53ec34b3..448fa84e27013b 100644
--- a/llvm/include/llvm/CodeGen/TargetLowering.h
+++ b/llvm/include/llvm/CodeGen/TargetLowering.h
@@ -4496,6 +4496,10 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// KnownZero elements for the expression (used to simplify the caller).
/// The KnownUndef/Zero elements may only be accurate for those bits
/// in the DemandedMask.
+ /// KnownUndef only reports elements known to be undef; elements that are
+ /// (only) known to be poison are never reported as undef, because
+ /// undef-keyed folds substitute a chosen concrete value for those elements,
+ /// which is invalid for poison - consuming a poison element yields poison.
/// \p AssumeSingleUse When this parameter is true, this function will
/// attempt to simplify \p Op even if there are multiple uses.
/// Callers are responsible for correctly updating the DAG based on the
@@ -4596,7 +4600,9 @@ class LLVM_ABI TargetLowering : public TargetLoweringBase {
/// elements, returning true on success. Otherwise, analyze the expression and
/// return a mask of KnownUndef and KnownZero elements for the expression
/// (used to simplify the caller). The KnownUndef/Zero elements may only be
- /// accurate for those bits in the DemandedMask.
+ /// accurate for those bits in the DemandedMask. As with
+ /// SimplifyDemandedVectorElts, poison elements must never be reported as
+ /// KnownUndef.
virtual bool SimplifyDemandedVectorEltsForTargetNode(
SDValue Op, const APInt &DemandedElts, APInt &KnownUndef,
APInt &KnownZero, TargetLoweringOpt &TLO, unsigned Depth = 0) const;
>From 4778da931498a1f3de199eda5cf3ce4f7243a8fa Mon Sep 17 00:00:00 2001
From: Cyrus Ding <785101675 at qq.com>
Date: Mon, 28 Sep 2026 09:29:35 +0800
Subject: [PATCH 3/3] [DAG] SimplifyDemandedVectorElts - don't report POISON
ops as KnownUndef
SDNode::isUndef() returns true for both ISD::UNDEF and ISD::POISON, so the
"Undef operand" early-out in SimplifyDemandedVectorElts marked every
element KnownUndef for a POISON Op as well. KnownUndef bits license folds
that substitute a chosen concrete value (e.g. zext(undef) -> 0 via
DemandedElts.isSubsetOf(KnownUndef), and the AND(0, undef) -> 0 shuffle
combines), which is invalid for poison - consuming a poison element
yields poison. Only mark the bits for genuine ISD::UNDEF ops; poison ops
now bail out leaving the elements unknown.
This is the same soundness rule #217185 applied to the SCALAR_TO_VECTOR
upper elements, extended to the general early-out, as flagged by
@RKSimon in review on #226003. The PowerPC scalar_to_vector shuffle tests
are updated to the resulting (conservative) codegen; those simplifications
were keyed on KnownUndef bits of poison lanes, and restoring them soundly
needs poison-aware demanded-elts folds - tracked separately rather than
blocking this fix. Supersedes the exploration in #226124.
---
.../CodeGen/SelectionDAG/TargetLowering.cpp | 7 +-
.../PowerPC/v16i8_scalar_to_vector_shuffle.ll | 17 ++-
.../PowerPC/v8i16_scalar_to_vector_shuffle.ll | 101 ++++++++++++------
3 files changed, 88 insertions(+), 37 deletions(-)
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 1b48a9bbce0628..a4f9779264283c 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -3283,9 +3283,12 @@ bool TargetLowering::SimplifyDemandedVectorElts(
assert(VT.getVectorNumElements() == NumElts &&
"Mask size mismatches value type element count!");
- // Undef operand.
+ // Undef operand. SDNode::isUndef() is also true for ISD::POISON, but poison
+ // elements must not be reported as KnownUndef: undef-keyed folds substitute
+ // a chosen concrete value for those elements, which is invalid for poison.
if (Op.isUndef()) {
- KnownUndef.setAllBits();
+ if (Op.getOpcode() == ISD::UNDEF)
+ KnownUndef.setAllBits();
return false;
}
diff --git a/llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll b/llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll
index 8f827dfee2a472..b1f26e83211a78 100644
--- a/llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll
+++ b/llvm/test/CodeGen/PowerPC/v16i8_scalar_to_vector_shuffle.ll
@@ -28,18 +28,25 @@
define <16 x i8> @test_v16i8_v16i8(ptr nocapture noundef readonly %a, ptr nocapture noundef readonly %b) {
; CHECK-LE-P8-LABEL: test_v16i8_v16i8:
; CHECK-LE-P8: # %bb.0: # %entry
+; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI0_0 at toc@ha
; CHECK-LE-P8-NEXT: lbz r3, 0(r3)
; CHECK-LE-P8-NEXT: lbz r4, 0(r4)
-; CHECK-LE-P8-NEXT: mtvsrd v2, r3
-; CHECK-LE-P8-NEXT: mtvsrd v3, r4
-; CHECK-LE-P8-NEXT: vmrghh v2, v3, v2
+; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI0_0 at toc@l
+; CHECK-LE-P8-NEXT: mtvsrd v3, r3
+; CHECK-LE-P8-NEXT: mtvsrd v4, r4
+; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5
+; CHECK-LE-P8-NEXT: xxswapd v2, vs0
+; CHECK-LE-P8-NEXT: vperm v2, v4, v3, v2
; CHECK-LE-P8-NEXT: blr
;
; CHECK-LE-P9-LABEL: test_v16i8_v16i8:
; CHECK-LE-P9: # %bb.0: # %entry
+; CHECK-LE-P9-NEXT: addis r5, r2, .LCPI0_0 at toc@ha
; CHECK-LE-P9-NEXT: lxsibzx v2, 0, r3
-; CHECK-LE-P9-NEXT: lxsibzx v3, 0, r4
-; CHECK-LE-P9-NEXT: vmrghh v2, v3, v2
+; CHECK-LE-P9-NEXT: lxsibzx f1, 0, r4
+; CHECK-LE-P9-NEXT: addi r5, r5, .LCPI0_0 at toc@l
+; CHECK-LE-P9-NEXT: lxv vs0, 0(r5)
+; CHECK-LE-P9-NEXT: xxperm v2, vs1, vs0
; CHECK-LE-P9-NEXT: blr
;
; CHECK-BE-P8-LABEL: test_v16i8_v16i8:
diff --git a/llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll b/llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll
index 3c9bd0a585a095..fc2528d19003c1 100644
--- a/llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll
+++ b/llvm/test/CodeGen/PowerPC/v8i16_scalar_to_vector_shuffle.ll
@@ -1058,17 +1058,24 @@ entry:
define <16 x i8> @test_v4i32_v8i16(ptr %a, ptr %b) local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_v4i32_v8i16:
; CHECK-LE-P8: # %bb.0: # %entry
+; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI10_0 at toc@ha
; CHECK-LE-P8-NEXT: lhz r3, 0(r3)
-; CHECK-LE-P8-NEXT: lxsiwzx v3, 0, r4
-; CHECK-LE-P8-NEXT: mtvsrd v2, r3
-; CHECK-LE-P8-NEXT: vmrghh v2, v2, v3
+; CHECK-LE-P8-NEXT: lxsiwzx v4, 0, r4
+; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI10_0 at toc@l
+; CHECK-LE-P8-NEXT: mtvsrd v3, r3
+; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5
+; CHECK-LE-P8-NEXT: xxswapd v2, vs0
+; CHECK-LE-P8-NEXT: vperm v2, v3, v4, v2
; CHECK-LE-P8-NEXT: blr
;
; CHECK-LE-P9-LABEL: test_v4i32_v8i16:
; CHECK-LE-P9: # %bb.0: # %entry
-; CHECK-LE-P9-NEXT: lxsihzx v2, 0, r3
-; CHECK-LE-P9-NEXT: lxsiwzx v3, 0, r4
-; CHECK-LE-P9-NEXT: vmrghh v2, v2, v3
+; CHECK-LE-P9-NEXT: lxsihzx f0, 0, r3
+; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI10_0 at toc@ha
+; CHECK-LE-P9-NEXT: lxsiwzx v2, 0, r4
+; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI10_0 at toc@l
+; CHECK-LE-P9-NEXT: lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1
; CHECK-LE-P9-NEXT: blr
;
; CHECK-BE-P8-LABEL: test_v4i32_v8i16:
@@ -1340,48 +1347,65 @@ entry:
define <16 x i8> @test_v2i64_v4i32(ptr %a, ptr %b) local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_v2i64_v4i32:
; CHECK-LE-P8: # %bb.0: # %entry
-; CHECK-LE-P8-NEXT: lxsiwzx v2, 0, r3
-; CHECK-LE-P8-NEXT: lxsdx v3, 0, r4
-; CHECK-LE-P8-NEXT: vmrghh v2, v2, v3
+; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI13_0 at toc@ha
+; CHECK-LE-P8-NEXT: lxsiwzx v3, 0, r3
+; CHECK-LE-P8-NEXT: lxsdx v4, 0, r4
+; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI13_0 at toc@l
+; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5
+; CHECK-LE-P8-NEXT: xxswapd v2, vs0
+; CHECK-LE-P8-NEXT: vperm v2, v3, v4, v2
; CHECK-LE-P8-NEXT: blr
;
; CHECK-LE-P9-LABEL: test_v2i64_v4i32:
; CHECK-LE-P9: # %bb.0: # %entry
-; CHECK-LE-P9-NEXT: lxsiwzx v2, 0, r3
-; CHECK-LE-P9-NEXT: lxsd v3, 0(r4)
-; CHECK-LE-P9-NEXT: vmrghh v2, v2, v3
+; CHECK-LE-P9-NEXT: lfiwzx f0, 0, r3
+; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI13_0 at toc@ha
+; CHECK-LE-P9-NEXT: lxsd v2, 0(r4)
+; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI13_0 at toc@l
+; CHECK-LE-P9-NEXT: lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1
; CHECK-LE-P9-NEXT: blr
;
; CHECK-BE-P8-LABEL: test_v2i64_v4i32:
; CHECK-BE-P8: # %bb.0: # %entry
; CHECK-BE-P8-NEXT: lfiwzx f0, 0, r3
+; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI13_0 at toc@ha
; CHECK-BE-P8-NEXT: lxsdx v3, 0, r4
+; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI13_0 at toc@l
+; CHECK-BE-P8-NEXT: lxvw4x v4, 0, r3
; CHECK-BE-P8-NEXT: xxsldwi v2, f0, f0, 1
-; CHECK-BE-P8-NEXT: vmrghh v2, v3, v2
+; CHECK-BE-P8-NEXT: vperm v2, v3, v2, v4
; CHECK-BE-P8-NEXT: blr
;
; CHECK-BE-P9-LABEL: test_v2i64_v4i32:
; CHECK-BE-P9: # %bb.0: # %entry
; CHECK-BE-P9-NEXT: lfiwzx f0, 0, r3
-; CHECK-BE-P9-NEXT: lxsd v3, 0(r4)
+; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI13_0 at toc@ha
+; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI13_0 at toc@l
+; CHECK-BE-P9-NEXT: lxv vs1, 0(r3)
; CHECK-BE-P9-NEXT: xxsldwi v2, f0, f0, 1
-; CHECK-BE-P9-NEXT: vmrghh v2, v3, v2
+; CHECK-BE-P9-NEXT: lfd f0, 0(r4)
+; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1
; CHECK-BE-P9-NEXT: blr
;
; CHECK-AIX-64-P8-LABEL: test_v2i64_v4i32:
; CHECK-AIX-64-P8: # %bb.0: # %entry
; CHECK-AIX-64-P8-NEXT: lfiwzx f0, 0, r3
+; CHECK-AIX-64-P8-NEXT: ld r3, L..C12(r2) # %const.0
; CHECK-AIX-64-P8-NEXT: lxsdx v3, 0, r4
+; CHECK-AIX-64-P8-NEXT: lxvw4x v4, 0, r3
; CHECK-AIX-64-P8-NEXT: xxsldwi v2, f0, f0, 1
-; CHECK-AIX-64-P8-NEXT: vmrghh v2, v3, v2
+; CHECK-AIX-64-P8-NEXT: vperm v2, v3, v2, v4
; CHECK-AIX-64-P8-NEXT: blr
;
; CHECK-AIX-64-P9-LABEL: test_v2i64_v4i32:
; CHECK-AIX-64-P9: # %bb.0: # %entry
; CHECK-AIX-64-P9-NEXT: lfiwzx f0, 0, r3
-; CHECK-AIX-64-P9-NEXT: lxsd v3, 0(r4)
+; CHECK-AIX-64-P9-NEXT: ld r3, L..C11(r2) # %const.0
; CHECK-AIX-64-P9-NEXT: xxsldwi v2, f0, f0, 1
-; CHECK-AIX-64-P9-NEXT: vmrghh v2, v3, v2
+; CHECK-AIX-64-P9-NEXT: lfd f0, 0(r4)
+; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3)
+; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1
; CHECK-AIX-64-P9-NEXT: blr
;
; CHECK-AIX-32-P8-LABEL: test_v2i64_v4i32:
@@ -1417,17 +1441,24 @@ entry:
define <16 x i8> @test_v2i64_v8i16(ptr %a, ptr %b) local_unnamed_addr {
; CHECK-LE-P8-LABEL: test_v2i64_v8i16:
; CHECK-LE-P8: # %bb.0: # %entry
+; CHECK-LE-P8-NEXT: addis r5, r2, .LCPI14_0 at toc@ha
; CHECK-LE-P8-NEXT: lhz r3, 0(r3)
-; CHECK-LE-P8-NEXT: lxsdx v3, 0, r4
-; CHECK-LE-P8-NEXT: mtvsrd v2, r3
-; CHECK-LE-P8-NEXT: vmrghh v2, v2, v3
+; CHECK-LE-P8-NEXT: lxsdx v4, 0, r4
+; CHECK-LE-P8-NEXT: addi r5, r5, .LCPI14_0 at toc@l
+; CHECK-LE-P8-NEXT: mtvsrd v3, r3
+; CHECK-LE-P8-NEXT: lxvd2x vs0, 0, r5
+; CHECK-LE-P8-NEXT: xxswapd v2, vs0
+; CHECK-LE-P8-NEXT: vperm v2, v3, v4, v2
; CHECK-LE-P8-NEXT: blr
;
; CHECK-LE-P9-LABEL: test_v2i64_v8i16:
; CHECK-LE-P9: # %bb.0: # %entry
-; CHECK-LE-P9-NEXT: lxsihzx v2, 0, r3
-; CHECK-LE-P9-NEXT: lxsd v3, 0(r4)
-; CHECK-LE-P9-NEXT: vmrghh v2, v2, v3
+; CHECK-LE-P9-NEXT: lxsihzx f0, 0, r3
+; CHECK-LE-P9-NEXT: addis r3, r2, .LCPI14_0 at toc@ha
+; CHECK-LE-P9-NEXT: lxsd v2, 0(r4)
+; CHECK-LE-P9-NEXT: addi r3, r3, .LCPI14_0 at toc@l
+; CHECK-LE-P9-NEXT: lxv vs1, 0(r3)
+; CHECK-LE-P9-NEXT: xxperm v2, vs0, vs1
; CHECK-LE-P9-NEXT: blr
;
; CHECK-BE-P8-LABEL: test_v2i64_v8i16:
@@ -1436,15 +1467,21 @@ define <16 x i8> @test_v2i64_v8i16(ptr %a, ptr %b) local_unnamed_addr {
; CHECK-BE-P8-NEXT: lxsdx v3, 0, r4
; CHECK-BE-P8-NEXT: sldi r3, r3, 48
; CHECK-BE-P8-NEXT: mtvsrd v2, r3
-; CHECK-BE-P8-NEXT: vmrghh v2, v3, v2
+; CHECK-BE-P8-NEXT: addis r3, r2, .LCPI14_0 at toc@ha
+; CHECK-BE-P8-NEXT: addi r3, r3, .LCPI14_0 at toc@l
+; CHECK-BE-P8-NEXT: lxvw4x v4, 0, r3
+; CHECK-BE-P8-NEXT: vperm v2, v3, v2, v4
; CHECK-BE-P8-NEXT: blr
;
; CHECK-BE-P9-LABEL: test_v2i64_v8i16:
; CHECK-BE-P9: # %bb.0: # %entry
; CHECK-BE-P9-NEXT: lxsihzx v2, 0, r3
-; CHECK-BE-P9-NEXT: lxsd v3, 0(r4)
+; CHECK-BE-P9-NEXT: addis r3, r2, .LCPI14_0 at toc@ha
+; CHECK-BE-P9-NEXT: lfd f0, 0(r4)
+; CHECK-BE-P9-NEXT: addi r3, r3, .LCPI14_0 at toc@l
+; CHECK-BE-P9-NEXT: lxv vs1, 0(r3)
; CHECK-BE-P9-NEXT: vsplth v2, v2, 3
-; CHECK-BE-P9-NEXT: vmrghh v2, v3, v2
+; CHECK-BE-P9-NEXT: xxperm v2, vs0, vs1
; CHECK-BE-P9-NEXT: blr
;
; CHECK-AIX-64-P8-LABEL: test_v2i64_v8i16:
@@ -1453,15 +1490,19 @@ define <16 x i8> @test_v2i64_v8i16(ptr %a, ptr %b) local_unnamed_addr {
; CHECK-AIX-64-P8-NEXT: lxsdx v3, 0, r4
; CHECK-AIX-64-P8-NEXT: sldi r3, r3, 48
; CHECK-AIX-64-P8-NEXT: mtvsrd v2, r3
-; CHECK-AIX-64-P8-NEXT: vmrghh v2, v3, v2
+; CHECK-AIX-64-P8-NEXT: ld r3, L..C13(r2) # %const.0
+; CHECK-AIX-64-P8-NEXT: lxvw4x v4, 0, r3
+; CHECK-AIX-64-P8-NEXT: vperm v2, v3, v2, v4
; CHECK-AIX-64-P8-NEXT: blr
;
; CHECK-AIX-64-P9-LABEL: test_v2i64_v8i16:
; CHECK-AIX-64-P9: # %bb.0: # %entry
; CHECK-AIX-64-P9-NEXT: lxsihzx v2, 0, r3
-; CHECK-AIX-64-P9-NEXT: lxsd v3, 0(r4)
+; CHECK-AIX-64-P9-NEXT: ld r3, L..C12(r2) # %const.0
+; CHECK-AIX-64-P9-NEXT: lfd f0, 0(r4)
+; CHECK-AIX-64-P9-NEXT: lxv vs1, 0(r3)
; CHECK-AIX-64-P9-NEXT: vsplth v2, v2, 3
-; CHECK-AIX-64-P9-NEXT: vmrghh v2, v3, v2
+; CHECK-AIX-64-P9-NEXT: xxperm v2, vs0, vs1
; CHECK-AIX-64-P9-NEXT: blr
;
; CHECK-AIX-32-P8-LABEL: test_v2i64_v8i16:
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