[llvm] [AMDGPU][NFC] De-factorize scalar_to_vector bf16 patterns (PR #226847)

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<!--LLVM PR SUMMARY COMMENT-->

@llvm/pr-subscribers-backend-amdgpu

Author: Changpeng Fang (changpeng)

<details>
<summary>Changes</summary>

For Fake16, an SGPR and a VGPR can share the same scalar_to_vector pattern because there is no 16-bit SGPR at all. The separate uniform SGPR pattern is therefore only needed for Real True16, where the divergent case uses a VGPR_16 REG_SEQUENCE.

This de-factorization is to prepare for follow-up PRs to separate SGPR and VGPR patterns of scalar_to_vector for other types.

---
Full diff: https://github.com/llvm/llvm-project/pull/226847.diff


1 Files Affected:

- (modified) llvm/lib/Target/AMDGPU/SIInstructions.td (+5-5) 


``````````diff
diff --git a/llvm/lib/Target/AMDGPU/SIInstructions.td b/llvm/lib/Target/AMDGPU/SIInstructions.td
index 3cf20ffb1fcf4..823a8b3a0c9f9 100644
--- a/llvm/lib/Target/AMDGPU/SIInstructions.td
+++ b/llvm/lib/Target/AMDGPU/SIInstructions.td
@@ -4256,8 +4256,8 @@ def : GCNPat <
 >;
 
 def : GCNPat <
-  (v2bf16 (DivergentUnaryFrag<scalar_to_vector> (bf16 VGPR_32:$src0))),
-  (COPY VGPR_32:$src0)
+  (v2bf16 (scalar_to_vector bf16:$src0)),
+  (COPY $src0)
 >;
 }
 
@@ -4286,14 +4286,14 @@ def : GCNPat <
   (v2bf16 (DivergentUnaryFrag<scalar_to_vector> (bf16 VGPR_16:$src0))),
   (REG_SEQUENCE VGPR_32, VGPR_16:$src0, lo16, (i16 (IMPLICIT_DEF)), hi16)
 >;
-}
 
-// A bf16 value can only be in the low 16 bits of an SGPR, regardless of
-// Real-True16 or Fake-True16.
+// Unlike the divergent case above, a uniform bf16 value lives in the low 16
+// bits of a 32-bit SGPR even for Real-True16, so a plain COPY is enough.
 def : GCNPat <
   (v2bf16 (UniformUnaryFrag<scalar_to_vector> (bf16 SReg_32:$src0))),
   (COPY SReg_32:$src0)
 >;
+}
 
 def : GCNPat <
   (i64 (int_amdgcn_mov_dpp i64:$src, timm:$dpp_ctrl, timm:$row_mask,

``````````

</details>


https://github.com/llvm/llvm-project/pull/226847