[llvm] [Mips] Fix R6 floating-point condition register handling (PR #226838)
via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 27 14:40:45 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-mips
Author: Jiaxun Yang (FlyGoat)
<details>
<summary>Changes</summary>
Sharing a predicate between R6 floating-point selects can produce copies between incompatible register classes and crash in copyPhysReg. The condition classes model both CMP.S and CMP.D results as i32, despite the instructions writing 32-bit and 64-bit FPRs respectively.
Use ordinary FPR classes for compare results and tied select operands. Represent the legalized i32 condition with a same-width copy for CMP.S and a low-word subregister for CMP.D. Insert the condition into the low word for SEL.D, leaving the unused upper word undefined. This lets register coalescing handle shared predicates and mixed-precision users, removing the special condition classes, copy heuristics and register-flags pass.
Select BC1EQZ/BC1NEZ directly for FP comparison conditions, including their microMIPS counterparts, and support them in branch analysis. These branches read bit zero, avoiding a GPR transfer and boolean normalization. Fold normalization of known 0/-1 masks into zero/nonzero branches as well, while preserving normalization for integer users that require 0/1.
Add coverage for shared predicates, mixed precision, PHIs, spills and all nonconstant FP branch predicates across MIPS32r6, MIPS64r6 and microMIPS, including both byte orders. Update branch analysis and long-branch tests.
Fixes: #<!-- -->223905
Fixes: #<!-- -->224541
Fixes: #<!-- -->224542
Assisted-by: OpenAI Codex
---
Patch is 93.20 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/226838.diff
25 Files Affected:
- (modified) llvm/lib/Target/Mips/CMakeLists.txt (-1)
- (modified) llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp (-22)
- (modified) llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h (-10)
- (modified) llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td (+32-23)
- (modified) llvm/lib/Target/Mips/Mips.h (-2)
- (modified) llvm/lib/Target/Mips/Mips32r6InstrInfo.td (+101-60)
- (modified) llvm/lib/Target/Mips/MipsMTInstrInfo.td (+2-2)
- (modified) llvm/lib/Target/Mips/MipsRegisterInfo.td (-17)
- (modified) llvm/lib/Target/Mips/MipsSEISelLowering.cpp (-17)
- (modified) llvm/lib/Target/Mips/MipsSEISelLowering.h (-1)
- (modified) llvm/lib/Target/Mips/MipsSEInstrInfo.cpp (+24-116)
- (removed) llvm/lib/Target/Mips/MipsSetMachineRegisterFlags.cpp (-111)
- (modified) llvm/lib/Target/Mips/MipsTargetMachine.cpp (-2)
- (modified) llvm/test/CodeGen/Mips/analyzebranch.ll (+10-19)
- (modified) llvm/test/CodeGen/Mips/fcmp.ll (+6-22)
- (modified) llvm/test/CodeGen/Mips/fpbr.ll (+47-40)
- (modified) llvm/test/CodeGen/Mips/llvm-ir/select-dbl.ll (+2-2)
- (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-micromipsr6.mir (+8-8)
- (modified) llvm/test/CodeGen/Mips/longbranch/branch-limits-fp-mipsr6.mir (+8-8)
- (modified) llvm/test/CodeGen/Mips/micromips-mtc-mfc.ll (+22-2)
- (modified) llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll (+2-2)
- (added) llvm/test/CodeGen/Mips/r6-fp-branch.ll (+434)
- (added) llvm/test/CodeGen/Mips/r6-fp-condition-spill.mir (+45)
- (added) llvm/test/CodeGen/Mips/r6-fp-condition-subregs.ll (+217)
- (modified) llvm/test/CodeGen/Mips/select.ll (+4-2)
``````````diff
diff --git a/llvm/lib/Target/Mips/CMakeLists.txt b/llvm/lib/Target/Mips/CMakeLists.txt
index 918a099b68df8..119cd34c369aa 100644
--- a/llvm/lib/Target/Mips/CMakeLists.txt
+++ b/llvm/lib/Target/Mips/CMakeLists.txt
@@ -60,7 +60,6 @@ add_llvm_target(MipsCodeGen
MipsSEISelLowering.cpp
MipsSERegisterInfo.cpp
MipsSelectionDAGInfo.cpp
- MipsSetMachineRegisterFlags.cpp
MipsSubtarget.cpp
MipsTargetMachine.cpp
MipsTargetObjectFile.cpp
diff --git a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
index bbd614fc64423..54c8cec035832 100644
--- a/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
+++ b/llvm/lib/Target/Mips/Disassembler/MipsDisassembler.cpp
@@ -995,28 +995,6 @@ static DecodeStatus DecodeFCCRegisterClass(MCInst &Inst, unsigned RegNo,
return MCDisassembler::Success;
}
-static DecodeStatus DecodeFGR32CCRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if (RegNo > 31)
- return MCDisassembler::Fail;
-
- MCRegister Reg = getReg(Decoder, Mips::FGR32CCRegClassID, RegNo);
- Inst.addOperand(MCOperand::createReg(Reg));
- return MCDisassembler::Success;
-}
-
-static DecodeStatus DecodeFGR64CCRegisterClass(MCInst &Inst, unsigned RegNo,
- uint64_t Address,
- const MCDisassembler *Decoder) {
- if (RegNo > 31)
- return MCDisassembler::Fail;
-
- MCRegister Reg = getReg(Decoder, Mips::FGR64CCRegClassID, RegNo);
- Inst.addOperand(MCOperand::createReg(Reg));
- return MCDisassembler::Success;
-}
-
static DecodeStatus DecodeMem(MCInst &Inst, unsigned Insn, uint64_t Address,
const MCDisassembler *Decoder) {
int Offset = SignExtend32<16>(Insn & 0xffff);
diff --git a/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h b/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
index a265331c0610e..0fd873002981a 100644
--- a/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
+++ b/llvm/lib/Target/Mips/MCTargetDesc/MipsBaseInfo.h
@@ -154,16 +154,6 @@ inline static MCRegister getMSARegFromFReg(MCRegister Reg) {
return MCRegister();
}
-inline static MCRegister getFloatRegFromFReg(MCRegister Reg) {
- if (Reg >= Mips::F0 && Reg <= Mips::F31)
- return Reg;
- else if (Reg >= Mips::D0_64 && Reg <= Mips::D31_64)
- return Reg - Mips::D0_64 + Mips::F0;
- else if (Reg >= Mips::W0 && Reg <= Mips::W31)
- return Reg - Mips::W0 + Mips::F0;
- return Mips::NoRegister;
-}
-
} // namespace llvm
#endif
diff --git a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
index 5487254c14ab3..9fdda60e247ba 100644
--- a/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/MicroMips32r6InstrInfo.td
@@ -878,73 +878,72 @@ class CVT_S_L_MMR6_DESC : CVT_MMR6_DESC_BASE<"cvt.s.l", FGR64Opnd, FGR32Opnd>,
FGR_64;
multiclass CMP_CC_MMR6<bits<6> format, string Typestr,
- RegisterOperand FGROpnd,
- RegisterOperand FGRCCOpnd> {
+ RegisterOperand FGROpnd> {
def CMP_AF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.af.", Typestr), format, FIELD_CMP_COND_AF>,
- CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_UN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.un.", Typestr), format, FIELD_CMP_COND_UN>,
- CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, FGRCCOpnd, setuo>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_EQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.eq.", Typestr), format, FIELD_CMP_COND_EQ>,
- CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, FGRCCOpnd, setoeq>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_UEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ueq.", Typestr), format, FIELD_CMP_COND_UEQ>,
- CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, FGRCCOpnd, setueq>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_LT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.lt.", Typestr), format, FIELD_CMP_COND_LT>,
- CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, FGRCCOpnd, setolt>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_ULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ult.", Typestr), format, FIELD_CMP_COND_ULT>,
- CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, FGRCCOpnd, setult>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_LE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.le.", Typestr), format, FIELD_CMP_COND_LE>,
- CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, FGRCCOpnd, setole>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_ULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.ule.", Typestr), format, FIELD_CMP_COND_ULE>,
- CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, FGRCCOpnd, setule>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
let mayRaiseFPException = 1 in {
def CMP_SAF_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.saf.", Typestr), format, FIELD_CMP_COND_SAF>,
- CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SUN_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sun.", Typestr), format, FIELD_CMP_COND_SUN>,
- CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.seq.", Typestr), format, FIELD_CMP_COND_SEQ>,
- CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SUEQ_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sueq.", Typestr), format, FIELD_CMP_COND_SUEQ>,
- CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SLT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.slt.", Typestr), format, FIELD_CMP_COND_SLT>,
- CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SULT_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sult.", Typestr), format, FIELD_CMP_COND_SULT>,
- CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SLE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sle.", Typestr), format, FIELD_CMP_COND_SLE>,
- CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
def CMP_SULE_#NAME : R6MMR6Rel, POOL32F_CMP_FM<
!strconcat("cmp.sule.", Typestr), format, FIELD_CMP_COND_SULE>,
- CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, FGRCCOpnd>, HARDFLOAT,
+ CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>, HARDFLOAT,
ISA_MICROMIPS32R6;
}
}
@@ -998,8 +997,8 @@ class ROUND_W_S_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.s", FGR32Opnd,
class ROUND_W_D_MMR6_DESC : ABSS_FT_MMR6_DESC_BASE<"round.w.d", FGR64Opnd,
FGR64Opnd>;
-class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd, FGR32CCOpnd>;
-class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd, FGR64CCOpnd>;
+class SEL_S_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.s", FGR32Opnd>;
+class SEL_D_MMR6_DESC : COP1_SEL_DESC_BASE<"sel.d", FGR64Opnd>;
class SELEQZ_S_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.s", FGR32Opnd>;
class SELEQZ_D_MMR6_DESC : SELEQNEZ_DESC_BASE<"seleqz.d", FGR64Opnd>;
@@ -1185,7 +1184,7 @@ class BNEZC_MMR6_DESC
MMR6Arch<"bnezc">;
class BRANCH_COP1_MMR6_DESC_BASE<string opstr> :
- InstSE<(outs), (ins FGR64Opnd:$rt, brtarget_mm:$offset),
+ InstSE<(outs), (ins FGR32Opnd:$rt, brtarget_mm:$offset),
!strconcat(opstr, "\t$rt, $offset"), [], FrmI>,
HARDFLOAT, BRANCH_DESC_BASE {
list<Register> Defs = [AT];
@@ -1423,8 +1422,8 @@ let mayRaiseFPException = 1 in {
}
}
-defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd, FGR32CCOpnd>;
-defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd, FGR64CCOpnd>;
+defm S_MMR6 : CMP_CC_MMR6<0b000101, "s", FGR32Opnd>;
+defm D_MMR6 : CMP_CC_MMR6<0b010101, "d", FGR64Opnd>;
let mayRaiseFPException = 1 in {
def FLOOR_L_S_MMR6 : StdMMR6Rel, FLOOR_L_S_MMR6_ENC, FLOOR_L_S_MMR6_DESC,
ISA_MICROMIPS32R6;
@@ -1690,6 +1689,16 @@ defm : SelectInt_Pats<i32, OR_MM, XORI_MMR6, SLTi_MM, SLTiu_MM, SELEQZ_MMR6,
defm S_MMR6 : Cmp_Pats<f32>, ISA_MICROMIPS32R6;
defm D_MMR6 : Cmp_Pats<f64>, ISA_MICROMIPS32R6;
+defm : FPBrcondPats<BC1EQZC_MMR6, BC1NEZC_MMR6>, ISA_MICROMIPS32R6;
+
+def : MipsPat<(brcond (and i32_zero_or_negative_one:$cond, 1), bb:$dst),
+ (BNEZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;
+def : MipsPat<(brcond (and (not i32_zero_or_negative_one:$cond), 1), bb:$dst),
+ (BEQZC_MMR6 GPR32:$cond, bb:$dst)>, ISA_MICROMIPS32R6;
+
+def : SEL_FP_PAT<FGR32Opnd, SEL_S_MMR6>, ISA_MICROMIPS32R6;
+def : SEL_FP_PAT<FGR64Opnd, SEL_D_MMR6>, ISA_MICROMIPS32R6;
+
def : MipsPat<(f32 fpimm0), (MTC1_MMR6 ZERO)>, ISA_MICROMIPS32R6;
def : MipsPat<(f32 fpimm0neg), (FNEG_S_MMR6(MTC1_MMR6 ZERO))>,
ISA_MICROMIPS32R6;
diff --git a/llvm/lib/Target/Mips/Mips.h b/llvm/lib/Target/Mips/Mips.h
index da06d33f15223..053bc3d0e4a41 100644
--- a/llvm/lib/Target/Mips/Mips.h
+++ b/llvm/lib/Target/Mips/Mips.h
@@ -50,7 +50,6 @@ FunctionPass *createMipsExpandPseudoPass();
FunctionPass *createMipsPreLegalizeCombiner();
FunctionPass *createMipsPostLegalizeCombiner(bool IsOptNone);
FunctionPass *createMipsMulMulBugPass();
-FunctionPass *createMipsSetMachineRegisterFlagsPass();
InstructionSelector *
createMipsInstructionSelector(const MipsTargetMachine &, const MipsSubtarget &,
@@ -64,7 +63,6 @@ void initializeMipsDelaySlotFillerPass(PassRegistry &);
void initializeMipsMulMulBugFixPass(PassRegistry &);
void initializeMipsPostLegalizerCombinerPass(PassRegistry &);
void initializeMipsPreLegalizerCombinerPass(PassRegistry &);
-void initializeMipsSetMachineRegisterFlagsPass(PassRegistry &);
} // namespace llvm
#endif
diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
index 5283a5da43eee..2f7039985697a 100644
--- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
+++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td
@@ -12,19 +12,6 @@
include "Mips32r6InstrFormats.td"
-//===----------------------------------------------------------------------===//
-//
-// Mips profiles and nodes
-//
-//===----------------------------------------------------------------------===//
-
-def SDT_MipsFSelect : SDTypeProfile<1, 3, [SDTCisFP<1>,
- SDTCisSameAs<0,2>,
- SDTCisSameAs<2,3>]>;
-
-// Floating point select
-def MipsFSelect : SDNode<"MipsISD::FSELECT", SDT_MipsFSelect>;
-
//===----------------------------------------------------------------------===//
//
// Mips Operands
@@ -211,100 +198,90 @@ class SIGRIE_ENC : SIGRIE_FM;
//===----------------------------------------------------------------------===//
class CMP_CONDN_DESC_BASE<string CondStr, string Typestr,
- RegisterOperand FGROpnd,
- RegisterOperand FGRCCOpnd,
- SDPatternOperator Op = null_frag> {
- dag OutOperandList = (outs FGRCCOpnd:$fd);
+ RegisterOperand FGROpnd> : NeverHasSideEffects {
+ dag OutOperandList = (outs FGROpnd:$fd);
dag InOperandList = (ins FGROpnd:$fs, FGROpnd:$ft);
string AsmString = !strconcat("cmp.", CondStr, ".", Typestr, "\t$fd, $fs, $ft");
- list<dag> Pattern = [(set FGRCCOpnd:$fd, (Op FGROpnd:$fs, FGROpnd:$ft))];
bit isCTI = 1;
}
multiclass CMP_CC_M <FIELD_CMP_FORMAT Format, string Typestr,
- RegisterOperand FGROpnd,
- RegisterOperand FGRCCOpnd>{
+ RegisterOperand FGROpnd>{
let AdditionalPredicates = [NotInMicroMips] in {
def CMP_F_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_AF>,
- CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"af", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.af.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_UN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_UN>,
- CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd, FGRCCOpnd, setuo>,
+ CMP_CONDN_DESC_BASE<"un", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.un.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_EQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_EQ>,
- CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd, FGRCCOpnd,
- setoeq>,
+ CMP_CONDN_DESC_BASE<"eq", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.eq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_UEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_UEQ>,
- CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd, FGRCCOpnd,
- setueq>,
+ CMP_CONDN_DESC_BASE<"ueq", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.ueq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_LT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LT>,
- CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd, FGRCCOpnd,
- setolt>,
+ CMP_CONDN_DESC_BASE<"lt", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.lt.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_ULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_ULT>,
- CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd, FGRCCOpnd,
- setult>,
+ CMP_CONDN_DESC_BASE<"ult", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.ult.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_LE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format, FIELD_CMP_COND_LE>,
- CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd, FGRCCOpnd,
- setole>,
+ CMP_CONDN_DESC_BASE<"le", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.le.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_ULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_ULE>,
- CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd, FGRCCOpnd,
- setule>,
+ CMP_CONDN_DESC_BASE<"ule", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.ule.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
let mayRaiseFPException = 1 in {
def CMP_SAF_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SAF>,
- CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"saf", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.saf.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SUN_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SUN>,
- CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"sun", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.sun.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SEQ>,
- CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"seq", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.seq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SUEQ_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SUEQ>,
- CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"sueq", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.sueq.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SLT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SLT>,
- CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"slt", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.slt.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SULT_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SULT>,
- CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"sult", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.sult.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SLE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SLE>,
- CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"sle", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.sle.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
def CMP_SULE_#NAME : R6MMR6Rel, COP1_CMP_CONDN_FM<Format,
FIELD_CMP_COND_SULE>,
- CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd, FGRCCOpnd>,
+ CMP_CONDN_DESC_BASE<"sule", Typestr, FGROpnd>,
MipsR6Arch<!strconcat("cmp.sule.", Typestr)>,
ISA_MIPS32R6, HARDFLOAT;
}
@@ -454,8 +431,7 @@ class BEQZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"beqzc", brtarget21, GPR32Opnd>;
class BNEZC_DESC : CMP_CBR_EQNE_Z_DESC_BASE<"bnezc", brtarget21, GPR32Opnd>;
class COP1_BCCZ_DESC_BASE<string instr_asm> : BRANCH_DESC_BASE {
- dag InOperandList = (ins FGR64Opnd:$ft, brtarget:$offset);
- dag OutOperandList = (outs);
+ dag InOperandList = (ins FGR32Opnd:$ft, brtarget:$offset);
string AsmString = instr_asm;
bit hasDelaySlot = 1;
}
@@ -588,20 +564,16 @@ class MUL_R6_DESC : MUL_R6_DESC_BASE<"mul", GPR32Opnd, mul>;
class MULU_DESC : MUL_R6_DESC_...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/226838
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