[llvm] [X86][APX] Precommit test for BLSI/BLSMSK i8 patterns with EGPR (NFC) (PR #226793)
Evgenii Kudriashov via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 27 07:46:47 PDT 2026
https://github.com/e-kud created https://github.com/llvm/llvm-project/pull/226793
The i8 BLSI/BLSMSK patterns always select the VEX forms, so when only extended GPRs (r16-r31) are available the operands get spilled instead of using the EVEX forms.
>From b3834b262496e55640a3e82fdc77b3629bb98eb9 Mon Sep 17 00:00:00 2001
From: Evgenii Kudriashov <evgenii.kudriashov at intel.com>
Date: Sun, 27 Sep 2026 16:41:17 +0200
Subject: [PATCH] [X86][APX] Precommit test for BLSI/BLSMSK i8 patterns with
EGPR (NFC)
The i8 BLSI/BLSMSK patterns always select the VEX forms, so when only
extended GPRs (r16-r31) are available the operands get spilled instead
of using the EVEX forms.
Co-Authored-By: Claude Opus 5.5 (1M context) <noreply at anthropic.com>
---
llvm/test/CodeGen/X86/apx/bls-egpr.ll | 137 ++++++++++++++++++++++++++
1 file changed, 137 insertions(+)
create mode 100644 llvm/test/CodeGen/X86/apx/bls-egpr.ll
diff --git a/llvm/test/CodeGen/X86/apx/bls-egpr.ll b/llvm/test/CodeGen/X86/apx/bls-egpr.ll
new file mode 100644
index 0000000000000..95ffb486f76cf
--- /dev/null
+++ b/llvm/test/CodeGen/X86/apx/bls-egpr.ll
@@ -0,0 +1,137 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+bmi,+egpr --show-mc-encoding | FileCheck %s
+
+; Clobber all legacy GPRs so that the BLS* operands have to live in r16-r31,
+; which requires the EVEX forms of the instructions.
+
+define i8 @blsi8(i8 %x) nounwind {
+; CHECK-LABEL: blsi8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp # encoding: [0x55]
+; CHECK-NEXT: pushq %r15 # encoding: [0x41,0x57]
+; CHECK-NEXT: pushq %r14 # encoding: [0x41,0x56]
+; CHECK-NEXT: pushq %r13 # encoding: [0x41,0x55]
+; CHECK-NEXT: pushq %r12 # encoding: [0x41,0x54]
+; CHECK-NEXT: pushq %rbx # encoding: [0x53]
+; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: # encoding: [0x89,0x7c,0x24,0xfc]
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: blsil {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Folded Reload
+; CHECK-NEXT: # encoding: [0xc4,0xe2,0x78,0xf3,0x5c,0x24,0xfc]
+; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: # encoding: [0x89,0x44,0x24,0xfc]
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; CHECK-NEXT: # encoding: [0x8b,0x44,0x24,0xfc]
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: popq %rbx # encoding: [0x5b]
+; CHECK-NEXT: popq %r12 # encoding: [0x41,0x5c]
+; CHECK-NEXT: popq %r13 # encoding: [0x41,0x5d]
+; CHECK-NEXT: popq %r14 # encoding: [0x41,0x5e]
+; CHECK-NEXT: popq %r15 # encoding: [0x41,0x5f]
+; CHECK-NEXT: popq %rbp # encoding: [0x5d]
+; CHECK-NEXT: retq # encoding: [0xc3]
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+ %neg = sub i8 0, %x
+ %r = and i8 %x, %neg
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+ ret i8 %r
+}
+
+define i32 @blsi32(i32 %x) nounwind {
+; CHECK-LABEL: blsi32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp # encoding: [0x55]
+; CHECK-NEXT: pushq %r15 # encoding: [0x41,0x57]
+; CHECK-NEXT: pushq %r14 # encoding: [0x41,0x56]
+; CHECK-NEXT: pushq %r13 # encoding: [0x41,0x55]
+; CHECK-NEXT: pushq %r12 # encoding: [0x41,0x54]
+; CHECK-NEXT: pushq %rbx # encoding: [0x53]
+; CHECK-NEXT: movl %edi, %r16d # encoding: [0xd5,0x10,0x89,0xf8]
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: blsil %r16d, %r16d # encoding: [0x62,0xfa,0x7c,0x00,0xf3,0xd8]
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl %r16d, %eax # encoding: [0xd5,0x40,0x89,0xc0]
+; CHECK-NEXT: popq %rbx # encoding: [0x5b]
+; CHECK-NEXT: popq %r12 # encoding: [0x41,0x5c]
+; CHECK-NEXT: popq %r13 # encoding: [0x41,0x5d]
+; CHECK-NEXT: popq %r14 # encoding: [0x41,0x5e]
+; CHECK-NEXT: popq %r15 # encoding: [0x41,0x5f]
+; CHECK-NEXT: popq %rbp # encoding: [0x5d]
+; CHECK-NEXT: retq # encoding: [0xc3]
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+ %neg = sub i32 0, %x
+ %r = and i32 %x, %neg
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+ ret i32 %r
+}
+
+define i8 @blsmsk8(i8 %x) nounwind {
+; CHECK-LABEL: blsmsk8:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp # encoding: [0x55]
+; CHECK-NEXT: pushq %r15 # encoding: [0x41,0x57]
+; CHECK-NEXT: pushq %r14 # encoding: [0x41,0x56]
+; CHECK-NEXT: pushq %r13 # encoding: [0x41,0x55]
+; CHECK-NEXT: pushq %r12 # encoding: [0x41,0x54]
+; CHECK-NEXT: pushq %rbx # encoding: [0x53]
+; CHECK-NEXT: movl %edi, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: # encoding: [0x89,0x7c,0x24,0xfc]
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: blsmskl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Folded Reload
+; CHECK-NEXT: # encoding: [0xc4,0xe2,0x78,0xf3,0x54,0x24,0xfc]
+; CHECK-NEXT: movl %eax, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
+; CHECK-NEXT: # encoding: [0x89,0x44,0x24,0xfc]
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl {{[-0-9]+}}(%r{{[sb]}}p), %eax # 4-byte Reload
+; CHECK-NEXT: # encoding: [0x8b,0x44,0x24,0xfc]
+; CHECK-NEXT: # kill: def $al killed $al killed $eax
+; CHECK-NEXT: popq %rbx # encoding: [0x5b]
+; CHECK-NEXT: popq %r12 # encoding: [0x41,0x5c]
+; CHECK-NEXT: popq %r13 # encoding: [0x41,0x5d]
+; CHECK-NEXT: popq %r14 # encoding: [0x41,0x5e]
+; CHECK-NEXT: popq %r15 # encoding: [0x41,0x5f]
+; CHECK-NEXT: popq %rbp # encoding: [0x5d]
+; CHECK-NEXT: retq # encoding: [0xc3]
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+ %y = add i8 %x, -1
+ %r = xor i8 %x, %y
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+ ret i8 %r
+}
+
+define i32 @blsmsk32(i32 %x) nounwind {
+; CHECK-LABEL: blsmsk32:
+; CHECK: # %bb.0:
+; CHECK-NEXT: pushq %rbp # encoding: [0x55]
+; CHECK-NEXT: pushq %r15 # encoding: [0x41,0x57]
+; CHECK-NEXT: pushq %r14 # encoding: [0x41,0x56]
+; CHECK-NEXT: pushq %r13 # encoding: [0x41,0x55]
+; CHECK-NEXT: pushq %r12 # encoding: [0x41,0x54]
+; CHECK-NEXT: pushq %rbx # encoding: [0x53]
+; CHECK-NEXT: movl %edi, %r16d # encoding: [0xd5,0x10,0x89,0xf8]
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: blsmskl %r16d, %r16d # encoding: [0x62,0xfa,0x7c,0x00,0xf3,0xd0]
+; CHECK-NEXT: #APP
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: movl %r16d, %eax # encoding: [0xd5,0x40,0x89,0xc0]
+; CHECK-NEXT: popq %rbx # encoding: [0x5b]
+; CHECK-NEXT: popq %r12 # encoding: [0x41,0x5c]
+; CHECK-NEXT: popq %r13 # encoding: [0x41,0x5d]
+; CHECK-NEXT: popq %r14 # encoding: [0x41,0x5e]
+; CHECK-NEXT: popq %r15 # encoding: [0x41,0x5f]
+; CHECK-NEXT: popq %rbp # encoding: [0x5d]
+; CHECK-NEXT: retq # encoding: [0xc3]
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+ %y = add i32 %x, -1
+ %r = xor i32 %x, %y
+ call void asm sideeffect "", "~{rax},~{rbx},~{rcx},~{rdx},~{rsi},~{rdi},~{rbp},~{r8},~{r9},~{r10},~{r11},~{r12},~{r13},~{r14},~{r15}"()
+ ret i32 %r
+}
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