[llvm] [MISched] Extract `SUnit::printNodeNum`(NFC) (PR #226785)
Tomer Shafir via llvm-commits
llvm-commits at lists.llvm.org
Sun Sep 27 06:29:14 PDT 2026
https://github.com/tomershafir created https://github.com/llvm/llvm-project/pull/226785
Establish a consistent API for printing a SUnit, rather than a scattered duplication.
>From 818345a40466e13f3c79d5e0cebf1b0a7e01d880 Mon Sep 17 00:00:00 2001
From: tomershafir <tomer.shafir8 at gmail.com>
Date: Sun, 27 Sep 2026 16:26:41 +0300
Subject: [PATCH] [MISched] Extract `SUnit::printNodeNum`(NFC)
Establish a consistent API for printing a SUnit, rather than a scattered duplication.
---
llvm/include/llvm/CodeGen/ScheduleDAG.h | 3 +
llvm/lib/CodeGen/MachinePipeliner.cpp | 15 ++--
llvm/lib/CodeGen/MachineScheduler.cpp | 72 +++++++++----------
llvm/lib/CodeGen/MacroFusion.cpp | 2 +-
llvm/lib/CodeGen/ScheduleDAG.cpp | 8 ++-
llvm/lib/CodeGen/ScheduleDAGInstrs.cpp | 6 +-
.../SelectionDAG/ScheduleDAGRRList.cpp | 37 +++++-----
.../SelectionDAG/SelectionDAGPrinter.cpp | 2 +-
.../AMDGPU/AMDGPUCoExecSchedStrategy.cpp | 4 +-
llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp | 10 +--
llvm/lib/Target/AMDGPU/GCNILPSched.cpp | 6 +-
llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp | 12 ++--
llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp | 2 +-
llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp | 18 ++---
llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp | 4 +-
.../Target/RISCV/RISCVMachineScheduler.cpp | 2 +-
.../SystemZ/SystemZHazardRecognizer.cpp | 2 +-
.../SystemZ/SystemZMachineScheduler.cpp | 2 +-
18 files changed, 108 insertions(+), 99 deletions(-)
diff --git a/llvm/include/llvm/CodeGen/ScheduleDAG.h b/llvm/include/llvm/CodeGen/ScheduleDAG.h
index 4638632815971..9c9de22fcf1e0 100644
--- a/llvm/include/llvm/CodeGen/ScheduleDAG.h
+++ b/llvm/include/llvm/CodeGen/ScheduleDAG.h
@@ -24,6 +24,7 @@
#include "llvm/CodeGen/TargetLowering.h"
#include "llvm/Support/Compiler.h"
#include "llvm/Support/ErrorHandling.h"
+#include "llvm/Support/Printable.h"
#include <cassert>
#include <cstddef>
#include <iterator>
@@ -486,6 +487,8 @@ class TargetRegisterInfo;
LLVM_ABI void dumpAttributes() const;
+ LLVM_ABI Printable printNum() const;
+
private:
LLVM_ABI void ComputeDepth();
LLVM_ABI void ComputeHeight();
diff --git a/llvm/lib/CodeGen/MachinePipeliner.cpp b/llvm/lib/CodeGen/MachinePipeliner.cpp
index ef21f32af9067..6bc8f0d72e16c 100644
--- a/llvm/lib/CodeGen/MachinePipeliner.cpp
+++ b/llvm/lib/CodeGen/MachinePipeliner.cpp
@@ -2513,7 +2513,7 @@ void SwingSchedulerDAG::registerPressureFilter(NodeSetType &NodeSets) {
RecRegPressure.MaxSetPressure);
if (RPDelta.Excess.isValid()) {
LLVM_DEBUG(
- dbgs() << "Excess register pressure: SU(" << SU->NodeNum << ") "
+ dbgs() << "Excess register pressure: " << SU->printNum() << " "
<< TRI->getRegPressureSetName(RPDelta.Excess.getPSet())
<< ":" << RPDelta.Excess.getUnitInc() << "\n");
NS.setExceedPressure(SU);
@@ -3681,8 +3681,8 @@ bool SMSchedule::normalizeNonPipelinedInstructions(
auto &OldS = getInstructions(OldCycle);
llvm::erase(OldS, &SU);
getInstructions(NewCycle).emplace_back(&SU);
- LLVM_DEBUG(dbgs() << "SU(" << SU.NodeNum
- << ") is not pipelined; moving from cycle " << OldCycle
+ LLVM_DEBUG(dbgs() << SU.printNum()
+ << " is not pipelined; moving from cycle " << OldCycle
<< " to " << NewCycle << " Instr:" << *SU.getInstr());
}
@@ -3951,7 +3951,7 @@ void NodeSet::print(raw_ostream &os) const {
os << "Num nodes " << size() << " rec " << RecMII << " mov " << MaxMOV
<< " depth " << MaxDepth << " col " << Colocate << "\n";
for (const auto &I : Nodes)
- os << " SU(" << I->NodeNum << ") " << *(I->getInstr());
+ os << " " << I->printNum() << " " << *(I->getInstr());
os << "\n";
}
@@ -4480,9 +4480,10 @@ void LoopCarriedEdges::dump(SUnit *SU, const TargetRegisterInfo *TRI,
return;
const auto DumpSU = [](const SUnit *SU) {
- std::ostringstream OSS;
- OSS << "SU(" << SU->NodeNum << ")";
- return OSS.str();
+ std::string S;
+ raw_string_ostream OS(S);
+ OS << SU->printNum();
+ return S;
};
dbgs() << " Loop carried edges from " << DumpSU(SU) << "\n"
diff --git a/llvm/lib/CodeGen/MachineScheduler.cpp b/llvm/lib/CodeGen/MachineScheduler.cpp
index c66b9d2914eda..8ccfed498e6ce 100644
--- a/llvm/lib/CodeGen/MachineScheduler.cpp
+++ b/llvm/lib/CodeGen/MachineScheduler.cpp
@@ -1606,7 +1606,7 @@ void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
return Change.isValid();
}))
LLVM_DEBUG(dbgs()
- << " UpdateRegPressure: SU(" << SU.NodeNum << ") "
+ << " UpdateRegPressure: " << SU.printNum() << " "
<< printReg(Reg, TRI) << ':'
<< PrintLaneMask(P.LaneMask) << ' ' << *SU.getInstr();
dbgs() << " to "; PDiff.dump(*TRI););
@@ -1644,8 +1644,8 @@ void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
if (llvm::any_of(PDiff, [](const PressureChange &Change) {
return Change.isValid();
}))
- LLVM_DEBUG(dbgs() << " UpdateRegPressure: SU(" << SU->NodeNum
- << ") " << *SU->getInstr();
+ LLVM_DEBUG(dbgs() << " UpdateRegPressure: " << SU->printNum()
+ << " " << *SU->getInstr();
dbgs() << " to ";
PDiff.dump(*TRI););
}
@@ -1857,8 +1857,8 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
} else
CyclicLatency = 0;
- LLVM_DEBUG(dbgs() << "Cyclic Path: SU(" << DefSU->NodeNum << ") -> SU("
- << SU->NodeNum << ") = " << CyclicLatency << "c\n");
+ LLVM_DEBUG(dbgs() << "Cyclic Path: " << DefSU->printNum() << " -> "
+ << SU->printNum() << " = " << CyclicLatency << "c\n");
if (CyclicLatency > MaxCyclicLatency)
MaxCyclicLatency = CyclicLatency;
}
@@ -2144,8 +2144,8 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
continue;
Clusters.unionSets(SUa, SUb);
- LLVM_DEBUG(dbgs() << "Cluster ld/st SU(" << SUa->NodeNum << ") - SU("
- << SUb->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << "Cluster ld/st " << SUa->printNum() << " - "
+ << SUb->printNum() << "\n");
++NumClustered;
if (IsLoad) {
@@ -2170,8 +2170,8 @@ void BaseMemOpClusterMutation::clusterNeighboringMemOps(
for (const SDep &Pred : SUb->Preds) {
if (Pred.getSUnit() == SUa)
continue;
- LLVM_DEBUG(dbgs() << " Copy Pred SU(" << Pred.getSUnit()->NodeNum
- << ")\n");
+ LLVM_DEBUG(dbgs() << " Copy Pred " << Pred.getSUnit()->printNum()
+ << "\n");
DAG->addEdge(SUa, SDep(Pred.getSUnit(), SDep::Artificial));
}
}
@@ -2447,7 +2447,7 @@ void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
return;
GlobalUses.push_back(Pred.getSUnit());
}
- LLVM_DEBUG(dbgs() << "Constraining copy SU(" << CopySU->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << "Constraining copy " << CopySU->printNum() << "\n");
// Add the weak edges.
for (SUnit *LU : LocalUses) {
LLVM_DEBUG(dbgs() << " Local use SU(" << LU->NodeNum << ") -> SU("
@@ -2455,8 +2455,8 @@ void CopyConstrain::constrainLocalCopy(SUnit *CopySU, ScheduleDAGMILive *DAG) {
DAG->addEdge(GlobalSU, SDep(LU, SDep::Weak));
}
for (SUnit *GU : GlobalUses) {
- LLVM_DEBUG(dbgs() << " Global use SU(" << GU->NodeNum << ") -> SU("
- << FirstLocalSU->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << " Global use " << GU->printNum() << " -> "
+ << FirstLocalSU->printNum() << "\n");
DAG->addEdge(FirstLocalSU, SDep(GU, SDep::Weak));
}
}
@@ -2717,13 +2717,13 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
if (HazardRec->isEnabled()
&& HazardRec->getHazardType(SU) != ScheduleHazardRecognizer::NoHazard) {
LLVM_DEBUG(dbgs().indent(2)
- << "hazard: SU(" << SU->NodeNum << ") reported by HazardRec\n");
+ << "hazard: " << SU->printNum() << " reported by HazardRec\n");
return true;
}
unsigned uops = SchedModel->getNumMicroOps(SU->getInstr());
if ((CurrMOps > 0) && (CurrMOps + uops > SchedModel->getIssueWidth())) {
- LLVM_DEBUG(dbgs().indent(2) << "hazard: SU(" << SU->NodeNum << ") uops="
+ LLVM_DEBUG(dbgs().indent(2) << "hazard: " << SU->printNum() << " uops="
<< uops << ", CurrMOps = " << CurrMOps << ", "
<< "CurrMOps + uops > issue width of "
<< SchedModel->getIssueWidth() << "\n");
@@ -2733,7 +2733,7 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
if (CurrMOps > 0 &&
((isTop() && SchedModel->mustBeginGroup(SU->getInstr())) ||
(!isTop() && SchedModel->mustEndGroup(SU->getInstr())))) {
- LLVM_DEBUG(dbgs().indent(2) << "hazard: SU(" << SU->NodeNum << ") must "
+ LLVM_DEBUG(dbgs().indent(2) << "hazard: " << SU->printNum() << " must "
<< (isTop() ? "begin" : "end") << " group\n");
return true;
}
@@ -2754,7 +2754,7 @@ bool SchedBoundary::checkHazard(SUnit *SU) {
MaxObservedStall = std::max(ReleaseAtCycle, MaxObservedStall);
#endif
LLVM_DEBUG(dbgs().indent(2)
- << "hazard: SU(" << SU->NodeNum << ") "
+ << "hazard: " << SU->printNum() << " "
<< SchedModel->getResourceName(ResIdx) << '['
<< InstanceIdx - ReservedCyclesIndex[ResIdx] << ']' << "="
<< NRCycle << "c, is later than "
@@ -2779,8 +2779,8 @@ findMaxLatency(ArrayRef<SUnit*> ReadySUs) {
}
}
if (LateSU) {
- LLVM_DEBUG(dbgs() << Available.getName() << " RemLatency SU("
- << LateSU->NodeNum << ") " << RemLatency << "c\n");
+ LLVM_DEBUG(dbgs() << Available.getName() << " RemLatency "
+ << LateSU->printNum() << " " << RemLatency << "c\n");
}
return RemLatency;
}
@@ -2835,10 +2835,10 @@ void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle, bool InPQueue,
bool IsBuffered = SchedModel->getMicroOpBufferSize() != 0;
bool HazardDetected = !IsBuffered && ReadyCycle > CurrCycle;
if (HazardDetected)
- LLVM_DEBUG(dbgs().indent(2) << "hazard: SU(" << SU->NodeNum
- << ") ReadyCycle = " << ReadyCycle
- << " is later than CurrCycle = " << CurrCycle
- << " on an unbuffered resource" << "\n");
+ LLVM_DEBUG(dbgs().indent(2)
+ << "hazard: " << SU->printNum() << " ReadyCycle = " << ReadyCycle
+ << " is later than CurrCycle = " << CurrCycle
+ << " on an unbuffered resource" << "\n");
else
HazardDetected = checkHazard(SU);
@@ -2851,7 +2851,7 @@ void SchedBoundary::releaseNode(SUnit *SU, unsigned ReadyCycle, bool InPQueue,
if (!HazardDetected) {
Available.push(SU);
LLVM_DEBUG(dbgs().indent(2)
- << "Move SU(" << SU->NodeNum << ") into Available Q\n");
+ << "Move " << SU->printNum() << " into Available Q\n");
if (InPQueue)
Pending.remove(Pending.begin() + Idx);
@@ -3063,13 +3063,13 @@ void SchedBoundary::bumpNode(SUnit *SU) {
unsigned &BotLatency = isTop() ? DependentLatency : ExpectedLatency;
if (SU->getDepth() > TopLatency) {
TopLatency = SU->getDepth();
- LLVM_DEBUG(dbgs() << " " << Available.getName() << " TopLatency SU("
- << SU->NodeNum << ") " << TopLatency << "c\n");
+ LLVM_DEBUG(dbgs() << " " << Available.getName() << " TopLatency "
+ << SU->printNum() << " " << TopLatency << "c\n");
}
if (SU->getHeight() > BotLatency) {
BotLatency = SU->getHeight();
- LLVM_DEBUG(dbgs() << " " << Available.getName() << " BotLatency SU("
- << SU->NodeNum << ") " << BotLatency << "c\n");
+ LLVM_DEBUG(dbgs() << " " << Available.getName() << " BotLatency "
+ << SU->printNum() << " " << BotLatency << "c\n");
}
// If we stall for any reason, bump the cycle.
if (NextCycle > CurrCycle)
@@ -3131,7 +3131,7 @@ void SchedBoundary::releasePending() {
SUnit *SU = *(Pending.begin() + I);
unsigned ReadyCycle = isTop() ? SU->TopReadyCycle : SU->BotReadyCycle;
- LLVM_DEBUG(dbgs() << "Checking pending node SU(" << SU->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << "Checking pending node " << SU->printNum() << "\n");
if (ReadyCycle < MinReadyCycle)
MinReadyCycle = ReadyCycle;
@@ -3407,7 +3407,8 @@ void GenericSchedulerBase::traceCandidate(const SchedCandidate &Cand) {
Latency = Cand.SU->getDepth();
break;
}
- dbgs() << " Cand SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
+ dbgs() << " Cand " << Cand.SU->printNum() << " "
+ << getReasonStr(Cand.Reason);
if (P.isValid())
dbgs() << " " << TRI->getRegPressureSetName(P.getPSet())
<< ":" << P.getUnitInc() << " ";
@@ -3522,8 +3523,8 @@ static void tracePick(const SUnit *SU,
const GenericSchedulerBase::CandReason Reason,
const bool IsTop, const bool IsPostRA = false) {
assert(SU && "SU must not be null for tracing");
- LLVM_DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ") << "Cand SU("
- << SU->NodeNum << ") "
+ LLVM_DEBUG(dbgs() << "Pick " << (IsTop ? "Top " : "Bot ") << "Cand "
+ << SU->printNum() << " "
<< GenericSchedulerBase::getReasonStr(Reason) << " ["
<< (IsPostRA ? "post-RA" : "pre-RA") << "]\n");
@@ -3946,7 +3947,7 @@ void GenericScheduler::initCandidate(SchedCandidate &Cand, SUnit *SU,
}
}
LLVM_DEBUG(if (Cand.RPDelta.Excess.isValid()) dbgs()
- << " Try SU(" << Cand.SU->NodeNum << ") "
+ << " Try " << Cand.SU->printNum() << " "
<< TRI->getRegPressureSetName(Cand.RPDelta.Excess.getPSet()) << ":"
<< Cand.RPDelta.Excess.getUnitInc() << "\n");
}
@@ -4235,7 +4236,7 @@ SUnit *GenericScheduler::pickNode(bool &IsTopNode) {
if (SU->isBottomReady())
Bot.removeReady(SU);
- LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
+ LLVM_DEBUG(dbgs() << "Scheduling " << SU->printNum() << " "
<< *SU->getInstr());
if (IsTopNode) {
@@ -4594,7 +4595,7 @@ SUnit *PostGenericScheduler::pickNode(bool &IsTopNode) {
if (SU->isBottomReady())
Bot.removeReady(SU);
- LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
+ LLVM_DEBUG(dbgs() << "Scheduling " << SU->printNum() << " "
<< *SU->getInstr());
if (IsTopNode) {
@@ -4698,8 +4699,7 @@ class ILPScheduler : public MachineSchedStrategy {
SUnit *SU = ReadyQ.back();
ReadyQ.pop_back();
IsTopNode = false;
- LLVM_DEBUG(dbgs() << "Pick node "
- << "SU(" << SU->NodeNum << ") "
+ LLVM_DEBUG(dbgs() << "Pick node " << SU->printNum() << " "
<< " ILP: " << DAG->getDFSResult()->getILP(SU)
<< " Tree: " << DAG->getDFSResult()->getSubtreeID(SU)
<< " @"
diff --git a/llvm/lib/CodeGen/MacroFusion.cpp b/llvm/lib/CodeGen/MacroFusion.cpp
index 9194c14335fa5..fa31b95f3b696 100644
--- a/llvm/lib/CodeGen/MacroFusion.cpp
+++ b/llvm/lib/CodeGen/MacroFusion.cpp
@@ -67,7 +67,7 @@ bool llvm::fuseInstructionPair(ScheduleDAGInstrs &DAG, SUnit &FirstSU,
dbgs() << "Fusion conflict: cannot fuse SU(" << FirstSU.NodeNum
<< ") and SU(" << SecondSU.NodeNum << ")\n";
if (FirstSU.isClustered())
- dbgs() << " SU(" << FirstSU.NodeNum << ") already clustered\n";
+ dbgs() << " " << FirstSU.printNum() << " already clustered\n";
if (SecondSU.isClustered())
dbgs() << " SU(" << SecondSU.NodeNum << ") already clustered\n";
});
diff --git a/llvm/lib/CodeGen/ScheduleDAG.cpp b/llvm/lib/CodeGen/ScheduleDAG.cpp
index c621fef7c1e0c..612f6ae1a5d87 100644
--- a/llvm/lib/CodeGen/ScheduleDAG.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAG.cpp
@@ -335,6 +335,12 @@ void SUnit::biasCriticalPath() {
std::swap(*Preds.begin(), *BestI);
}
+Printable SUnit::printNum() const {
+ assert(!isBoundaryNode() &&
+ "use ScheduleDAG::dumpNodeName for boundary nodes");
+ return Printable([this](raw_ostream &OS) { OS << "SU(" << NodeNum << ")"; });
+}
+
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
LLVM_DUMP_METHOD void SUnit::dumpAttributes() const {
dbgs() << " # preds left : " << NumPredsLeft << "\n";
@@ -355,7 +361,7 @@ LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeName(const SUnit &SU) const {
else if (&SU == &ExitSU)
dbgs() << "ExitSU";
else
- dbgs() << "SU(" << SU.NodeNum << ")";
+ dbgs() << SU.printNum();
}
LLVM_DUMP_METHOD void ScheduleDAG::dumpNodeAll(const SUnit &SU) const {
diff --git a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
index 6f42de464cb5b..e9fcb289a7a38 100644
--- a/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
+++ b/llvm/lib/CodeGen/ScheduleDAGInstrs.cpp
@@ -99,7 +99,7 @@ static void dumpSUList(const ScheduleDAGInstrs::SUList &L) {
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
dbgs() << "{ ";
for (const SUnit *SU : L) {
- dbgs() << "SU(" << SU->NodeNum << ")";
+ dbgs() << SU->printNum();
if (SU != L.back())
dbgs() << ", ";
}
@@ -880,8 +880,8 @@ void ScheduleDAGInstrs::buildSchedGraph(AAResults *AA,
BarrierChain->addPredBarrier(SU);
BarrierChain = SU;
- LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: SU("
- << BarrierChain->NodeNum << ").\n");
+ LLVM_DEBUG(dbgs() << "Global memory object and new barrier chain: "
+ << BarrierChain->printNum() << ".\n");
// Add dependencies against everything below it and clear maps.
addBarrierChain(Stores);
diff --git a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
index 520fe43a8cfc2..6f15b88fb959f 100644
--- a/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp
@@ -1498,8 +1498,8 @@ SUnit *ScheduleDAGRRList::PickNodeToScheduleBottomUp() {
if (!BtSU->isPending)
AvailableQueue->remove(BtSU);
}
- LLVM_DEBUG(dbgs() << "ARTIFICIAL edge from SU(" << BtSU->NodeNum
- << ") to SU(" << TrySU->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << "ARTIFICIAL edge from " << BtSU->printNum() << " to "
+ << TrySU->printNum() << "\n");
AddPredQueued(TrySU, SDep(BtSU, SDep::Artificial));
// If one or more successors has been unscheduled, then the current
@@ -2205,8 +2205,7 @@ void RegReductionPQBase::scheduledNode(SUnit *SU) {
if (RegPressure[RCId] < Cost) {
// Register pressure tracking is imprecise. This can happen. But we try
// hard not to let it happen because it likely results in poor scheduling.
- LLVM_DEBUG(dbgs() << " SU(" << SU->NodeNum
- << ") has too many regdefs\n");
+ LLVM_DEBUG(dbgs() << " " << SU->printNum() << " has too many regdefs\n");
RegPressure[RCId] = 0;
}
else {
@@ -2397,7 +2396,7 @@ static void initVRegCycle(SUnit *SU) {
if (!hasOnlyLiveInOpers(SU) || !hasOnlyLiveOutUses(SU))
return;
- LLVM_DEBUG(dbgs() << "VRegCycle: SU(" << SU->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << "VRegCycle: " << SU->printNum() << "\n");
SU->isVRegCycle = true;
@@ -2520,8 +2519,8 @@ static bool BURRSort(SUnit *left, SUnit *right, RegReductionPQBase *SPQ) {
" defines a physreg" };
#endif
LLVM_DEBUG(dbgs() << " SU (" << left->NodeNum << ") "
- << PhysRegMsg[LHasPhysReg] << " SU(" << right->NodeNum
- << ") " << PhysRegMsg[RHasPhysReg] << "\n");
+ << PhysRegMsg[LHasPhysReg] << " " << right->printNum()
+ << " " << PhysRegMsg[RHasPhysReg] << "\n");
return LHasPhysReg < RHasPhysReg;
}
}
@@ -2665,13 +2664,13 @@ bool hybrid_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
// Avoid causing spills. If register pressure is high, schedule for
// register pressure reduction.
if (LHigh && !RHigh) {
- LLVM_DEBUG(dbgs() << " pressure SU(" << left->NodeNum << ") > SU("
- << right->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << " pressure " << left->printNum() << " > "
+ << right->printNum() << "\n");
return true;
}
else if (!LHigh && RHigh) {
- LLVM_DEBUG(dbgs() << " pressure SU(" << right->NodeNum << ") > SU("
- << left->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << " pressure " << right->printNum() << " > "
+ << left->printNum() << "\n");
return false;
}
if (!LHigh && !RHigh) {
@@ -2733,9 +2732,9 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
RPDiff = SPQ->RegPressureDiff(right, RLiveUses);
}
if (!DisableSchedRegPressure && LPDiff != RPDiff) {
- LLVM_DEBUG(dbgs() << "RegPressureDiff SU(" << left->NodeNum
- << "): " << LPDiff << " != SU(" << right->NodeNum
- << "): " << RPDiff << "\n");
+ LLVM_DEBUG(dbgs() << "RegPressureDiff " << left->printNum() << ": "
+ << LPDiff << " != " << right->printNum() << ": " << RPDiff
+ << "\n");
return LPDiff > RPDiff;
}
@@ -2747,8 +2746,8 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
}
if (!DisableSchedLiveUses && (LLiveUses != RLiveUses)) {
- LLVM_DEBUG(dbgs() << "Live uses SU(" << left->NodeNum << "): " << LLiveUses
- << " != SU(" << right->NodeNum << "): " << RLiveUses
+ LLVM_DEBUG(dbgs() << "Live uses " << left->printNum() << ": " << LLiveUses
+ << " != " << right->printNum() << ": " << RLiveUses
<< "\n");
return LLiveUses < RLiveUses;
}
@@ -2763,9 +2762,9 @@ bool ilp_ls_rr_sort::operator()(SUnit *left, SUnit *right) const {
if (!DisableSchedCriticalPath) {
int spread = (int)left->getDepth() - (int)right->getDepth();
if (std::abs(spread) > MaxReorderWindow) {
- LLVM_DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
- << left->getDepth() << " != SU(" << right->NodeNum
- << "): " << right->getDepth() << "\n");
+ LLVM_DEBUG(dbgs() << "Depth of " << left->printNum() << ": "
+ << left->getDepth() << " != " << right->printNum()
+ << ": " << right->getDepth() << "\n");
return left->getDepth() < right->getDepth();
}
}
diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
index ac28f62894788..25a7a232a9e0d 100644
--- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp
@@ -284,7 +284,7 @@ void SelectionDAG::setSubgraphColor(SDNode *N, const char *Color) {
std::string ScheduleDAGSDNodes::getGraphNodeLabel(const SUnit *SU) const {
std::string s;
raw_string_ostream O(s);
- O << "SU(" << SU->NodeNum << "): ";
+ O << SU->printNum() << ": ";
if (SU->getNode()) {
SmallVector<SDNode *, 4> GluedNodes;
for (SDNode *N = SU->getNode(); N; N = N->getGluedNode())
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
index 1f3905a0465e4..bd2efec0a6338 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUCoExecSchedStrategy.cpp
@@ -875,7 +875,7 @@ SUnit *AMDGPUCoExecSchedStrategy::pickNode(bool &IsTopNode) {
if (SU->isBottomReady())
Bot.removeReady(SU);
- LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
+ LLVM_DEBUG(dbgs() << "Scheduling " << SU->printNum() << " "
<< *SU->getInstr());
assert(IsTopNode && "coexec scheduler must only schedule from top boundary");
@@ -942,7 +942,7 @@ void AMDGPUCoExecSchedStrategy::dumpPickSummary(SUnit *SU, bool IsTopNode,
dbgs() << "=== Pick @ Cycle " << Cycle << " ===\n";
const InstructionFlavor Flavor = classifyFlavor(*SU->getInstr(), *SII);
- dbgs() << "Picked: SU(" << SU->NodeNum << ") ";
+ dbgs() << "Picked: " << SU->printNum() << " ";
SU->getInstr()->print(dbgs(), /*IsStandalone=*/true, /*SkipOpers=*/false,
/*SkipDebugLoc=*/true);
dbgs() << " [" << getFlavorName(Flavor) << "]\n";
diff --git a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
index b60e5c30855d2..866cfd47fb381 100644
--- a/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
+++ b/llvm/lib/Target/AMDGPU/AMDGPUIGroupLP.cpp
@@ -453,7 +453,7 @@ void PipelineSolver::makePipeline() {
for (auto &SU : SG.Collection) {
if (SU->getInstr()->getOpcode() == AMDGPU::SCHED_GROUP_BARRIER)
SGBarr = SU;
- LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << SU->printNum() << "\n");
}
// Command line requested IGroupLP doesn't have SGBarr
if (!SGBarr)
@@ -721,8 +721,8 @@ bool PipelineSolver::solveExact() {
assert(static_cast<size_t>(CurrConflInstNo) <
PipelineInstrs[CurrSyncGroupIdx].size());
SUToCandSGsPair CurrSU = PipelineInstrs[CurrSyncGroupIdx][CurrConflInstNo];
- LLVM_DEBUG(dbgs() << "Fitting SU(" << CurrSU.first->NodeNum
- << ") in Pipeline # " << CurrSyncGroupIdx << "\n");
+ LLVM_DEBUG(dbgs() << "Fitting " << CurrSU.first->printNum()
+ << " in Pipeline # " << CurrSyncGroupIdx << "\n");
// SchedGroup -> Cost pairs
SmallVector<std::pair<int, int>, 4> ReadyList;
@@ -820,8 +820,8 @@ void PipelineSolver::greedyFind(
std::optional<GroupInfo> Best;
auto &SyncPipeline = CurrPipeline[CurrSyncGroupIdx];
- LLVM_DEBUG(dbgs() << "Fitting SU(" << CurrSU.first->NodeNum
- << ") in Pipeline # " << CurrSyncGroupIdx << "\n");
+ LLVM_DEBUG(dbgs() << "Fitting " << CurrSU.first->printNum()
+ << " in Pipeline # " << CurrSyncGroupIdx << "\n");
EdgeSetBuilder Builder(CurrSU.first, SyncPipeline, IsBottomUp);
diff --git a/llvm/lib/Target/AMDGPU/GCNILPSched.cpp b/llvm/lib/Target/AMDGPU/GCNILPSched.cpp
index 79b4a68c6a44e..c2d510ec3aae3 100644
--- a/llvm/lib/Target/AMDGPU/GCNILPSched.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNILPSched.cpp
@@ -168,9 +168,9 @@ const SUnit *GCNILPScheduler::pickBest(const SUnit *left, const SUnit *right)
if (!DisableSchedCriticalPath) {
int spread = (int)left->getDepth() - (int)right->getDepth();
if (std::abs(spread) > MaxReorderWindow) {
- LLVM_DEBUG(dbgs() << "Depth of SU(" << left->NodeNum << "): "
- << left->getDepth() << " != SU(" << right->NodeNum
- << "): " << right->getDepth() << "\n");
+ LLVM_DEBUG(dbgs() << "Depth of " << left->printNum() << ": "
+ << left->getDepth() << " != " << right->printNum()
+ << ": " << right->getDepth() << "\n");
return left->getDepth() < right->getDepth() ? right : left;
}
}
diff --git a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
index 4154f946de8ff..6f27ad59b2415 100644
--- a/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNMinRegStrategy.cpp
@@ -145,8 +145,8 @@ GCNMinRegScheduler::Candidate* GCNMinRegScheduler::pickCandidate() {
Num = findMax(Num, [=](const Candidate &C) {
const auto *SU = C.SU;
int Res = getNotReadySuccessors(SU);
- LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << ") would left non-ready "
- << Res << " successors, metric = " << -Res << '\n');
+ LLVM_DEBUG(dbgs() << SU->printNum() << " would left non-ready " << Res
+ << " successors, metric = " << -Res << '\n');
return -Res;
});
if (Num == 1) break;
@@ -156,7 +156,7 @@ GCNMinRegScheduler::Candidate* GCNMinRegScheduler::pickCandidate() {
Num = findMax(Num, [=](const Candidate &C) {
const auto *SU = C.SU;
auto Res = getReadySuccessors(SU);
- LLVM_DEBUG(dbgs() << "SU(" << SU->NodeNum << ") would make ready " << Res
+ LLVM_DEBUG(dbgs() << SU->printNum() << " would make ready " << Res
<< " successors, metric = " << Res << '\n');
return Res;
});
@@ -198,13 +198,13 @@ void GCNMinRegScheduler::bumpPredsPriority(const SUnit *SchedSU, int Priority) {
Worklist.push_back(P.getSUnit());
}
}
- LLVM_DEBUG(dbgs() << "Make the predecessors of SU(" << SchedSU->NodeNum
- << ")'s non-ready successors of " << Priority
+ LLVM_DEBUG(dbgs() << "Make the predecessors of " << SchedSU->printNum()
+ << "'s non-ready successors of " << Priority
<< " priority in ready queue: ");
for (auto &C : RQ) {
if (Set.count(C.SU)) {
C.Priority = Priority;
- LLVM_DEBUG(dbgs() << " SU(" << C.SU->NodeNum << ')');
+ LLVM_DEBUG(dbgs() << ' ' << C.SU->printNum());
}
}
LLVM_DEBUG(dbgs() << '\n');
diff --git a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
index 56f2a86ff8cb2..27ada09770d04 100644
--- a/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNSchedStrategy.cpp
@@ -734,7 +734,7 @@ SUnit *GCNSchedStrategy::pickNode(bool &IsTopNode) {
if (SU->isBottomReady())
Bot.removeReady(SU);
- LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
+ LLVM_DEBUG(dbgs() << "Scheduling " << SU->printNum() << " "
<< *SU->getInstr());
return SU;
}
diff --git a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
index 3def256f07f78..2f53e65e95040 100644
--- a/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
+++ b/llvm/lib/Target/AMDGPU/GCNVOPDUtils.cpp
@@ -399,19 +399,19 @@ static bool loadsMayOverlap(
for (SUnit *JLoad : JLoadPreds) {
if (ILoad == JLoad) {
LLVM_DEBUG(
- dbgs() << "Will not pair SU(" << I.NodeNum << ") with SU("
- << J.NodeNum << ")\n"
- << " Fusion would introduce a cyclic dependency with SU("
- << ILoad->NodeNum << ")\n");
+ dbgs() << "Will not pair " << I.printNum() << " with "
+ << J.printNum() << "\n"
+ << " Fusion would introduce a cyclic dependency with "
+ << ILoad->printNum() << "\n");
return true;
}
if (!ILoadDeps.contains(JLoad)) {
- LLVM_DEBUG(dbgs() << "Will not pair SU(" << I.NodeNum << ") with SU("
- << J.NodeNum << ")\n"
- << " Fusion may force SU(" << JLoad->NodeNum
- << ") to complete its load before dispatching SU("
- << ILoad->NodeNum << ")\n");
+ LLVM_DEBUG(dbgs() << "Will not pair " << I.printNum() << " with "
+ << J.printNum() << "\n"
+ << " Fusion may force " << JLoad->printNum()
+ << " to complete its load before dispatching "
+ << ILoad->printNum() << "\n");
return true;
}
}
diff --git a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
index 408fe8c49e1f5..c3655921bebae 100644
--- a/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
+++ b/llvm/lib/Target/AMDGPU/SIMachineScheduler.cpp
@@ -180,7 +180,7 @@ void SIScheduleBlock::addUnit(SUnit *SU) {
#ifndef NDEBUG
void SIScheduleBlock::traceCandidate(const SISchedCandidate &Cand) {
- dbgs() << " SU(" << Cand.SU->NodeNum << ") " << getReasonStr(Cand.Reason);
+ dbgs() << " " << Cand.SU->printNum() << " " << getReasonStr(Cand.Reason);
dbgs() << '\n';
}
#endif
@@ -1975,7 +1975,7 @@ void SIScheduleDAGMI::schedule()
scheduleMI(SU, true);
- LLVM_DEBUG(dbgs() << "Scheduling SU(" << SU->NodeNum << ") "
+ LLVM_DEBUG(dbgs() << "Scheduling " << SU->printNum() << " "
<< *SU->getInstr());
}
diff --git a/llvm/lib/Target/RISCV/RISCVMachineScheduler.cpp b/llvm/lib/Target/RISCV/RISCVMachineScheduler.cpp
index c9285721d8544..d8200ba5d392d 100644
--- a/llvm/lib/Target/RISCV/RISCVMachineScheduler.cpp
+++ b/llvm/lib/Target/RISCV/RISCVMachineScheduler.cpp
@@ -205,7 +205,7 @@ void RISCVPreRAMachineSchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
LLVM_DEBUG({
dbgs() << "Previous scheduled Unit: \n";
dbgs() << " IsTop: " << IsTopNode << "\n";
- dbgs() << " SU(" << SU->NodeNum << ") - ";
+ dbgs() << " " << SU->printNum() << " - ";
MI->dump();
dbgs() << " \n";
Info.dump();
diff --git a/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp b/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp
index 8fc339f59e60a..d7c11097cfe9f 100644
--- a/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZHazardRecognizer.cpp
@@ -163,7 +163,7 @@ void SystemZHazardRecognizer::nextGroup() {
#ifndef NDEBUG // Debug output
void SystemZHazardRecognizer::dumpSU(SUnit *SU, raw_ostream &OS) const {
- OS << "SU(" << SU->NodeNum << "):";
+ OS << SU->printNum() << ":";
OS << TII->getName(SU->getInstr()->getOpcode());
const MCSchedClassDesc *SC = getSchedClass(SU);
diff --git a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
index 606273a5e0df8..d41819488e248 100644
--- a/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZMachineScheduler.cpp
@@ -392,7 +392,7 @@ operator<(const Candidate &other) {
}
void SystemZPostRASchedStrategy::schedNode(SUnit *SU, bool IsTopNode) {
- LLVM_DEBUG(dbgs() << "** Scheduling SU(" << SU->NodeNum << ") ";
+ LLVM_DEBUG(dbgs() << "** Scheduling " << SU->printNum() << " ";
if (Available.size() == 1) dbgs() << "(only one) ";
Candidate c(SU, *HazardRec); c.dumpCosts(); dbgs() << "\n";);
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