[llvm] [LSR] Return null from `getExactSDiv` for a zero divisor (PR #226703)

[Akash Manna via llvm-commits]

https://github.com/akash-manna-sky updated https://github.com/llvm/llvm-project/pull/226703

>From a6b7df98cc1ae7bbcc3e414646090316dcafa127 Mon Sep 17 00:00:00 2001
From: Akash Manna <akash.manna.mymail at gmail.com>
Date: Sat, 26 Sep 2026 19:49:58 +0530
Subject: [PATCH] [LSR] Return null from getExactSDiv for a zero divisor

CollectInterestingTypesAndFactors sign-extends the strides of narrower
IVs before pairing them with wider ones, and SCEV can fold that
extension to a constant zero when the narrow stride is a multiple of
the narrow type's modulus. getExactSDiv then divided by it and hit the
"Remainder by zero?" assertion in APInt::srem.

Fixes #226063
---
 .../Transforms/Scalar/LoopStrengthReduce.cpp  |  4 ++
 .../Transforms/LoopStrengthReduce/pr226063.ll | 45 +++++++++++++++++++
 2 files changed, 49 insertions(+)
 create mode 100644 llvm/test/Transforms/LoopStrengthReduce/pr226063.ll

diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
index 08a4a2f95033e..b2961f80226af 100644
--- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
+++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp
@@ -825,6 +825,10 @@ static bool isMulSExtable(const SCEVMulExpr *M, ScalarEvolution &SE) {
 static const SCEV *getExactSDiv(const SCEV *LHS, const SCEV *RHS,
                                 ScalarEvolution &SE,
                                 bool IgnoreSignificantBits = false) {
+  // A stride can fold to zero once the callers sign-extend it.
+  if (RHS->isZero())
+    return nullptr;
+
   // Handle the trivial case, which works for any SCEV type.
   if (LHS == RHS)
     return SE.getConstant(LHS->getType(), 1);
diff --git a/llvm/test/Transforms/LoopStrengthReduce/pr226063.ll b/llvm/test/Transforms/LoopStrengthReduce/pr226063.ll
new file mode 100644
index 0000000000000..84697c6aa873d
--- /dev/null
+++ b/llvm/test/Transforms/LoopStrengthReduce/pr226063.ll
@@ -0,0 +1,45 @@
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt -S -passes=loop-reduce < %s | FileCheck %s
+
+; %x has 30 known trailing zeros, so the i32 IV stride 4 * trunc(%x) is not a
+; constant but folds to 0 once sign-extended to i64. Make sure LSR does not
+; divide the i64 stride by it while collecting factors.
+
+target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128"
+
+declare void @use(i32)
+
+define void @test(i64 range(i64 1073741824, 1073741825) %x) {
+; CHECK-LABEL: define void @test(
+; CHECK-SAME: i64 range(i64 1073741824, 1073741825) [[X:%.*]]) {
+; CHECK-NEXT:  [[ENTRY:.*]]:
+; CHECK-NEXT:    [[STEP:%.*]] = shl i64 [[X]], 2
+; CHECK-NEXT:    [[TMP0:%.*]] = trunc i64 [[X]] to i32
+; CHECK-NEXT:    [[TMP1:%.*]] = shl i32 [[TMP0]], 2
+; CHECK-NEXT:    br label %[[LOOP:.*]]
+; CHECK:       [[LOOP]]:
+; CHECK-NEXT:    [[LSR_IV1:%.*]] = phi i64 [ [[LSR_IV_NEXT2:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT:    [[LSR_IV:%.*]] = phi i32 [ [[LSR_IV_NEXT:%.*]], %[[LOOP]] ], [ 0, %[[ENTRY]] ]
+; CHECK-NEXT:    call void @use(i32 [[LSR_IV]])
+; CHECK-NEXT:    [[LSR_IV_NEXT]] = add i32 [[LSR_IV]], [[TMP1]]
+; CHECK-NEXT:    [[LSR_IV_NEXT2]] = sub i64 [[LSR_IV1]], [[STEP]]
+; CHECK-NEXT:    [[CMP:%.*]] = icmp eq i64 [[LSR_IV_NEXT2]], 0
+; CHECK-NEXT:    br i1 [[CMP]], label %[[EXIT:.*]], label %[[LOOP]]
+; CHECK:       [[EXIT]]:
+; CHECK-NEXT:    ret void
+;
+entry:
+  %step = shl i64 %x, 2
+  br label %loop
+
+loop:
+  %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ]
+  %iv.next = add i64 %iv, %step
+  %t = trunc i64 %iv to i32
+  call void @use(i32 %t)
+  %cmp = icmp eq i64 %iv.next, 0
+  br i1 %cmp, label %exit, label %loop
+
+exit:
+  ret void
+}