[clang] [llvm] [Clang][RISCV] Add packed widening shift intrinsics (PR #224790)

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``````````bash
git-clang-format --diff origin/main HEAD --extensions c,h,cpp -- clang/lib/CodeGen/TargetBuiltins/RISCV.cpp clang/lib/Headers/riscv_packed_simd.h clang/test/CodeGen/RISCV/rvp-intrinsics.c cross-project-tests/intrinsic-header-tests/riscv_packed_simd.c llvm/lib/Target/RISCV/RISCVISelLowering.cpp --diff_from_common_commit
``````````

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View the diff from clang-format here.
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``````````diff
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 93dc052ef..5c43ca41f 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -13176,8 +13176,7 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
           (VT == MVT::v2i32 && SrcVT == MVT::v2i16)))
       reportFatalUsageError("unsupported packed widening shift intrinsic");
 
-    SDValue ShAmt =
-        DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op.getOperand(2));
+    SDValue ShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op.getOperand(2));
     bool IsSigned = IntNo == Intrinsic::riscv_pwsla;
     if (!Subtarget.is64Bit()) {
       unsigned Opc = IsSigned ? RISCVISD::PWSLA : RISCVISD::PWSLL;

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https://github.com/llvm/llvm-project/pull/224790