[llvm] [InstCombine] Fold inner selects on the same condition in select values (PR #226371)
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Sat Sep 26 15:51:00 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-llvm-transforms
@llvm/pr-subscribers-backend-amdgpu
Author: Henry Jiang (mustartt)
<details>
<summary>Changes</summary>
This patch generalizes f7b86728fa1912fef2da37995a75c1023c838498 from https://reviews.llvm.org/D39999 `[InstCombine] Simplify binops that are only used by a select and are fed by a select with the same condition.` for operations other than binary operators.
Suppose there is an intermediate instruction `I` in between selects. We can propagate the selected value from the inner dependent select on the same condition. This generally has the effect of shortening the critical path.
```
select(C, I(..., select(C, X, Y), ...), Z) -> select(C, I(..., X, ...), Z)
select(C, Z, I(..., select(C, X, Y), ...)) -> select(C, Z, I(..., Y, ...))
```
where `I` is an any nary, speculatable instruction. As an example:
```llvm
%s = select i1 %c, i32 %a, i32 %b
%i = add i32 %s, 1
%r0 = select i1 %c, i32 %i, i32 %x
%r1 = select i1 %c, i32 %i, i32 %y
; becomes
%i = add i32 %a, 1
%r0 = select i1 %c, i32 %i, i32 %x
%r1 = select i1 %c, i32 %i, i32 %y
%s = select i1 %c, ptr null, ptr %p
%g = getelementptr inbounds nuw i8, ptr %s, i64 8
%r = select i1 %c, ptr null, ptr %g
; becomes
%g = getelementptr inbounds nuw i8, ptr %p, i64 8
%r = select i1 %c, ptr null, ptr %g
%s = select i1 %c, i64 %x, i64 0 ; has other uses
%i = add nuw nsw i64 %s, %y
%r = select i1 %c, i64 %i, i64 0
; becomes
%s = select i1 %c, i64 %x, i64 0
%i = add nuw nsw i64 %x, %y ; shortens the dependent path
%r = select i1 %c, i64 %i, i64 0
```
Alive2 Proofs: https://alive2.llvm.org/ce/z/b5gvzS these uses `--disable-undef-input`, but also verifies locally without `--disable-undef-input` but at a much higher smt timeout.
Assisted-By: Claude
---
Patch is 40.51 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/226371.diff
7 Files Affected:
- (modified) llvm/lib/Transforms/InstCombine/InstCombineInternal.h (+1)
- (modified) llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp (+47-43)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll (+30-36)
- (modified) llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll (+9-18)
- (modified) llvm/test/CodeGen/AMDGPU/simplify-libcalls.ll (+1-1)
- (modified) llvm/test/Transforms/InstCombine/select-select.ll (+386-1)
- (modified) llvm/test/Transforms/InstCombine/select.ll (+2-3)
``````````diff
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
index f2549bad3a852..d05b9dfa0cbd0 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
+++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h
@@ -831,6 +831,7 @@ class LLVM_LIBRARY_VISIBILITY InstCombinerImpl final
bool replaceInInstruction(Value *V, Value *Old, Value *New,
unsigned Depth = 0);
+ Instruction *foldInnerSelectOperandsOnSameCond(SelectInst &SI);
Value *insertRangeTest(Value *V, const APInt &Lo, const APInt &Hi,
bool isSigned, bool Inside);
diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
index a4061bbd60770..c7bcf19ea66fe 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp
@@ -1685,6 +1685,50 @@ bool InstCombinerImpl::replaceInInstruction(Value *V, Value *Old, Value *New,
return Changed;
}
+// select(C, I(..., select(C, X, Y), ...), Z) -> select(C, I(..., X, ...), Z)
+// select(C, Z, I(..., select(C, X, Y), ...)) -> select(C, Z, I(..., Y, ...))
+Instruction *
+InstCombinerImpl::foldInnerSelectOperandsOnSameCond(SelectInst &SI) {
+ Value *Cond = SI.getCondition();
+ for (unsigned OperandNo : {1, 2}) {
+ auto *I = dyn_cast<Instruction>(SI.getOperand(OperandNo));
+ if (!I || !isSafeToSpeculativelyExecuteWithVariableReplaced(
+ I, /*IgnoreUBImplyingAttrs=*/false))
+ continue;
+
+ if (Cond->getType()->isVectorTy() && !isNotCrossLaneOperation(I))
+ continue;
+
+ auto GetInnerSelectValue = [&](Value *Operand) -> Value * {
+ auto *InnerSI = dyn_cast<SelectInst>(Operand);
+ if (!InnerSI || InnerSI->getCondition() != Cond)
+ return nullptr;
+ return InnerSI->getOperand(OperandNo);
+ };
+
+ // Every use of I must be the same operand of a select on C.
+ if (any_of(I->uses(), [&](Use &U) {
+ return U.getOperandNo() != OperandNo ||
+ !match(U.getUser(),
+ m_Select(m_Specific(Cond), m_Value(), m_Value()));
+ }))
+ continue;
+
+ bool Changed = false;
+ for (Use &Operand : I->operands()) {
+ if (Value *V = GetInnerSelectValue(Operand)) {
+ replaceUse(Operand, V);
+ Changed = true;
+ }
+ }
+ if (Changed) {
+ Worklist.add(I);
+ return &SI;
+ }
+ }
+ return nullptr;
+}
+
/// If we have a select with an equality comparison, then we know the value in
/// one of the arms of the select. See if substituting this value into an arm
/// and simplifying the result yields the same value as the other arm.
@@ -4918,6 +4962,9 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
if (Instruction *NewSel = foldSelectValueEquivalence(SI, *CI))
return NewSel;
+ if (Instruction *R = foldInnerSelectOperandsOnSameCond(SI))
+ return R;
+
if (ICmpInst *ICI = dyn_cast<ICmpInst>(CondVal))
if (Instruction *Result = foldSelectInstWithICmp(SI, ICI))
return Result;
@@ -5105,49 +5152,6 @@ Instruction *InstCombinerImpl::visitSelectInst(SelectInst &SI) {
}
}
- // Try to simplify a binop sandwiched between 2 selects with the same
- // condition. This is not valid for div/rem because the select might be
- // preventing a division-by-zero.
- // TODO: A div/rem restriction is conservative; use something like
- // isSafeToSpeculativelyExecute().
- // select(C, binop(select(C, X, Y), W), Z) -> select(C, binop(X, W), Z)
- BinaryOperator *TrueBO;
- if (match(TrueVal, m_OneUse(m_BinOp(TrueBO))) && !TrueBO->isIntDivRem()) {
- if (auto *TrueBOSI = dyn_cast<SelectInst>(TrueBO->getOperand(0))) {
- if (TrueBOSI->getCondition() == CondVal) {
- replaceOperand(*TrueBO, 0, TrueBOSI->getTrueValue());
- Worklist.push(TrueBO);
- return &SI;
- }
- }
- if (auto *TrueBOSI = dyn_cast<SelectInst>(TrueBO->getOperand(1))) {
- if (TrueBOSI->getCondition() == CondVal) {
- replaceOperand(*TrueBO, 1, TrueBOSI->getTrueValue());
- Worklist.push(TrueBO);
- return &SI;
- }
- }
- }
-
- // select(C, Z, binop(select(C, X, Y), W)) -> select(C, Z, binop(Y, W))
- BinaryOperator *FalseBO;
- if (match(FalseVal, m_OneUse(m_BinOp(FalseBO))) && !FalseBO->isIntDivRem()) {
- if (auto *FalseBOSI = dyn_cast<SelectInst>(FalseBO->getOperand(0))) {
- if (FalseBOSI->getCondition() == CondVal) {
- replaceOperand(*FalseBO, 0, FalseBOSI->getFalseValue());
- Worklist.push(FalseBO);
- return &SI;
- }
- }
- if (auto *FalseBOSI = dyn_cast<SelectInst>(FalseBO->getOperand(1))) {
- if (FalseBOSI->getCondition() == CondVal) {
- replaceOperand(*FalseBO, 1, FalseBOSI->getFalseValue());
- Worklist.push(FalseBO);
- return &SI;
- }
- }
- }
-
Value *NotCond;
if (match(CondVal, m_Not(m_Value(NotCond))) &&
!InstCombiner::shouldAvoidAbsorbingNotIntoSelect(SI)) {
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
index 80c073c7b94d7..49a469c4a5573 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-pow.ll
@@ -1396,13 +1396,12 @@ define float @test_pow_afn_f32_0.5(float %x) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = select ninf nsz afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp ninf nsz afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select ninf nsz afn i1 [[TMP20]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP22:%.*]] = select ninf nsz afn i1 [[TMP12]], float [[X]], float 0.000000e+00
-; NOPRELINK-NEXT: [[TMP23:%.*]] = call ninf nsz afn float @llvm.copysign.f32(float [[TMP21]], float [[TMP22]])
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select ninf nsz afn i1 [[TMP20]], float [[TMP23]], float [[TMP19]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp ninf nsz afn uno float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select ninf nsz afn i1 [[TMP25]], float +qnan, float [[TMP24]]
-; NOPRELINK-NEXT: ret float [[TMP26]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call ninf nsz afn float @llvm.copysign.f32(float 0.000000e+00, float [[X]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select i1 [[TMP12]], float [[TMP21]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select ninf nsz afn i1 [[TMP20]], float [[TMP22]], float [[TMP19]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp ninf nsz afn uno float [[X]], 0.000000e+00
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select ninf nsz afn i1 [[TMP24]], float +qnan, float [[TMP23]]
+; NOPRELINK-NEXT: ret float [[TMP25]]
;
%pow = tail call nsz ninf afn float @_Z3powff(float %x, float 0.5)
ret float %pow
@@ -1478,13 +1477,12 @@ define <2 x float> @test_pow_afn_v2f32_0.5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = select ninf nsz afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp ninf nsz afn oeq <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select ninf nsz afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
-; NOPRELINK-NEXT: [[TMP22:%.*]] = select ninf nsz afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP23:%.*]] = call ninf nsz afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select ninf nsz afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp ninf nsz afn uno <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select ninf nsz afn <2 x i1> [[TMP25]], <2 x float> splat (float +qnan), <2 x float> [[TMP24]]
-; NOPRELINK-NEXT: ret <2 x float> [[TMP26]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call ninf nsz afn <2 x float> @llvm.copysign.v2f32(<2 x float> zeroinitializer, <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select <2 x i1> [[TMP12]], <2 x float> [[TMP21]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select ninf nsz afn <2 x i1> [[TMP20]], <2 x float> [[TMP22]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp ninf nsz afn uno <2 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select ninf nsz afn <2 x i1> [[TMP24]], <2 x float> splat (float +qnan), <2 x float> [[TMP23]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP25]]
;
%pow = tail call nsz ninf afn <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 0.5, float 0.5>)
ret <2 x float> %pow
@@ -1602,13 +1600,12 @@ define <3 x float> @test_pow_afn_v3f32_0.5_splat_undef(<3 x float> %x, <3 x floa
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <3 x i1> [[TMP17]], [[TMP16]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = select ninf nsz afn <3 x i1> [[TMP18]], <3 x float> splat (float +qnan), <3 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp ninf nsz afn oeq <3 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select ninf nsz afn <3 x i1> [[TMP20]], <3 x float> zeroinitializer, <3 x float> splat (float +inf)
-; NOPRELINK-NEXT: [[TMP22:%.*]] = select ninf nsz afn <3 x i1> [[TMP12]], <3 x float> [[X]], <3 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP23:%.*]] = call ninf nsz afn <3 x float> @llvm.copysign.v3f32(<3 x float> [[TMP21]], <3 x float> [[TMP22]])
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select ninf nsz afn <3 x i1> [[TMP20]], <3 x float> [[TMP23]], <3 x float> [[TMP19]]
-; NOPRELINK-NEXT: [[TMP25:%.*]] = fcmp ninf nsz afn uno <3 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP26:%.*]] = select ninf nsz afn <3 x i1> [[TMP25]], <3 x float> splat (float +qnan), <3 x float> [[TMP24]]
-; NOPRELINK-NEXT: ret <3 x float> [[TMP26]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call ninf nsz afn <3 x float> @llvm.copysign.v3f32(<3 x float> zeroinitializer, <3 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select <3 x i1> [[TMP12]], <3 x float> [[TMP21]], <3 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select ninf nsz afn <3 x i1> [[TMP20]], <3 x float> [[TMP22]], <3 x float> [[TMP19]]
+; NOPRELINK-NEXT: [[TMP24:%.*]] = fcmp ninf nsz afn uno <3 x float> [[X]], zeroinitializer
+; NOPRELINK-NEXT: [[TMP25:%.*]] = select ninf nsz afn <3 x i1> [[TMP24]], <3 x float> splat (float +qnan), <3 x float> [[TMP23]]
+; NOPRELINK-NEXT: ret <3 x float> [[TMP25]]
;
%pow = tail call nsz ninf afn <3 x float> @_Z3powDv3_fS_(<3 x float> %x, <3 x float> <float 0.5, float poison, float 0.5>)
ret <3 x float> %pow
@@ -4333,11 +4330,10 @@ define float @test_pow_afn_f32_nnan_ninf__y_4_5(float %x) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = and i1 [[TMP17]], [[TMP16]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn i1 [[TMP18]], float +qnan, float [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn i1 [[TMP20]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn i1 [[TMP12]], float [[X]], float 0.000000e+00
-; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP21]], float [[TMP22]])
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn i1 [[TMP20]], float [[TMP23]], float [[TMP19]]
-; NOPRELINK-NEXT: ret float [[TMP24]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float 0.000000e+00, float [[X]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select i1 [[TMP12]], float [[TMP21]], float 0.000000e+00
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select nnan ninf afn i1 [[TMP20]], float [[TMP22]], float [[TMP19]]
+; NOPRELINK-NEXT: ret float [[TMP23]]
;
%pow = tail call afn nnan ninf float @_Z3powff(float %x, float 4.5)
ret float %pow
@@ -4528,11 +4524,10 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
-; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
-; NOPRELINK-NEXT: ret <2 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> zeroinitializer, <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select <2 x i1> [[TMP12]], <2 x float> [[TMP21]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP22]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP23]]
;
%pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 4.5, float 4.5>)
ret <2 x float> %pow
@@ -4566,11 +4561,10 @@ define <2 x float> @test_pow_afn_v2f32_nnan_ninf__y_4_5_undef(<2 x float> %x) {
; NOPRELINK-NEXT: [[TMP18:%.*]] = and <2 x i1> [[TMP17]], [[TMP16]]
; NOPRELINK-NEXT: [[TMP19:%.*]] = select nnan ninf afn <2 x i1> [[TMP18]], <2 x float> splat (float +qnan), <2 x float> [[TMP14]]
; NOPRELINK-NEXT: [[TMP20:%.*]] = fcmp nnan ninf afn oeq <2 x float> [[X]], zeroinitializer
-; NOPRELINK-NEXT: [[TMP21:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> zeroinitializer, <2 x float> splat (float +inf)
-; NOPRELINK-NEXT: [[TMP22:%.*]] = select nnan ninf afn <2 x i1> [[TMP12]], <2 x float> [[X]], <2 x float> zeroinitializer
-; NOPRELINK-NEXT: [[TMP23:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> [[TMP21]], <2 x float> [[TMP22]])
-; NOPRELINK-NEXT: [[TMP24:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP23]], <2 x float> [[TMP19]]
-; NOPRELINK-NEXT: ret <2 x float> [[TMP24]]
+; NOPRELINK-NEXT: [[TMP21:%.*]] = call nnan ninf afn <2 x float> @llvm.copysign.v2f32(<2 x float> zeroinitializer, <2 x float> [[X]])
+; NOPRELINK-NEXT: [[TMP22:%.*]] = select <2 x i1> [[TMP12]], <2 x float> [[TMP21]], <2 x float> zeroinitializer
+; NOPRELINK-NEXT: [[TMP23:%.*]] = select nnan ninf afn <2 x i1> [[TMP20]], <2 x float> [[TMP22]], <2 x float> [[TMP19]]
+; NOPRELINK-NEXT: ret <2 x float> [[TMP23]]
;
%pow = tail call afn nnan ninf <2 x float> @_Z3powDv2_fS_(<2 x float> %x, <2 x float> <float 4.5, float poison>)
ret <2 x float> %pow
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
index 805e510bde37b..a342e675044cc 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-simplify-libcall-rootn.ll
@@ -1362,8 +1362,7 @@ define float @test_rootn_afn_nnan_ninf_f32__y_3(float %x) {
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float 0.000000e+00, float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT: ret float [[TMP9]]
;
@@ -1385,8 +1384,7 @@ define float @test_rootn_afn_nnan_ninf_f32__y_neg3(float %x) {
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float +inf, float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
; NOPRELINK-NEXT: ret float [[TMP9]]
;
@@ -1452,8 +1450,7 @@ define float @test_rootn_afn_nnan_ninf_f32__y_5(float %x) {
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float 0.000000e+00, float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT: ret float [[TMP9]]
;
@@ -1475,8 +1472,7 @@ define float @test_rootn_afn_nnan_ninf_f32__y_neg5(float %x) {
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float +inf, float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP5]], float [[TMP8]]
; NOPRELINK-NEXT: ret float [[TMP9]]
;
@@ -1498,8 +1494,7 @@ define float @test_rootn_afn_nnan_ninf_f32__y_7(float %x) {
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn oeq float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float 0.000000e+00, float [[X]])
; NOPRELINK-NEXT: [[TMP9:%.*]] = select nnan ninf afn i1 [[TMP6]], float [[TMP8]], float [[TMP5]]
; NOPRELINK-NEXT: ret float [[TMP9]]
;
@@ -1521,8 +1516,7 @@ define float @test_rootn_afn_nnan_ninf_f32__y_neg7(float %x) {
; NOPRELINK-NEXT: [[TMP4:%.*]] = call nnan ninf afn float @llvm.exp2.f32(float [[TMP3]])
; NOPRELINK-NEXT: [[TMP5:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP4]], float [[X]])
; NOPRELINK-NEXT: [[TMP6:%.*]] = fcmp nnan ninf afn une float [[X]], 0.000000e+00
-; NOPRELINK-NEXT: [[TMP7:%.*]] = select nnan ninf afn i1 [[TMP6]], float 0.000000e+00, float +inf
-; NOPRELINK-NEXT: [[TMP8:%.*]] = call nnan ninf afn float @llvm.copysign.f32(float [[TMP7]], float [[X]])
+; NOPRELINK-NEXT: [[TMP8:%.*...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/226371
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