[llvm] Revert "[CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths" (PR #226665)
via llvm-commits
llvm-commits at lists.llvm.org
Sat Sep 26 02:11:36 PDT 2026
llvmorg-github-actions[bot] wrote:
<!--LLVM PR SUMMARY COMMENT-->
@llvm/pr-subscribers-backend-amdgpu
Author: Matt Arsenault (arsenm)
<details>
<summary>Changes</summary>
Reverts llvm/llvm-project#<!-- -->226556
This is handling malformed IR and adding size based instead of register class based reasoning
---
Patch is 192.75 KiB, truncated to 20.00 KiB below, full version: https://github.com/llvm/llvm-project/pull/226665.diff
4 Files Affected:
- (modified) llvm/lib/CodeGen/DetectDeadLanes.cpp (+2-13)
- (removed) llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir (-24)
- (modified) llvm/test/CodeGen/AMDGPU/frem.ll (+1052-1538)
- (removed) llvm/test/CodeGen/AMDGPU/true16-uniform-f16-phi-copysign.ll (-72)
``````````diff
diff --git a/llvm/lib/CodeGen/DetectDeadLanes.cpp b/llvm/lib/CodeGen/DetectDeadLanes.cpp
index 7a2fc38c1aa58..79104760b7b75 100644
--- a/llvm/lib/CodeGen/DetectDeadLanes.cpp
+++ b/llvm/lib/CodeGen/DetectDeadLanes.cpp
@@ -72,6 +72,8 @@ static bool isCrossCopy(const MachineRegisterInfo &MRI,
assert(lowersToCopies(MI));
Register SrcReg = MO.getReg();
const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
+ if (DstRC == SrcRC)
+ return false;
unsigned SrcSubIdx = MO.getSubReg();
@@ -93,19 +95,6 @@ static bool isCrossCopy(const MachineRegisterInfo &MRI,
}
}
- if (DstRC == SrcRC) {
- // Identical register classes only give a lane-for-lane transfer if the
- // source operand and the destination subregister slot are the same width.
- TypeSize SrcSize = SrcSubIdx
- ? TypeSize::getFixed(TRI.getSubRegIdxSize(SrcSubIdx))
- : TRI.getRegSizeInBits(*SrcRC);
- TypeSize DstSize = DstSubIdx
- ? TypeSize::getFixed(TRI.getSubRegIdxSize(DstSubIdx))
- : TRI.getRegSizeInBits(*DstRC);
- if (SrcSize == DstSize)
- return false;
- }
-
return !TRI.findCommonRegClass(SrcRC, SrcSubIdx, DstRC, DstSubIdx);
}
diff --git a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir b/llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
deleted file mode 100644
index d474bcb70ea39..0000000000000
--- a/llvm/test/CodeGen/AMDGPU/detect-dead-lanes-reg-sequence-narrow-slot.mir
+++ /dev/null
@@ -1,24 +0,0 @@
-# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 6
-# RUN: llc -mtriple=amdgpu12.50 -run-pass detect-dead-lanes -o - %s | FileCheck %s
-
----
-name: reg_sequence_wide_source_in_narrow_slot
-tracksRegLiveness: true
-registers:
- - { id: 0, class: vgpr_16 }
- - { id: 1, class: vgpr_32 }
- - { id: 2, class: vgpr_32 }
- - { id: 3, class: vgpr_32 }
- - { id: 4, class: vgpr_32 }
-body: |
- bb.0:
- ; CHECK-LABEL: name: reg_sequence_wide_source_in_narrow_slot
- ; CHECK: S_NOP 0, implicit-def %0
- ; CHECK-NEXT: [[REG_SEQUENCE:%[0-9]+]]:vgpr_32 = REG_SEQUENCE %0, %subreg.lo16, undef %2:vgpr_32, %subreg.hi16
- ; CHECK-NEXT: [[REG_SEQUENCE1:%[0-9]+]]:vgpr_32 = REG_SEQUENCE [[REG_SEQUENCE]], %subreg.lo16, undef %4:vgpr_32, %subreg.hi16
- ; CHECK-NEXT: S_NOP 0, implicit [[REG_SEQUENCE1]]
- S_NOP 0, implicit-def %0
- %1 = REG_SEQUENCE %0, %subreg.lo16, undef %2, %subreg.hi16
- %3 = REG_SEQUENCE %1, %subreg.lo16, undef %4, %subreg.hi16
- S_NOP 0, implicit %3
-...
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 7e0ceb5baf440..486d7c15150bc 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -529,70 +529,67 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[4:5] offset:8
-; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, |v1.l|
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] offset:8
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.h|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v3, v2
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v2
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
+; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0x8000, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.l, v3.l, vcc_lo
; GFX11-TRUE16-NEXT: s_branch .LBB0_3
; GFX11-TRUE16-NEXT: .LBB0_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
; GFX11-TRUE16-NEXT: .LBB0_3: ; %Flow18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v3, 11
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v2
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v2
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v2
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX11-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -600,51 +597,29 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v4, v3, v7
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s2
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX11-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v5, v3, v4
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX11-TRUE16-NEXT: v_fma_f32 v1, -v4, v2, v1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
-; GFX11-TRUE16-NEXT: .LBB0_9: ; %Flow19
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1.l|
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX11-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.h
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v3.l, s2
+; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: frem_f16:
@@ -803,42 +778,41 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v2
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v2
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v5
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
-; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s1, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -846,46 +820,23 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, v4
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, s0
-; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, v7
-; GFX1150-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
-; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
-; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
-; GFX1150-TRUE16-NEXT: .LBB0_9: ; %Flow19
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(V...
[truncated]
``````````
</details>
https://github.com/llvm/llvm-project/pull/226665
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