[llvm] c0b6ee1 - [AArch64] Add tests for sve fixed length reverse shuffles. NFC (#226661)
via llvm-commits
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Sat Sep 26 01:47:59 PDT 2026
Author: David Green
Date: 2026-09-26T09:47:52+01:00
New Revision: c0b6ee14c2f8dece229da557352e116f9a6d7064
URL: https://github.com/llvm/llvm-project/commit/c0b6ee14c2f8dece229da557352e116f9a6d7064
DIFF: https://github.com/llvm/llvm-project/commit/c0b6ee14c2f8dece229da557352e116f9a6d7064.diff
LOG: [AArch64] Add tests for sve fixed length reverse shuffles. NFC (#226661)
Added:
llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
Modified:
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
new file mode 100644
index 0000000000000..6dffe8d267353
--- /dev/null
+++ b/llvm/test/CodeGen/AArch64/sve-fixed-length-shuffle-reverse.ll
@@ -0,0 +1,158 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 6
+; RUN: llc < %s -mtriple=aarch64--linux-gnu -mattr=+sve | FileCheck %s
+
+define <2 x i64> @testrev_v2i64_vscale1(<2 x i64> %x) vscale_range(1,1) {
+; CHECK-LABEL: testrev_v2i64_vscale1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
+ ret <2 x i64> %r
+}
+
+define <2 x i64> @testrev_v2i64(<2 x i64> %x) {
+; CHECK-LABEL: testrev_v2i64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <2 x i64> %x, <2 x i64> poison, <2 x i32> <i32 1, i32 0>
+ ret <2 x i64> %r
+}
+
+define <2 x double> @testrev_v2f64_vscale1(<2 x double> %x) vscale_range(1,1) {
+; CHECK-LABEL: testrev_v2f64_vscale1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <2 x double> %x, <2 x double> poison, <2 x i32> <i32 1, i32 0>
+ ret <2 x double> %r
+}
+
+define <2 x double> @testrev_v2f64(<2 x double> %x) {
+; CHECK-LABEL: testrev_v2f64:
+; CHECK: // %bb.0:
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <2 x double> %x, <2 x double> poison, <2 x i32> <i32 1, i32 0>
+ ret <2 x double> %r
+}
+
+define <4 x i32> @testrev_v4i32_vscale1(<4 x i32> %x) vscale_range(1,1) {
+; CHECK-LABEL: testrev_v4i32_vscale1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i32> %r
+}
+
+define <4 x i32> @testrev_v4i32(<4 x i32> %x) {
+; CHECK-LABEL: testrev_v4i32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <4 x i32> %x, <4 x i32> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x i32> %r
+}
+
+define <4 x float> @testrev_v4f32_vscale1(<4 x float> %x) vscale_range(1,1) {
+; CHECK-LABEL: testrev_v4f32_vscale1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <4 x float> %x, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x float> %r
+}
+
+define <4 x float> @testrev_v4f32(<4 x float> %x) {
+; CHECK-LABEL: testrev_v4f32:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.4s, v0.4s
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <4 x float> %x, <4 x float> poison, <4 x i32> <i32 3, i32 2, i32 1, i32 0>
+ ret <4 x float> %r
+}
+
+define <8 x i16> @testrev_v8i16_vscale1(<8 x i16> %x) vscale_range(1,1) {
+; CHECK-LABEL: testrev_v8i16_vscale1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i16> %r
+}
+
+define <8 x i16> @testrev_v8i16(<8 x i16> %x) {
+; CHECK-LABEL: testrev_v8i16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <8 x i16> %x, <8 x i16> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x i16> %r
+}
+
+define <8 x half> @testrev_v8f16_vscale1(<8 x half> %x) vscale_range(1,1) {
+; CHECK-LABEL: testrev_v8f16_vscale1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <8 x half> %x, <8 x half> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x half> %r
+}
+
+define <8 x half> @testrev_v8f16(<8 x half> %x) {
+; CHECK-LABEL: testrev_v8f16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <8 x half> %x, <8 x half> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x half> %r
+}
+
+define <8 x bfloat> @testrev_v8bf16_vscale1(<8 x bfloat> %x) vscale_range(1,1) {
+; CHECK-LABEL: testrev_v8bf16_vscale1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <8 x bfloat> %x, <8 x bfloat> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x bfloat> %r
+}
+
+define <8 x bfloat> @testrev_v8bf16(<8 x bfloat> %x) {
+; CHECK-LABEL: testrev_v8bf16:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.8h, v0.8h
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <8 x bfloat> %x, <8 x bfloat> poison, <8 x i32> <i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <8 x bfloat> %r
+}
+
+define <16 x i8> @testrev_v16i8_vscale1(<16 x i8> %x) vscale_range(1,1) {
+; CHECK-LABEL: testrev_v16i8_vscale1:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x i8> %r
+}
+
+define <16 x i8> @testrev_v16i8(<16 x i8> %x) {
+; CHECK-LABEL: testrev_v16i8:
+; CHECK: // %bb.0:
+; CHECK-NEXT: rev64 v0.16b, v0.16b
+; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8
+; CHECK-NEXT: ret
+ %r = shufflevector <16 x i8> %x, <16 x i8> poison, <16 x i32> <i32 15, i32 14, i32 13, i32 12, i32 11, i32 10, i32 9, i32 8, i32 7, i32 6, i32 5, i32 4, i32 3, i32 2, i32 1, i32 0>
+ ret <16 x i8> %r
+}
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