[llvm] [RISCV] Fixed redundant add instructions generated during the fold of vscale add in rvv. (PR #225266)

[via llvm-commits]

FoolgryGamer wrote:

The previous changes in `DAGCombiner.cpp` would cause a performance regression on the
AArch64 architecture.
In this submission, the fold of vscale add has been lowered to the RISC-V architecture
to ensure no performance regression occurs on the AArch64 architecture.

I locally tested the AArch64 and RISC-V test cases that had previously failed in CI, and they all passed.

https://github.com/llvm/llvm-project/pull/225266