[llvm] [CodeGen] Fix DetectDeadLanes for same-class copies with mismatched widths (PR #226556)

[Shilei Tian via llvm-commits]

shiltian wrote:

> That is wrong when a REG_SEQUENCE names a subregister slot narrower than the source operand, e.g. a 32-bit vreg used as the lo16 piece of another 32-bit vreg.

Is it even legal to have this in the first place?

https://github.com/llvm/llvm-project/pull/226556