[llvm] 44c8476 - [RISCV] Replace uses of RegState::Define. NFC (#226569)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 12:52:49 PDT 2026
Author: Craig Topper
Date: 2026-09-25T12:52:43-07:00
New Revision: 44c84768990686eb1e24b4d1dcbd13fff37442bb
URL: https://github.com/llvm/llvm-project/commit/44c84768990686eb1e24b4d1dcbd13fff37442bb
DIFF: https://github.com/llvm/llvm-project/commit/44c84768990686eb1e24b4d1dcbd13fff37442bb.diff
LOG: [RISCV] Replace uses of RegState::Define. NFC (#226569)
Either pass the destination register to the BuildMI call or use addDef
if there are multiple defs or other flags are set.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
index c833c1c7ee3c2..440dc2a092ad5 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoPostRA.cpp
@@ -108,11 +108,11 @@ bool RISCVExpandPseudoPostRAImpl::expandMovAddr(
bool Renamable = MBBI->getOperand(0).isRenamable();
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LUI))
- .addReg(DstReg, RegState::Define | getRenamableRegState(Renamable))
+ .addDef(DstReg, getRenamableRegState(Renamable))
.add(MBBI->getOperand(1));
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADDI))
- .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead) |
- getRenamableRegState(Renamable))
+ .addDef(DstReg,
+ getDeadRegState(DstIsDead) | getRenamableRegState(Renamable))
.addReg(DstReg, RegState::Kill | getRenamableRegState(Renamable))
.add(MBBI->getOperand(2));
MBBI->eraseFromParent();
@@ -131,11 +131,11 @@ bool RISCVExpandPseudoPostRAImpl::expandAddUpperImm(
// Expand to LUI+ADD: the immediate is already the upper 20-bit value.
BuildMI(MBB, MBBI, DL, TII->get(RISCV::LUI))
- .addReg(DstReg, RegState::Define | getRenamableRegState(Renamable))
+ .addDef(DstReg, getRenamableRegState(Renamable))
.addImm(Hi);
BuildMI(MBB, MBBI, DL, TII->get(RISCV::ADD))
- .addReg(DstReg, RegState::Define | getDeadRegState(DstIsDead) |
- getRenamableRegState(Renamable))
+ .addDef(DstReg,
+ getDeadRegState(DstIsDead) | getRenamableRegState(Renamable))
.addReg(BaseReg)
.addReg(DstReg, RegState::Kill | getRenamableRegState(Renamable));
diff --git a/llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp b/llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
index d3c4cce206977..2ae3dae0822f4 100644
--- a/llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
+++ b/llvm/lib/Target/RISCV/RISCVExpandPseudoPreEmit.cpp
@@ -594,8 +594,7 @@ bool RISCVExpandPseudoPreEmitImpl::expandPseudoReadVLENBViaVSETVLIX0(
unsigned VTypeImm = RISCVVType::encodeVTYPE(
VLMUL, /*SEW=*/8, /*TailAgnostic=*/true, /*MaskAgnostic=*/true);
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0))
- .addReg(Dst, RegState::Define)
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::PseudoVSETVLIX0), Dst)
.addReg(RISCV::X0, RegState::Kill)
.addImm(VTypeImm);
diff --git a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
index 648df0690fa20..7d2539ab3f2da 100644
--- a/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVFrameLowering.cpp
@@ -146,8 +146,7 @@ static void emitSCSPrologue(MachineFunction &MF, MachineBasicBlock &MBB,
// Store return address to shadow call stack
// addi gp, gp, [4|8]
// s[w|d] ra, -[4|8](gp)
- BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
- .addReg(SCSPReg, RegState::Define)
+ BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI), SCSPReg)
.addReg(SCSPReg)
.addImm(SlotSize)
.setMIFlag(MachineInstr::FrameSetup);
@@ -214,13 +213,11 @@ static void emitSCSEpilogue(MachineFunction &MF, MachineBasicBlock &MBB,
// Load return address from shadow call stack
// l[w|d] ra, -[4|8](gp)
// addi gp, gp, -[4|8]
- BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW))
- .addReg(RAReg, RegState::Define)
+ BuildMI(MBB, MI, DL, TII->get(IsRV64 ? RISCV::LD : RISCV::LW), RAReg)
.addReg(SCSPReg)
.addImm(-SlotSize)
.setMIFlag(MachineInstr::FrameDestroy);
- BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI))
- .addReg(SCSPReg, RegState::Define)
+ BuildMI(MBB, MI, DL, TII->get(RISCV::ADDI), SCSPReg)
.addReg(SCSPReg)
.addImm(-SlotSize)
.setMIFlag(MachineInstr::FrameDestroy);
@@ -245,8 +242,7 @@ static void emitSiFiveCLICStackSwap(MachineFunction &MF, MachineBasicBlock &MBB,
assert(STI.hasVendorXSfmclic() && "Stack Swapping Requires XSfmclic");
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRW))
- .addReg(SPReg, RegState::Define)
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRW), SPReg)
.addImm(RISCVSysReg::sf_mscratchcsw)
.addReg(SPReg, RegState::Kill)
.setMIFlag(FrameFlag);
@@ -307,8 +303,7 @@ static void emitSiFiveCLICPreemptibleSaves(MachineFunction &MF,
CFIInstBuilder(MBB, MBBI, MachineInstr::FrameSetup)
.buildOffset(RISCV::X5, MF.getFrameInfo().getObjectOffset(ScratchFI));
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRS))
- .addReg(RISCV::X5, RegState::Define)
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRS), RISCV::X5)
.addImm(RISCVSysReg::mcause)
.addReg(RISCV::X0)
.setMIFlag(MachineInstr::FrameSetup);
@@ -317,15 +312,13 @@ static void emitSiFiveCLICPreemptibleSaves(MachineFunction &MF,
&RISCV::GPRRegClass, Register(),
MachineInstr::FrameSetup);
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRS))
- .addReg(RISCV::X5, RegState::Define)
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRS), RISCV::X5)
.addImm(RISCVSysReg::mepc)
.addReg(RISCV::X0)
.setMIFlag(MachineInstr::FrameSetup);
// Enable interrupts.
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRSI))
- .addReg(RISCV::X0, RegState::Define)
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRSI), RISCV::X0)
.addImm(RISCVSysReg::mstatus)
.addImm(8)
.setMIFlag(MachineInstr::FrameSetup);
@@ -358,16 +351,14 @@ static void emitSiFiveCLICPreemptibleRestores(MachineFunction &MF,
RISCV::NoSubRegister, MachineInstr::FrameDestroy);
// Disable interrupts.
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRCI))
- .addReg(RISCV::X0, RegState::Define)
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRCI), RISCV::X0)
.addImm(RISCVSysReg::mstatus)
.addImm(8)
.setMIFlag(MachineInstr::FrameDestroy);
// Restore `mepc` and `mcause` through X5, then restore the value X5 held
// on entry to the handler.
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRW))
- .addReg(RISCV::X0, RegState::Define)
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRW), RISCV::X0)
.addImm(RISCVSysReg::mepc)
.addReg(RISCV::X5, RegState::Kill)
.setMIFlag(MachineInstr::FrameDestroy);
@@ -376,8 +367,7 @@ static void emitSiFiveCLICPreemptibleRestores(MachineFunction &MF,
RVFI->getInterruptCSRFrameIndex(0),
&RISCV::GPRRegClass, Register(),
RISCV::NoSubRegister, MachineInstr::FrameDestroy);
- BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRW))
- .addReg(RISCV::X0, RegState::Define)
+ BuildMI(MBB, MBBI, DL, TII->get(RISCV::CSRRW), RISCV::X0)
.addImm(RISCVSysReg::mcause)
.addReg(RISCV::X5, RegState::Kill)
.setMIFlag(MachineInstr::FrameDestroy);
diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
index 62b8e9f1e0ef4..1087737e2d96c 100644
--- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp
@@ -168,7 +168,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
auto MI = BuildMI(MBB, InsertPt, DL,
TII->get(Info.getTWiden() ? RISCV::PseudoSF_VSETTNTX0X0
: RISCV::PseudoVSETVLIX0X0))
- .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+ .addDef(RISCV::X0, RegState::Dead)
.addReg(RISCV::X0, RegState::Kill)
.addImm(Info.encodeVTYPE())
.addReg(RISCV::VL, RegState::Implicit);
@@ -189,7 +189,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
BuildMI(MBB, InsertPt, DL,
TII->get(Info.getTWiden() ? RISCV::PseudoSF_VSETTNTX0X0
: RISCV::PseudoVSETVLIX0X0))
- .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+ .addDef(RISCV::X0, RegState::Dead)
.addReg(RISCV::X0, RegState::Kill)
.addImm(Info.encodeVTYPE())
.addReg(RISCV::VL, RegState::Implicit);
@@ -203,7 +203,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
if (Info.hasAVLImm()) {
auto MI = BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETIVLI))
- .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+ .addDef(RISCV::X0, RegState::Dead)
.addImm(Info.getAVLImm())
.addImm(Info.encodeVTYPE());
if (LIS)
@@ -216,7 +216,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
auto MI = BuildMI(MBB, InsertPt, DL,
TII->get(Info.getTWiden() ? RISCV::PseudoSF_VSETTNTX0
: RISCV::PseudoVSETVLIX0))
- .addReg(DestReg, RegState::Define | RegState::Dead)
+ .addDef(DestReg, RegState::Dead)
.addReg(RISCV::X0, RegState::Kill)
.addImm(Info.encodeVTYPE());
if (LIS) {
@@ -231,7 +231,7 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB,
auto MI = BuildMI(MBB, InsertPt, DL,
TII->get(Info.getTWiden() ? RISCV::PseudoSF_VSETTNT
: RISCV::PseudoVSETVLI))
- .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+ .addDef(RISCV::X0, RegState::Dead)
.addReg(AVLReg)
.addImm(Info.encodeVTYPE());
if (LIS) {
@@ -1109,7 +1109,7 @@ bool RISCVInsertVSETVLI::insertVSETMTK(MachineBasicBlock &MBB,
MachineOperand &Op = MI.getOperand(OpNum);
auto TmpMI = BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(Opcode))
- .addReg(RISCV::X0, RegState::Define | RegState::Dead)
+ .addDef(RISCV::X0, RegState::Dead)
.addReg(Op.getReg())
.addImm(Log2_32(CurrInfo.getSEW()))
.addImm(CurrInfo.getTWiden());
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
index 541ba785c20c9..e7aaeb0ac9e97 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -1046,27 +1046,27 @@ void RISCVInstrInfo::movImm(MachineBasicBlock &MBB,
switch (Inst.getOpndKind()) {
case RISCVMatInt::Imm:
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
- .addReg(DstReg, RegState::Define | DstRegState)
+ .addDef(DstReg, DstRegState)
.addImm(Inst.getImm())
.setMIFlag(Flag);
break;
case RISCVMatInt::RegX0:
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
- .addReg(DstReg, RegState::Define | DstRegState)
+ .addDef(DstReg, DstRegState)
.addReg(SrcReg, SrcRegState)
.addReg(RISCV::X0)
.setMIFlag(Flag);
break;
case RISCVMatInt::RegReg:
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
- .addReg(DstReg, RegState::Define | DstRegState)
+ .addDef(DstReg, DstRegState)
.addReg(SrcReg, SrcRegState)
.addReg(SrcReg, SrcRegState)
.setMIFlag(Flag);
break;
case RISCVMatInt::RegImm:
BuildMI(MBB, MBBI, DL, get(Inst.getOpcode()))
- .addReg(DstReg, RegState::Define | DstRegState)
+ .addDef(DstReg, DstRegState)
.addReg(SrcReg, SrcRegState)
.addImm(Inst.getImm())
.setMIFlag(Flag);
@@ -1545,7 +1545,7 @@ void RISCVInstrInfo::insertIndirectBranch(MachineBasicBlock &MBB,
auto II = MBB.end();
// We may also update the jump target to RestoreBB later.
MachineInstr &MI = *BuildMI(MBB, II, DL, get(RISCV::PseudoJump))
- .addReg(ScratchReg, RegState::Define | RegState::Dead)
+ .addDef(ScratchReg, RegState::Dead)
.addMBB(&DestBB, RISCVII::MO_CALL);
RS->enterBasicBlockEnd(MBB);
@@ -4042,10 +4042,9 @@ void RISCVInstrInfo::buildOutlinedFrame(
MBB.addLiveIn(RISCV::X5);
// Add in a return instruction to the end of the outlined frame.
- MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR))
- .addReg(RISCV::X0, RegState::Define)
- .addReg(RISCV::X5)
- .addImm(0));
+ MBB.insert(MBB.end(), BuildMI(MF, DebugLoc(), get(RISCV::JALR), RISCV::X0)
+ .addReg(RISCV::X5)
+ .addImm(0));
}
MachineBasicBlock::iterator RISCVInstrInfo::insertOutlinedCall(
diff --git a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
index eb6eddfba749f..1892e86413843 100644
--- a/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVLoadStoreOptimizer.cpp
@@ -822,23 +822,19 @@ void RISCVLoadStoreOpt::splitLdSdIntoTwo(MachineBasicBlock &MBB,
// X10 = LW killed X10, 0
if (FirstReg == BaseReg) {
MIB2 = BuildMI(MBB, MBBI, DL, TII->get(Opc))
- .addReg(SecondReg,
- RegState::Define | getDeadRegState(SecondOp.isDead()))
+ .addDef(SecondReg, getDeadRegState(SecondOp.isDead()))
.addReg(BaseReg);
MIB1 = BuildMI(MBB, MBBI, DL, TII->get(Opc))
- .addReg(FirstReg,
- RegState::Define | getDeadRegState(FirstOp.isDead()))
+ .addDef(FirstReg, getDeadRegState(FirstOp.isDead()))
.addReg(BaseReg, getKillRegState(BaseOp.isKill()));
} else {
MIB1 = BuildMI(MBB, MBBI, DL, TII->get(Opc))
- .addReg(FirstReg,
- RegState::Define | getDeadRegState(FirstOp.isDead()))
+ .addDef(FirstReg, getDeadRegState(FirstOp.isDead()))
.addReg(BaseReg);
MIB2 = BuildMI(MBB, MBBI, DL, TII->get(Opc))
- .addReg(SecondReg,
- RegState::Define | getDeadRegState(SecondOp.isDead()))
+ .addDef(SecondReg, getDeadRegState(SecondOp.isDead()))
.addReg(BaseReg, getKillRegState(BaseOp.isKill()));
}
@@ -923,8 +919,7 @@ bool RISCVLoadStoreOpt::fixInvalidRegPairOp(MachineBasicBlock &MBB,
if (IsLoad) {
// For LD, the register pair is the destination
- MIB.addReg(RegPair, RegState::Define | getDeadRegState(FirstOp.isDead() &&
- SecondOp.isDead()));
+ MIB.addDef(RegPair, getDeadRegState(FirstOp.isDead() && SecondOp.isDead()));
} else {
// For SD, the register pair is the source
MIB.addReg(RegPair, getKillRegState(FirstOp.isKill() && SecondOp.isKill()));
diff --git a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
index 1886ccc0b8186..bae193d59f7a4 100644
--- a/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
+++ b/llvm/lib/Target/RISCV/RISCVZilsdOptimizer.cpp
@@ -351,8 +351,8 @@ bool RISCVPreAllocZilsdOpt::rescheduleOps(
if (IsLoad) {
MIB = BuildMI(*MBB, InsertPos, DL, TII->get(RISCV::PseudoLD_RV32_OPT))
- .addReg(FirstReg, RegState::Define)
- .addReg(SecondReg, RegState::Define);
+ .addDef(FirstReg)
+ .addDef(SecondReg);
++NumLDFormed;
LLVM_DEBUG(dbgs() << "Formed LD: " << *MIB << "\n");
} else {
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