[clang] [llvm] [Clang][RISCV][P-ext] Add Packed Widening Multiply Accumulate intrinsics (PR #226505)

[Craig Topper via llvm-commits]

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@@ -1977,6 +1977,20 @@ def riscv_pmaccsu_halves_00
 def riscv_pmaccsu_halves_11
     : RVSDNode<"PMACCSU_HALVES_11", SDT_RISCVWideningMulAccByHalves>;
 
+// The pwmacc*/pwmaccsu* instructions use a 64-bit accumulator on RV32.
+// The accumulator and result are represented as two i32 values in the
+// SelectionDAG; custom ISel combines and splits the register pair.
+def SDT_RISCVPackedWideningMulAccPair
+    : SDTypeProfile<2, 4, [SDTCisVT<0, i32>, SDTCisVT<1, i32>,
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topperc wrote:

This node should produce a v2i32 result. That's a legal type for RV32.

https://github.com/llvm/llvm-project/pull/226505