[llvm] [AMDGPU] Lower loads and stores for address space 13 (PR #209541)

[Gheorghe-Teodor Bercea via llvm-commits]

doru1004 wrote:

@arsenm M0 is now written at selection: the movrel pseudos take the index as an `M0` pattern input,
the indexing-mode ones declare `Defs = [M0]`, and SIFixSGPRCopies waterfalls a divergent index. The
custom inserter is gone.

https://github.com/llvm/llvm-project/pull/209541