[llvm] [AMDGPU] Insert MFMA anti-hints in GCNPreRAOptimizations (PR #218075)

[Matt Arsenault via llvm-commits]

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@@ -0,0 +1,514 @@
+//===-- GCNPreRAAntiHints.cpp - MFMA register anti-hints ------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+/// \file
+/// Insert register allocation anti-hints.
+///
+//===----------------------------------------------------------------------===//
+
+#include "GCNPreRAAntiHints.h"
+#include "GCNSubtarget.h"
+#include "SIInstrInfo.h"
+#include "SIRegisterInfo.h"
+#include "llvm/CodeGen/LiveIntervals.h"
+#include "llvm/CodeGen/MachineRegisterInfo.h"
+#include "llvm/CodeGen/SlotIndexes.h"
+#include "llvm/CodeGen/TargetSchedule.h"
+
+using namespace llvm;
+using namespace llvm::AMDGPU;
+
+#define DEBUG_TYPE "amdgpu-anti-hints"
+
+namespace HC = llvm::AMDGPU::HazardClass;
+
+enum class AntiHintRule {
+  None,
+  MFMAWAW,
+  MFMAWAR,
+  All,
+};
+
+static cl::bits<AntiHintRule> AntiHintRuleSelection(
+    "amdgpu-anti-hints-rules", cl::Hidden, cl::CommaSeparated,
+    cl::desc("Anti-hints rules to select."),
+    cl::values(clEnumValN(AntiHintRule::None, "none", "Select no rules"),
+               clEnumValN(AntiHintRule::MFMAWAW, "mfma-waw",
+                          "MFMA destination write-after-write"),
+               clEnumValN(AntiHintRule::MFMAWAR, "mfma-war",
+                          "XDL MFMA src2 write-after-read"),
+               clEnumValN(AntiHintRule::All, "all",
+                          "Select all rules (default)")));
+
+namespace {
+
+// Classify the MI into a HazardClassMask.
+HazardClassMask getInstHazardClass(const MachineInstr &MI,
+                                   const HazardContext &Ctx) {
+  const SIInstrInfo &TII = *Ctx.TII;
+  HazardClassMask Mask = HC::None;
+
+  if (TII.isLDSDMA(MI))
+    Mask = HC::VALU | HC::VMEM | HC::DS;
+  else if (TII.isWMMA(MI) || SIInstrInfo::isSWMMAC(MI))
+    Mask = HC::WMMA;
+  else if (TII.isMFMA(MI))
+    Mask = HC::MFMA;
+  else if (SIInstrInfo::isTRANS(MI))
+    Mask = HC::TRANS;
+  else if (SIInstrInfo::isVALU(MI, /*AllowLDSDMA=*/true))
+    Mask = HC::VALU;
+  else if (TII.isDS(MI))
+    Mask = HC::DS;
+  else if (TII.isVMEM(MI))
+    Mask = HC::VMEM;
+  else if (TII.isSMRD(MI))
+    Mask = HC::SMEM;
+  else if (TII.isEXP(MI))
+    Mask = HC::EXP;
+  else if (SIInstrInfo::isSALU(MI))
+    Mask = HC::SALU;
+
+  return Mask;
+}
+
+void collectOperandRegs(const MachineInstr &MI, HazardOperand Op,
+                        const HazardContext &Ctx,
+                        SmallVectorImpl<Register> &Out) {
+  const SIInstrInfo &TII = *Ctx.TII;
+  auto Add = [&](const MachineOperand *MO) {
+    if (MO && MO->isReg() && MO->getReg().isVirtual() &&
+        Ctx.TRI->hasVGPRs(Ctx.MRI->getRegClass(MO->getReg())))
+      Out.push_back(MO->getReg());
+  };
+  auto Named = [&](AMDGPU::OpName N) { Add(TII.getNamedOperand(MI, N)); };
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arsenm wrote:

I'd just inline this 

https://github.com/llvm/llvm-project/pull/218075