[llvm] [Mips] Enable generic bitfield extract preparation (PR #226491)

[Jiaxun Yang via llvm-commits]

https://github.com/FlyGoat created https://github.com/llvm/llvm-project/pull/226491

Enable CodeGenPrepare's shift sinking when the subtarget supports bitfield extract instructions. This exposes shift-and-mask patterns across basic blocks to the existing MIPS extract combine.

Use hasExtractInsert() to keep this disabled for pre-r2 targets and MIPS16. Add a minimal cross-block regression case to extins.ll.

>From b149ffaf0eda04613954a09bda2ef990d210bc21 Mon Sep 17 00:00:00 2001
From: Jiaxun Yang <jiaxun.yang at flygoat.com>
Date: Fri, 25 Sep 2026 14:20:31 +0100
Subject: [PATCH] [Mips] Enable generic bitfield extract preparation

Enable CodeGenPrepare's shift sinking when the subtarget supports bitfield
extract instructions. This exposes shift-and-mask patterns across basic
blocks to the existing MIPS extract combine.

Use hasExtractInsert() to keep this disabled for pre-r2 targets and MIPS16.
Add a minimal cross-block regression case to extins.ll.
---
 llvm/lib/Target/Mips/MipsISelLowering.cpp |  3 +++
 llvm/test/CodeGen/Mips/extins.ll          | 18 ++++++++++++++++++
 2 files changed, 21 insertions(+)

diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp
index a5f3cda3bc8a30..be89192121ac9c 100644
--- a/llvm/lib/Target/Mips/MipsISelLowering.cpp
+++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp
@@ -422,6 +422,9 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM,
                        ISD::OR, ISD::ADD, ISD::SUB, ISD::AssertZext, ISD::SHL,
                        ISD::SIGN_EXTEND});
 
+  // Sink shifts into their users' blocks to expose extract patterns.
+  setHasExtractBitsInsn(Subtarget.hasExtractInsert());
+
   // R5900 has no LL/SC instructions for atomic operations
   if (Subtarget.isR5900())
     setMaxAtomicSizeInBitsSupported(0);
diff --git a/llvm/test/CodeGen/Mips/extins.ll b/llvm/test/CodeGen/Mips/extins.ll
index e5c66602450e8f..02bf346ad1fde7 100644
--- a/llvm/test/CodeGen/Mips/extins.ll
+++ b/llvm/test/CodeGen/Mips/extins.ll
@@ -22,3 +22,21 @@ entry:
   store i32 %or, ptr %d, align 4
   ret void
 }
+
+; Sink the shared shift to combine it with the mask in a successor block.
+define i32 @ext_in_successor(i32 %s, i1 zeroext %cond) {
+; 32R2-LABEL: ext_in_successor:
+; 32R2: ext ${{[0-9]+}}, $4, 5, 9
+; 16-LABEL: ext_in_successor:
+; 16-NOT: ext ${{[0-9]+}}
+entry:
+  %shr = lshr i32 %s, 5
+  br i1 %cond, label %extract, label %full
+
+extract:
+  %masked = and i32 %shr, 511
+  ret i32 %masked
+
+full:
+  ret i32 %shr
+}