[llvm] ARM: Remove cached TargetABI from ARMBaseTargetMachine (PR #226482)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 06:18:44 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/226482
This cannot account for the "target-abi" module flag, so
let the uses query that. ARMElfTargetObjectFile was the one user of
this value, so this failed to respect the module flag.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
>From 7be97a982cb32276ce367a547fb1908dfbb54d7d Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 25 Sep 2026 14:44:05 +0200
Subject: [PATCH] ARM: Remove cached TargetABI from ARMBaseTargetMachine
This cannot account for the "target-abi" module flag, so
let the uses query that. ARMElfTargetObjectFile was the one user of
this value, so this failed to respect the module flag.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
---
llvm/lib/Target/ARM/ARMTargetMachine.cpp | 5 ++---
llvm/lib/Target/ARM/ARMTargetMachine.h | 18 ------------------
llvm/lib/Target/ARM/ARMTargetObjectFile.cpp | 20 +++++++++++++-------
llvm/lib/Target/ARM/ARMTargetObjectFile.h | 2 ++
llvm/test/CodeGen/ARM/module-target-abi.ll | 13 ++++++++++++-
5 files changed, 29 insertions(+), 29 deletions(-)
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.cpp b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
index 667f6c00d59967..e1153ed22ab918 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.cpp
@@ -155,7 +155,6 @@ ARMBaseTargetMachine::ARMBaseTargetMachine(const Target &T, const Triple &TT,
: CodeGenTargetMachineImpl(T, TT, CPU, FS, Options,
getEffectiveRelocModel(TT, RM),
getEffectiveCodeModel(CM, CodeModel::Small), OL),
- TargetABI(ARM::computeTargetABI(TT, Options.MCOptions.ABIName)),
TLOF(createTLOF(getTargetTriple())), isLittle(TT.isLittleEndian()) {
if (TT.isOSBinFormatMachO()) {
@@ -224,7 +223,7 @@ FloatABI::ABIType ARMBaseTargetMachine::getFloatABI(const Module &M) const {
// With no explicit ABI, an explicit -target-abi=aapcs16 forces hard float
// even on triples whose default float ABI is soft (the triple default only
// detects AAPCS16 when it is the triple's own default ABI).
- if (TargetABI == ARM::ARM_ABI_AAPCS16)
+ if (getEffectiveABI(M) == ARM::ARM_ABI_AAPCS16)
return FloatABI::Hard;
// Otherwise fall back to the ABI implied by the target triple.
return M.getTargetTriple().getDefaultFloatABI();
@@ -234,7 +233,7 @@ ARM::ARMABI ARMBaseTargetMachine::getEffectiveABI(const Module &M) const {
// Consistency of "target-abi" and -target-abi is validated elsewhere.
if (const auto *MD = cast_or_null<MDString>(M.getModuleFlag("target-abi")))
return ARM::computeTargetABI(TargetTriple, MD->getString());
- return TargetABI;
+ return ARM::computeTargetABI(TargetTriple, Options.MCOptions.getABIName());
}
const ARMSubtarget *
diff --git a/llvm/lib/Target/ARM/ARMTargetMachine.h b/llvm/lib/Target/ARM/ARMTargetMachine.h
index 1771fcaa26c663..51960634bf993c 100644
--- a/llvm/lib/Target/ARM/ARMTargetMachine.h
+++ b/llvm/lib/Target/ARM/ARMTargetMachine.h
@@ -27,9 +27,6 @@
namespace llvm {
class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
-public:
- ARM::ARMABI TargetABI;
-
protected:
std::unique_ptr<TargetLoweringObjectFile> TLOF;
bool isLittle;
@@ -73,21 +70,6 @@ class ARMBaseTargetMachine : public CodeGenTargetMachineImpl {
return TLOF.get();
}
- bool isAPCS_ABI() const {
- assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
- return TargetABI == ARM::ARM_ABI_APCS;
- }
-
- bool isAAPCS_ABI() const {
- assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
- return TargetABI == ARM::ARM_ABI_AAPCS || TargetABI == ARM::ARM_ABI_AAPCS16;
- }
-
- bool isAAPCS16_ABI() const {
- assert(TargetABI != ARM::ARM_ABI_UNKNOWN);
- return TargetABI == ARM::ARM_ABI_AAPCS16;
- }
-
bool targetSchedulesPostRAScheduling() const override { return true; };
MachineFunctionInfo *
diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp b/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
index d42a6484076d92..44040be9c8db9e 100644
--- a/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
+++ b/llvm/lib/Target/ARM/ARMTargetObjectFile.cpp
@@ -35,17 +35,12 @@ ARMElfTargetObjectFile::ARMElfTargetObjectFile() {
void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
const TargetMachine &TM) {
- const ARMBaseTargetMachine &ARM_TM = static_cast<const ARMBaseTargetMachine &>(TM);
- bool isAAPCS_ABI = ARM_TM.TargetABI == ARM::ARMABI::ARM_ABI_AAPCS;
+ const ARMBaseTargetMachine &ARM_TM =
+ static_cast<const ARMBaseTargetMachine &>(TM);
bool genExecuteOnly =
ARM_TM.getMCSubtargetInfo().hasFeature(ARM::FeatureExecuteOnly);
TargetLoweringObjectFileELF::Initialize(Ctx, TM);
- InitializeELF(isAAPCS_ABI);
-
- if (isAAPCS_ABI) {
- LSDASection = nullptr;
- }
// Make code section unreadable when in execute-only mode
if (genExecuteOnly) {
@@ -60,6 +55,17 @@ void ARMElfTargetObjectFile::Initialize(MCContext &Ctx,
}
}
+void ARMElfTargetObjectFile::getModuleMetadata(Module &M) {
+ TargetLoweringObjectFileELF::getModuleMetadata(M);
+
+ const auto &ARM_TM = static_cast<const ARMBaseTargetMachine &>(*TM);
+ bool isAAPCS_ABI = ARM_TM.getEffectiveABI(M) == ARM::ARMABI::ARM_ABI_AAPCS;
+ InitializeELF(isAAPCS_ABI);
+
+ if (isAAPCS_ABI)
+ LSDASection = nullptr;
+}
+
MCRegister ARMElfTargetObjectFile::getStaticBase() const { return ARM::R9; }
const MCExpr *ARMElfTargetObjectFile::getIndirectSymViaGOTPCRel(
diff --git a/llvm/lib/Target/ARM/ARMTargetObjectFile.h b/llvm/lib/Target/ARM/ARMTargetObjectFile.h
index e2cce9b79e0574..02cd138cf5c04d 100644
--- a/llvm/lib/Target/ARM/ARMTargetObjectFile.h
+++ b/llvm/lib/Target/ARM/ARMTargetObjectFile.h
@@ -20,6 +20,8 @@ class ARMElfTargetObjectFile : public TargetLoweringObjectFileELF {
ARMElfTargetObjectFile();
void Initialize(MCContext &Ctx, const TargetMachine &TM) override;
+ void getModuleMetadata(Module &M) override;
+
MCRegister getStaticBase() const override;
const MCExpr *getIndirectSymViaGOTPCRel(const GlobalValue *GV,
diff --git a/llvm/test/CodeGen/ARM/module-target-abi.ll b/llvm/test/CodeGen/ARM/module-target-abi.ll
index 0cb41cae6c67cd..72c59ad85c487e 100644
--- a/llvm/test/CodeGen/ARM/module-target-abi.ll
+++ b/llvm/test/CodeGen/ARM/module-target-abi.ll
@@ -1,6 +1,7 @@
; The "target-abi" module flag selects the ABI used for codegen. APCS uses
; 4-byte stack alignment while AAPCS uses 8-byte alignment, which is observable
-; in the emitted prologue. The flag drives this with no -target-abi option.
+; in the emitted prologue. AAPCS also selects .init_array over .ctors. The flag
+; drives both with no -target-abi option.
; RUN: split-file %s %t
; RUN: llc -mtriple=armv7-none-eabi -filetype=asm < %t/apcs.ll | FileCheck %s --check-prefix=APCS
; RUN: llc -mtriple=armv7-none-eabi -filetype=asm < %t/aapcs.ll | FileCheck %s --check-prefix=AAPCS
@@ -8,23 +9,33 @@
;--- apcs.ll
; APCS: push {lr}
; APCS: sub sp, sp, #4
+; APCS: .section .ctors,"aw",%progbits
declare void @use(ptr)
define void @f() {
%a = alloca i32
call void @use(ptr %a)
ret void
}
+define void @ctor() {
+ ret void
+}
+ at llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @ctor, ptr null }]
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"target-abi", !"apcs"}
;--- aapcs.ll
; AAPCS: push {r11, lr}
; AAPCS: sub sp, sp, #8
+; AAPCS: .section .init_array,"aw",%init_array
declare void @use(ptr)
define void @f() {
%a = alloca i32
call void @use(ptr %a)
ret void
}
+define void @ctor() {
+ ret void
+}
+ at llvm.global_ctors = appending global [1 x { i32, ptr, ptr }] [{ i32, ptr, ptr } { i32 65535, ptr @ctor, ptr null }]
!llvm.module.flags = !{!0}
!0 = !{i32 1, !"target-abi", !"aapcs"}
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