[llvm] SystemZ: Mark unread CC defs dead at build time (PR #226434)
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 03:53:42 PDT 2026
https://github.com/arsenm created https://github.com/llvm/llvm-project/pull/226434
The custom inserters for the subword atomic pseudos and for probed
allocas, plus the inline stack probe emitted by frame lowering, build
instructions whose CC def is never read. Set the dead flags.
Marking the RISBG32 in the subword cmpxchg loop dead lets MachineSink
move it out of the compare block and into the store block, so it is
skipped when the comparison fails.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
>From 4d866ffecc7bb32ba3ad1dfcd9d51cf3291a1b49 Mon Sep 17 00:00:00 2001
From: Matt Arsenault <Matthew.Arsenault at amd.com>
Date: Fri, 25 Sep 2026 11:53:07 +0200
Subject: [PATCH] SystemZ: Mark unread CC defs dead at build time
The custom inserters for the subword atomic pseudos and for probed
allocas, plus the inline stack probe emitted by frame lowering, build
instructions whose CC def is never read. Set the dead flags.
Marking the RISBG32 in the subword cmpxchg loop dead lets MachineSink
move it out of the compare block and into the store block, so it is
skipped when the comparison fails.
Co-Authored-By: Claude Opus 5 <noreply at anthropic.com>
---
.../Target/SystemZ/SystemZFrameLowering.cpp | 9 ++-
.../Target/SystemZ/SystemZISelLowering.cpp | 74 ++++++++++++------
.../test/CodeGen/SystemZ/atomicrmw-fadd-04.ll | 6 +-
llvm/test/CodeGen/SystemZ/cmpxchg-01.ll | 20 ++---
llvm/test/CodeGen/SystemZ/cmpxchg-02.ll | 24 +++---
llvm/test/CodeGen/SystemZ/dead-cc-defs.ll | 75 +++++++++++++++++++
6 files changed, 159 insertions(+), 49 deletions(-)
create mode 100644 llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
diff --git a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
index 14688a53c1c63..145db33a41c74 100644
--- a/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZFrameLowering.cpp
@@ -801,9 +801,12 @@ void SystemZELFFrameLowering::inlineStackProbe(
MachineMemOperand *MMO = MF.getMachineMemOperand(MachinePointerInfo(),
MachineMemOperand::MOVolatile | MachineMemOperand::MOLoad, 8, Align(1));
BuildMI(InsMBB, InsPt, DL, ZII->get(SystemZ::CG))
- .addReg(SystemZ::R0D, RegState::Undef)
- .addReg(SystemZ::R15D).addImm(Size - 8).addReg(0)
- .addMemOperand(MMO);
+ .addReg(SystemZ::R0D, RegState::Undef)
+ .addReg(SystemZ::R15D)
+ .addImm(Size - 8)
+ .addReg(0)
+ .setOperandDead(4)
+ .addMemOperand(MMO);
};
bool StoreBackchain = MF.getSubtarget<SystemZSubtarget>().hasBackChain();
diff --git a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
index 8e621aafe27d2..039aff408b517 100644
--- a/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
+++ b/llvm/lib/Target/SystemZ/SystemZISelLowering.cpp
@@ -10235,21 +10235,31 @@ MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadBinary(
if (Invert) {
// Perform the operation normally and then invert every bit of the field.
Register Tmp = MRI.createVirtualRegister(&SystemZ::GR32BitRegClass);
- BuildMI(MBB, DL, TII->get(BinOpcode), Tmp).addReg(RotatedOldVal).add(Src2);
+ BuildMI(MBB, DL, TII->get(BinOpcode), Tmp)
+ .addReg(RotatedOldVal)
+ .add(Src2)
+ .setOperandDead(3);
// XILF with the upper BitSize bits set.
BuildMI(MBB, DL, TII->get(SystemZ::XILF), RotatedNewVal)
- .addReg(Tmp).addImm(-1U << (32 - BitSize));
+ .addReg(Tmp)
+ .addImm(-1U << (32 - BitSize))
+ .setOperandDead(3);
} else if (BinOpcode)
// A simply binary operation.
BuildMI(MBB, DL, TII->get(BinOpcode), RotatedNewVal)
.addReg(RotatedOldVal)
- .add(Src2);
+ .add(Src2)
+ .setOperandDead(3);
else
// Use RISBG to rotate Src2 into position and use it to replace the
// field in RotatedOldVal.
BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedNewVal)
- .addReg(RotatedOldVal).addReg(Src2.getReg())
- .addImm(32).addImm(31 + BitSize).addImm(32 - BitSize);
+ .addReg(RotatedOldVal)
+ .addReg(Src2.getReg())
+ .addImm(32)
+ .addImm(31 + BitSize)
+ .addImm(32 - BitSize)
+ .setOperandDead(6);
BuildMI(MBB, DL, TII->get(SystemZ::RLL), NewVal)
.addReg(RotatedNewVal).addReg(NegBitShift).addImm(0);
BuildMI(MBB, DL, TII->get(CSOpcode), Dest)
@@ -10339,8 +10349,12 @@ MachineBasicBlock *SystemZTargetLowering::emitAtomicLoadMinMax(
// # fall through to UpdateMBB
MBB = UseAltMBB;
BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RotatedAltVal)
- .addReg(RotatedOldVal).addReg(Src2)
- .addImm(32).addImm(31 + BitSize).addImm(0);
+ .addReg(RotatedOldVal)
+ .addReg(Src2)
+ .addImm(32)
+ .addImm(31 + BitSize)
+ .addImm(0)
+ .setOperandDead(6);
MBB->addSuccessor(UpdateMBB);
// UpdateMBB:
@@ -10447,7 +10461,12 @@ SystemZTargetLowering::emitAtomicCmpSwapW(MachineInstr &MI,
BuildMI(MBB, DL, TII->get(SystemZ::RLL), OldValRot)
.addReg(OldVal).addReg(BitShift).addImm(BitSize);
BuildMI(MBB, DL, TII->get(SystemZ::RISBG32), RetrySwapVal)
- .addReg(SwapVal).addReg(OldValRot).addImm(32).addImm(63 - BitSize).addImm(0);
+ .addReg(SwapVal)
+ .addReg(OldValRot)
+ .addImm(32)
+ .addImm(63 - BitSize)
+ .addImm(0)
+ .setOperandDead(6);
BuildMI(MBB, DL, TII->get(ZExtOpcode), Dest)
.addReg(OldValRot);
BuildMI(MBB, DL, TII->get(SystemZ::CR))
@@ -10811,7 +10830,9 @@ SystemZTargetLowering::emitMemMemWrapper(MachineInstr &MI,
BuildMI(MBB, DL, TII->get(SystemZ::LA), NextSrcReg)
.addReg(ThisSrcReg).addImm(256).addReg(0);
BuildMI(MBB, DL, TII->get(SystemZ::AGHI), NextCountReg)
- .addReg(ThisCountReg).addImm(-1);
+ .addReg(ThisCountReg)
+ .addImm(-1)
+ .setOperandDead(3);
BuildMI(MBB, DL, TII->get(SystemZ::CGHI))
.addReg(NextCountReg).addImm(0);
BuildMI(MBB, DL, TII->get(SystemZ::BRC))
@@ -11110,14 +11131,20 @@ MachineBasicBlock *SystemZTargetLowering::emitProbedAlloca(
// J LoopTestMBB
MBB = LoopBodyMBB;
BuildMI(MBB, DL, TII->get(SystemZ::SLGFI), IncReg)
- .addReg(PHIReg)
- .addImm(ProbeSize);
+ .addReg(PHIReg)
+ .addImm(ProbeSize)
+ .setOperandDead(3);
BuildMI(MBB, DL, TII->get(SystemZ::SLGFI), SystemZ::R15D)
- .addReg(SystemZ::R15D)
- .addImm(ProbeSize);
- BuildMI(MBB, DL, TII->get(SystemZ::CG)).addReg(SystemZ::R15D)
- .addReg(SystemZ::R15D).addImm(ProbeSize - 8).addReg(0)
- .setMemRefs(VolLdMMO);
+ .addReg(SystemZ::R15D)
+ .addImm(ProbeSize)
+ .setOperandDead(3);
+ BuildMI(MBB, DL, TII->get(SystemZ::CG))
+ .addReg(SystemZ::R15D)
+ .addReg(SystemZ::R15D)
+ .addImm(ProbeSize - 8)
+ .addReg(0)
+ .setOperandDead(4)
+ .setMemRefs(VolLdMMO);
BuildMI(MBB, DL, TII->get(SystemZ::J)).addMBB(LoopTestMBB);
MBB->addSuccessor(LoopTestMBB);
@@ -11138,11 +11165,16 @@ MachineBasicBlock *SystemZTargetLowering::emitProbedAlloca(
// # fallthrough to DoneMBB
MBB = TailMBB;
BuildMI(MBB, DL, TII->get(SystemZ::SLGR), SystemZ::R15D)
- .addReg(SystemZ::R15D)
- .addReg(PHIReg);
- BuildMI(MBB, DL, TII->get(SystemZ::CG)).addReg(SystemZ::R15D)
- .addReg(SystemZ::R15D).addImm(-8).addReg(PHIReg)
- .setMemRefs(VolLdMMO);
+ .addReg(SystemZ::R15D)
+ .addReg(PHIReg)
+ .setOperandDead(3);
+ BuildMI(MBB, DL, TII->get(SystemZ::CG))
+ .addReg(SystemZ::R15D)
+ .addReg(SystemZ::R15D)
+ .addImm(-8)
+ .addReg(PHIReg)
+ .setOperandDead(4)
+ .setMemRefs(VolLdMMO);
MBB->addSuccessor(DoneMBB);
// DoneMBB
diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
index a0869e13a013d..f21c2ff6d30dd 100644
--- a/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
+++ b/llvm/test/CodeGen/SystemZ/atomicrmw-fadd-04.ll
@@ -53,13 +53,13 @@ define half @f1(ptr %src, half %b) {
; CHECK-NEXT: .LBB0_3: # %atomicrmw.start
; CHECK-NEXT: # Parent Loop BB0_2 Depth=1
; CHECK-NEXT: # => This Inner Loop Header: Depth=2
-; CHECK-NEXT: rll %r3, %r0, 16(%r13)
-; CHECK-NEXT: risbg %r1, %r3, 32, 47, 0
-; CHECK-NEXT: llhr %r3, %r3
+; CHECK-NEXT: rll %r4, %r0, 16(%r13)
+; CHECK-NEXT: llhr %r3, %r4
; CHECK-NEXT: cr %r3, %r2
; CHECK-NEXT: jlh .LBB0_1
; CHECK-NEXT: # %bb.4: # %atomicrmw.start
; CHECK-NEXT: # in Loop: Header=BB0_3 Depth=2
+; CHECK-NEXT: risbg %r1, %r4, 32, 47, 0
; CHECK-NEXT: rll %r4, %r1, -16(%r11)
; CHECK-NEXT: cs %r0, %r4, 0(%r12)
; CHECK-NEXT: jl .LBB0_3
diff --git a/llvm/test/CodeGen/SystemZ/cmpxchg-01.ll b/llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
index 79db0157b502f..e5c5a49d6c21b 100644
--- a/llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
+++ b/llvm/test/CodeGen/SystemZ/cmpxchg-01.ll
@@ -17,10 +17,10 @@ define i8 @f1(i8 %dummy, ptr %src, i8 %cmp, i8 %swap) {
; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN-DAG: llcr %r4, %r4
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
-; CHECK-MAIN: rll %r2, [[OLD]], 8(%r3)
-; CHECK-MAIN: risbg %r5, %r2, 32, 55, 0
-; CHECK-MAIN: llcr %r2, %r2
+; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r3)
+; CHECK-MAIN: llcr %r2, [[TMP]]
; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
+; CHECK-MAIN: risbg %r5, [[TMP]], 32, 55, 0
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK-MAIN: jl [[LOOP]]
@@ -65,10 +65,10 @@ define i32 @f3(i8 %dummy, ptr %src, i8 %cmp, i8 %swap) {
; CHECK-MAIN-DAG: llcr %r2, %r4
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r3)
-; CHECK-MAIN: risbg %r5, [[TMP]], 32, 55, 0
; CHECK-MAIN: llcr [[TMP2:%r[0-9]+]], [[TMP]]
; CHECK-MAIN: cr [[TMP2]], %r2
; CHECK-MAIN: jlh [[EXIT:\.[^ ]*]]
+; CHECK-MAIN: risbg %r5, [[TMP]], 32, 55, 0
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -8({{%r[1-9]+}})
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK-MAIN: jl [[LOOP]]
@@ -102,10 +102,10 @@ declare void @g()
; CHECK-MAIN-DAG: llcr %r3, %r3
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r2)
-; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0
-; CHECK-MAIN: llcr [[TMP]], [[TMP]]
-; CHECK-MAIN: cr [[TMP]], %r3
+; CHECK-MAIN: llcr [[TMP2:%r[0-9]+]], [[TMP]]
+; CHECK-MAIN: cr [[TMP2]], %r3
; CHECK-MAIN: jlh [[EXIT:\.[^ ]*]]
+; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r4, -8({{%r[1-9]+}})
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK-MAIN: jl [[LOOP]]
@@ -141,10 +141,10 @@ exit:
; CHECK-MAIN-DAG: llcr %r3, %r3
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 8(%r2)
-; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0
-; CHECK-MAIN: llcr [[TMP]], [[TMP]]
-; CHECK-MAIN: cr [[TMP]], %r3
+; CHECK-MAIN: llcr [[TMP2:%r[0-9]+]], [[TMP]]
+; CHECK-MAIN: cr [[TMP2]], %r3
; CHECK-MAIN: jlh [[EXIT:\.[^ ]*]]
+; CHECK-MAIN: risbg %r4, [[TMP]], 32, 55, 0
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r4, -8({{%r[1-9]+}})
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK-MAIN: jl [[LOOP]]
diff --git a/llvm/test/CodeGen/SystemZ/cmpxchg-02.ll b/llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
index 706386854dd13..326ecae70f8ce 100644
--- a/llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
+++ b/llvm/test/CodeGen/SystemZ/cmpxchg-02.ll
@@ -17,10 +17,10 @@ define i16 @f1(i16 %dummy, ptr %src, i16 %cmp, i16 %swap) {
; CHECK-MAIN-DAG: l [[OLD:%r[0-9]+]], 0([[RISBG]])
; CHECK-MAIN-DAG: llhr %r4, %r4
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
-; CHECK-MAIN: rll %r2, [[OLD]], 16(%r3)
-; CHECK-MAIN: risbg %r5, %r2, 32, 47, 0
-; CHECK-MAIN: llhr %r2, %r2
+; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 16(%r3)
+; CHECK-MAIN: llhr %r2, [[TMP]]
; CHECK-MAIN: crjlh %r2, %r4, [[EXIT:\.[^ ]*]]
+; CHECK-MAIN: risbg %r5, [[TMP]], 32, 47, 0
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}})
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK-MAIN: jl [[LOOP]]
@@ -65,10 +65,10 @@ define i32 @f3(i16 %dummy, ptr %src, i16 %cmp, i16 %swap) {
; CHECK-MAIN-DAG: llhr %r2, %r4
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 16(%r3)
-; CHECK-MAIN: risbg %r5, [[TMP]], 32, 47, 0
-; CHECK-MAIN: llhr %r14, %r14
-; CHECK-MAIN: cr [[TMP]], %r2
+; CHECK-MAIN: llhr [[TMP2:%r[0-9]+]], [[TMP]]
+; CHECK-MAIN: cr [[TMP2]], %r2
; CHECK-MAIN: jlh [[EXIT:\.[^ ]*]]
+; CHECK-MAIN: risbg %r5, [[TMP]], 32, 47, 0
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r5, -16({{%r[1-9]+}})
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK-MAIN: jl [[LOOP]]
@@ -101,10 +101,10 @@ declare void @g()
; CHECK-MAIN-DAG: llhr %r3, %r3
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 16(%r2)
-; CHECK-MAIN: risbg %r4, [[TMP]], 32, 47, 0
-; CHECK-MAIN: llhr %r14, %r14
-; CHECK-MAIN: cr [[TMP]], %r3
+; CHECK-MAIN: llhr [[TMP2:%r[0-9]+]], [[TMP]]
+; CHECK-MAIN: cr [[TMP2]], %r3
; CHECK-MAIN: jlh [[EXIT:\.[^ ]*]]
+; CHECK-MAIN: risbg %r4, [[TMP]], 32, 47, 0
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r4, -16({{%r[1-9]+}})
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK-MAIN: jl [[LOOP]]
@@ -140,10 +140,10 @@ exit:
; CHECK-MAIN-DAG: llhr %r3, %r3
; CHECK-MAIN: [[LOOP:\.[^ ]*]]:
; CHECK-MAIN: rll [[TMP:%r[0-9]+]], [[OLD]], 16(%r2)
-; CHECK-MAIN: risbg %r4, [[TMP]], 32, 47, 0
-; CHECK-MAIN: llhr %r14, %r14
-; CHECK-MAIN: cr [[TMP]], %r3
+; CHECK-MAIN: llhr [[TMP2:%r[0-9]+]], [[TMP]]
+; CHECK-MAIN: cr [[TMP2]], %r3
; CHECK-MAIN: jlh [[EXIT:\.[^ ]*]]
+; CHECK-MAIN: risbg %r4, [[TMP]], 32, 47, 0
; CHECK-MAIN: rll [[NEW:%r[0-9]+]], %r4, -16({{%r[1-9]+}})
; CHECK-MAIN: cs [[OLD]], [[NEW]], 0([[RISBG]])
; CHECK-MAIN: jl [[LOOP]]
diff --git a/llvm/test/CodeGen/SystemZ/dead-cc-defs.ll b/llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
new file mode 100644
index 0000000000000..c639a4a1ba961
--- /dev/null
+++ b/llvm/test/CodeGen/SystemZ/dead-cc-defs.ll
@@ -0,0 +1,75 @@
+; Check that custom inserters and frame lowering mark the CC defs of
+; instructions whose condition code is never read as dead.
+
+; RUN: llc -mtriple=s390x-linux-gnu -stop-after=finalize-isel -o - %s | FileCheck %s
+; RUN: llc -mtriple=s390x-linux-gnu -stop-after=prolog-epilog -o - %s | FileCheck -check-prefix=PEI %s
+
+; CHECK-LABEL: name: atomicrmw_and_i8
+; CHECK: NR {{.*}}, implicit-def dead $cc
+define i8 @atomicrmw_and_i8(ptr %src, i8 %b) {
+ %res = atomicrmw and ptr %src, i8 %b seq_cst
+ ret i8 %res
+}
+
+; CHECK-LABEL: name: atomicrmw_nand_i8
+; CHECK: NR {{.*}}, implicit-def dead $cc
+; CHECK: XILF {{.*}}, implicit-def dead $cc
+define i8 @atomicrmw_nand_i8(ptr %src, i8 %b) {
+ %res = atomicrmw nand ptr %src, i8 %b seq_cst
+ ret i8 %res
+}
+
+; CHECK-LABEL: name: atomicrmw_xchg_i8
+; CHECK: RISBG32 {{.*}}, implicit-def dead $cc
+define i8 @atomicrmw_xchg_i8(ptr %src, i8 %b) {
+ %res = atomicrmw xchg ptr %src, i8 %b seq_cst
+ ret i8 %res
+}
+
+; CHECK-LABEL: name: atomicrmw_max_i8
+; CHECK: RISBG32 {{.*}}, implicit-def dead $cc
+define i8 @atomicrmw_max_i8(ptr %src, i8 %b) {
+ %res = atomicrmw max ptr %src, i8 %b seq_cst
+ ret i8 %res
+}
+
+; CHECK-LABEL: name: cmpxchg_i8
+; CHECK: RISBG32 {{.*}}, implicit-def dead $cc
+define i8 @cmpxchg_i8(ptr %src, i8 %cmp, i8 %swap) {
+ %pair = cmpxchg ptr %src, i8 %cmp, i8 %swap seq_cst seq_cst
+ %res = extractvalue { i8, i1 } %pair, 0
+ ret i8 %res
+}
+
+; CHECK-LABEL: name: memcpy_variable
+; CHECK: AGHI {{.*}}, -1, implicit-def dead $cc
+; CHECK: CGHI {{.*}}, 0, implicit-def $cc
+define void @memcpy_variable(ptr %dest, ptr %src, i64 %len) {
+ call void @llvm.memcpy.p0.p0.i64(ptr %dest, ptr %src, i64 %len, i1 false)
+ ret void
+}
+
+; CHECK-LABEL: name: probed_dynamic_alloca
+; CHECK: CLGFI {{.*}}, 4096, implicit-def $cc
+; CHECK: SLGFI {{.*}}, 4096, implicit-def dead $cc
+; CHECK: $r15d = SLGFI $r15d, 4096, implicit-def dead $cc
+; CHECK: CG $r15d, $r15d, 4088, $noreg, implicit-def dead $cc
+; CHECK: CGHI {{.*}}, 0, implicit-def $cc
+; CHECK: $r15d = SLGR $r15d, {{.*}}, implicit-def dead $cc
+; CHECK: CG $r15d, $r15d, -8, {{.*}}, implicit-def dead $cc
+define ptr @probed_dynamic_alloca(i64 %len) "probe-stack"="inline-asm" {
+ %p = alloca i8, i64 %len
+ ret ptr %p
+}
+
+; PEI-LABEL: name: probed_static_alloca
+; PEI: $r15d = AGHI $r15d, -4096, implicit-def dead $cc
+; PEI: CG undef $r0d, $r15d, 4088, $noreg, implicit-def dead $cc
+define void @probed_static_alloca() "probe-stack"="inline-asm" {
+ %p = alloca [4000 x i8]
+ call void @use(ptr %p)
+ ret void
+}
+
+declare void @use(ptr)
+declare void @llvm.memcpy.p0.p0.i64(ptr, ptr, i64, i1)
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