[clang] [llvm] [AArch64] Rename memory hints to avoid clash with arm_acle.h macros (PR #226432)

[Kerry McLaughlin via llvm-commits]

https://github.com/kmclaughlin-arm created https://github.com/llvm/llvm-project/pull/226432

Renames the hints in AArch64MemoryHints.h, as HINT_STSHH_KEEP and
HINT_STSHH_STRM are already defined in arm_acle.h.

>From 772a8fc479bd138d119554009aac1d0d0f2cb877 Mon Sep 17 00:00:00 2001
From: Kerry McLaughlin <kerry.mclaughlin at arm.com>
Date: Fri, 25 Sep 2026 09:59:45 +0000
Subject: [PATCH] [AArch64] Rename memory hints to avoid clash with arm_acle.h
 macros

Renames the hints in AArch64MemoryHints.h, as HINT_STSHH_KEEP and
HINT_STSHH_STRM are already defined in arm_acle.h.
---
 clang/lib/CodeGen/TargetBuiltins/ARM.cpp        |  2 +-
 clang/lib/Sema/SemaARM.cpp                      |  2 +-
 llvm/include/llvm/Support/AArch64MemoryHints.h  | 16 ++++++++--------
 llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp |  6 +++---
 4 files changed, 13 insertions(+), 13 deletions(-)

diff --git a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
index 52a7564789fb77..56e440a2aa66fe 100644
--- a/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
+++ b/clang/lib/CodeGen/TargetBuiltins/ARM.cpp
@@ -2112,7 +2112,7 @@ static Value *EmitAtomicStoreWithHintBuiltin(CodeGenFunction &CGF,
   unsigned HintArg = Result.Val.getInt().getExtValue();
 
   // Attach the hint if valid
-  if (toAArch64MemoryHint(HintArg) != AArch64MemoryHint::HINT_NONE) {
+  if (toAArch64MemoryHint(HintArg) != AArch64MemoryHint::MEM_HINT_NONE) {
     LLVMContext &Ctx = CGM.getLLVMContext();
     MDNode *MemHint = MDNode::get(
         Ctx, {MDString::get(Ctx, "aarch64.mem_hint"),
diff --git a/clang/lib/Sema/SemaARM.cpp b/clang/lib/Sema/SemaARM.cpp
index 2bf6901bcc07f2..9c24245cfe5a12 100644
--- a/clang/lib/Sema/SemaARM.cpp
+++ b/clang/lib/Sema/SemaARM.cpp
@@ -434,7 +434,7 @@ bool SemaARM::BuiltinARMAtomicStoreHintCall(unsigned BuiltinID,
              << Hint->getType() << Hint->getSourceRange();
 
     if (llvm::toAArch64MemoryHint(HintAP->getZExtValue()) ==
-        llvm::AArch64MemoryHint::HINT_NONE) {
+        llvm::AArch64MemoryHint::MEM_HINT_NONE) {
       Diag(TheCall->getBeginLoc(), diag::warn_atomic_hint_has_invalid_hint_type)
           << *HintAP << Hint->getSourceRange();
       return false;
diff --git a/llvm/include/llvm/Support/AArch64MemoryHints.h b/llvm/include/llvm/Support/AArch64MemoryHints.h
index 44ac64e481e80b..6c93fb95535738 100644
--- a/llvm/include/llvm/Support/AArch64MemoryHints.h
+++ b/llvm/include/llvm/Support/AArch64MemoryHints.h
@@ -11,24 +11,24 @@
 
 namespace llvm {
 enum class AArch64MemoryHint {
-  HINT_NONE = 0,
-  HINT_STSHH_KEEP = 1,
-  HINT_STSHH_STRM = 2,
+  MEM_HINT_NONE = 0,
+  MEM_HINT_STSHH_KEEP = 1,
+  MEM_HINT_STSHH_STRM = 2,
 };
 
 template <typename Int> inline bool isValidAArch64MemoryHintValue(Int I) {
-  return (Int)AArch64MemoryHint::HINT_STSHH_KEEP <= I &&
-         I <= (Int)AArch64MemoryHint::HINT_STSHH_STRM;
+  return (Int)AArch64MemoryHint::MEM_HINT_STSHH_KEEP <= I &&
+         I <= (Int)AArch64MemoryHint::MEM_HINT_STSHH_STRM;
 }
 
 template <typename Int> inline AArch64MemoryHint toAArch64MemoryHint(Int I) {
   switch (I) {
   case 0:
-    return AArch64MemoryHint::HINT_STSHH_KEEP;
+    return AArch64MemoryHint::MEM_HINT_STSHH_KEEP;
   case 1:
-    return AArch64MemoryHint::HINT_STSHH_STRM;
+    return AArch64MemoryHint::MEM_HINT_STSHH_STRM;
   default:
-    return AArch64MemoryHint::HINT_NONE;
+    return AArch64MemoryHint::MEM_HINT_NONE;
   }
 }
 } // namespace llvm
diff --git a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
index ee87070c127272..3694fa70841be3 100644
--- a/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
+++ b/llvm/lib/Target/AArch64/AArch64ISelDAGToDAG.cpp
@@ -4624,7 +4624,7 @@ AArch64DAGToDAGISel::decodeMemoryHintFlags(MachineMemOperand *MMO) const {
   int MemoryHint = -1;
   const MDNode *MemCacheHint = MMO->getMemCacheHint();
   if (!MemCacheHint)
-    return AArch64MemoryHint::HINT_NONE;
+    return AArch64MemoryHint::MEM_HINT_NONE;
 
   for (unsigned I = 0; I + 1 < MemCacheHint->getNumOperands(); I += 2) {
     if (MemCacheHint->getOperand(I).equalsStr("aarch64.mem_hint")) {
@@ -4639,12 +4639,12 @@ AArch64DAGToDAGISel::decodeMemoryHintFlags(MachineMemOperand *MMO) const {
 
 bool AArch64DAGToDAGISel::isAtomicSTSHH_KEEP(SDNode *N) const {
   return decodeMemoryHintFlags(cast<MemSDNode>(N)->getMemOperand()) ==
-         AArch64MemoryHint::HINT_STSHH_KEEP;
+         AArch64MemoryHint::MEM_HINT_STSHH_KEEP;
 }
 
 bool AArch64DAGToDAGISel::isAtomicSTSHH_STRM(SDNode *N) const {
   return decodeMemoryHintFlags(cast<MemSDNode>(N)->getMemOperand()) ==
-         AArch64MemoryHint::HINT_STSHH_STRM;
+         AArch64MemoryHint::MEM_HINT_STSHH_STRM;
 }
 
 bool AArch64DAGToDAGISel::SelectSVEAddSubImm(SDValue N, MVT VT, SDValue &Imm,