[clang] [llvm] [IRBuilder] Produce canonical constexpr GEPs (PR #226425)
Nikita Popov via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 03:14:10 PDT 2026
https://github.com/nikic created https://github.com/llvm/llvm-project/pull/226425
This switches the IRBuilder to always produce canonical constexpr GEPs in ptradd form, including in the case where ConstantFolder rather than TargetFolder is used.
This is done in a slightly hacky way, by passing the DataLayout from the insertion point into FoldGEP. In the future, when we start canonicalizing the non-constant GEPs as well, we'll do the canonicalization directly in IRBuilder and replace FoldGEP with FoldPtrAdd. (Though it would be even better to make IRBuilder always require a DataLayout...)
>From e5fd5c7c26acd89ec3517632b09e33b44000a65a Mon Sep 17 00:00:00 2001
From: Nikita Popov <npopov at redhat.com>
Date: Thu, 24 Sep 2026 12:21:50 +0200
Subject: [PATCH] [IRBuilder] Produce canonical constexpr GEPs
---
clang/test/Profile/branch-logical-mixed.cpp | 44 ++--
clang/test/Profile/c-captured.c | 10 +-
clang/test/Profile/c-general.c | 214 +++++++++---------
clang/test/Profile/c-ternary.c | 2 +-
clang/test/Profile/cxx-class.cpp | 12 +-
clang/test/Profile/cxx-lambda.cpp | 10 +-
clang/test/Profile/cxx-rangefor.cpp | 8 +-
clang/test/Profile/cxx-stmt-initializers.cpp | 8 +-
clang/test/Profile/cxx-templates.cpp | 4 +-
clang/test/Profile/cxx-throws.cpp | 20 +-
clang/test/Profile/objc-general.m | 4 +-
.../llvm/Analysis/InstSimplifyFolder.h | 4 +-
llvm/include/llvm/Analysis/TargetFolder.h | 4 +-
llvm/include/llvm/IR/ConstantFolder.h | 8 +-
llvm/include/llvm/IR/IRBuilder.h | 2 +-
llvm/include/llvm/IR/IRBuilderFolder.h | 3 +-
llvm/include/llvm/IR/NoFolder.h | 4 +-
llvm/lib/Transforms/Vectorize/VPlanUtils.cpp | 6 +-
...dgpu-sw-lower-lds-dynamic-lds-test-asan.ll | 8 +-
.../amdgpu-sw-lower-lds-dynamic-lds-test.ll | 8 +-
.../AMDGPU/amdgpu-sw-lower-lds-lower-all.ll | 8 +-
...lti-static-dynamic-indirect-access-asan.ll | 32 +--
...ds-multi-static-dynamic-indirect-access.ll | 32 +--
...w-lower-lds-multiple-blocks-return-asan.ll | 4 +-
...gpu-sw-lower-lds-multiple-blocks-return.ll | 4 +-
...gpu-sw-lower-lds-non-kernel-declaration.ll | 4 +-
...lds-static-dynamic-indirect-access-asan.ll | 16 +-
...ower-lds-static-dynamic-indirect-access.ll | 16 +-
...-lower-lds-static-dynamic-lds-test-asan.ll | 16 +-
...pu-sw-lower-lds-static-dynamic-lds-test.ll | 16 +-
...w-lower-lds-static-indirect-access-asan.ll | 4 +-
...tic-indirect-access-function-param-asan.ll | 4 +-
...s-static-indirect-access-function-param.ll | 4 +-
...er-lds-static-indirect-access-lower-all.ll | 4 +-
...-lds-static-indirect-access-nested-asan.ll | 24 +-
...lower-lds-static-indirect-access-nested.ll | 24 +-
...static-indirect-access-no-kernel-lds-id.ll | 4 +-
...gpu-sw-lower-lds-static-indirect-access.ll | 4 +-
.../amdgpu-sw-lower-lds-static-lds-O0.ll | 4 +-
...gpu-sw-lower-lds-static-lds-no-heap-ptr.ll | 4 +-
...mdgpu-sw-lower-lds-static-lds-test-asan.ll | 4 +-
...lds-static-lds-test-atomic-cmpxchg-asan.ll | 4 +-
...ower-lds-static-lds-test-atomicrmw-asan.ll | 4 +-
...r-lds-static-lds-test-memintrinsic-asan.ll | 24 +-
.../amdgpu-sw-lower-lds-static-lds-test.ll | 4 +-
...gpu-sw-lower-lds-static-lds-vector-ptrs.ll | 4 +-
.../AMDGPU/lower-ctor-dtor-constexpr-alias.ll | 4 +-
llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll | 4 +-
.../AMDGPU/lower-multiple-ctor-dtor.ll | 4 +-
.../bugfix_150050_data_scalarize_const_gep.ll | 20 +-
llvm/test/CodeGen/DirectX/flatten-array.ll | 8 +-
.../CodeGen/DirectX/flatten-bug-117273.ll | 4 +-
llvm/test/CodeGen/DirectX/legalize-i8.ll | 4 +-
.../DirectX/llc-vector-load-scalarize.ll | 59 ++---
.../DirectX/llc-vector-store-scalarize.ll | 2 +-
llvm/test/CodeGen/DirectX/scalar-load.ll | 2 +-
llvm/test/CodeGen/DirectX/scalar-store.ll | 23 +-
...scalarize-static-array-of-float-vectors.ll | 12 +-
.../CodeGen/RISCV/riscv-promote-constant.ll | 8 +-
.../DataFlowSanitizer/origin_abilist.ll | 26 +--
.../DataFlowSanitizer/origin_call.ll | 4 +-
.../DataFlowSanitizer/origin_load.ll | 2 +-
.../DataFlowSanitizer/origin_mem_intrinsic.ll | 2 +-
.../DataFlowSanitizer/origin_other_ops.ll | 20 +-
.../DataFlowSanitizer/origin_phi.ll | 2 +-
.../DataFlowSanitizer/origin_select.ll | 20 +-
.../DataFlowSanitizer/origin_store.ll | 12 +-
.../origin_store_threshold.ll | 2 +-
.../amdgpu-contiguous-counters.ll | 2 +-
.../conditional-counter-updates.ll | 8 +-
.../NumericalStabilitySanitizer/basic.ll | 12 +-
.../SanitizerCoverage/missing_dbg.ll | 4 +-
.../gather-scatter-opt-inseltpoison.ll | 2 +-
.../AArch64/gather-scatter-opt.ll | 2 +-
.../X86/gather-scatter-opt-inseltpoison.ll | 2 +-
.../CodeGenPrepare/X86/gather-scatter-opt.ll | 2 +-
.../test/Transforms/LowerIFunc/ifunc-alias.ll | 6 +-
.../LowerIFunc/ifunc-program-addrspace.ll | 16 +-
.../test/Transforms/LowerIFunc/lower-ifunc.ll | 32 +--
.../LowerMatrixIntrinsics/const-gep.ll | 4 +-
.../Transforms/PGOProfile/counter_promo.ll | 16 +-
.../counter_promo_exit_catchswitch.ll | 12 +-
.../PGOProfile/counter_promo_exit_merge.ll | 12 +-
.../PGOProfile/counter_promo_mexits.ll | 24 +-
.../PGOProfile/counter_promo_sampling.ll | 12 +-
.../Transforms/PGOProfile/instr_entry_bb.ll | 4 +-
llvm/test/Transforms/SROA/phi-gep.ll | 2 +-
llvm/test/tools/llvm-reduce/ifunc-alias.ll | 4 +-
.../remove-ifunc-program-addrspace.ll | 16 +-
llvm/test/tools/llvm-reduce/remove-ifunc.ll | 24 +-
90 files changed, 562 insertions(+), 555 deletions(-)
diff --git a/clang/test/Profile/branch-logical-mixed.cpp b/clang/test/Profile/branch-logical-mixed.cpp
index cdcee76c3d0cf1..933c710350f987 100644
--- a/clang/test/Profile/branch-logical-mixed.cpp
+++ b/clang/test/Profile/branch-logical-mixed.cpp
@@ -23,44 +23,44 @@ bool func() {
bool bf5 = false;
bool a = bt0 &&
- bf0 && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 10
- bt1 && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 8
- bf1 && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 6
- bt2 && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 4
- bf2; // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 2
+ bf0 && // CHECK: store {{.*}} @[[FUNC]], i64 80
+ bt1 && // CHECK: store {{.*}} @[[FUNC]], i64 64
+ bf1 && // CHECK: store {{.*}} @[[FUNC]], i64 48
+ bt2 && // CHECK: store {{.*}} @[[FUNC]], i64 32
+ bf2; // CHECK: store {{.*}} @[[FUNC]], i64 16
bool b = bt0 ||
- bf0 || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 20
- bt1 || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 18
- bf1 || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 16
- bt2 || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 14
- bf2; // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 12
+ bf0 || // CHECK: store {{.*}} @[[FUNC]], i64 160
+ bt1 || // CHECK: store {{.*}} @[[FUNC]], i64 144
+ bf1 || // CHECK: store {{.*}} @[[FUNC]], i64 128
+ bt2 || // CHECK: store {{.*}} @[[FUNC]], i64 112
+ bf2; // CHECK: store {{.*}} @[[FUNC]], i64 96
bool c = (bt0 &&
- bf0) || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 27
+ bf0) || // CHECK: store {{.*}} @[[FUNC]], i64 216
(bt1 &&
- bf1) || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 29
+ bf1) || // CHECK: store {{.*}} @[[FUNC]], i64 232
(bt2 &&
- bf2) || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 31
+ bf2) || // CHECK: store {{.*}} @[[FUNC]], i64 248
(bt3 &&
- bf3) || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 33
+ bf3) || // CHECK: store {{.*}} @[[FUNC]], i64 264
(bt4 &&
- bf4) || // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 35
+ bf4) || // CHECK: store {{.*}} @[[FUNC]], i64 280
(bf5 &&
- bf5); // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 37
+ bf5); // CHECK: store {{.*}} @[[FUNC]], i64 296
bool d = (bt0 ||
- bf0) && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 44
+ bf0) && // CHECK: store {{.*}} @[[FUNC]], i64 352
(bt1 ||
- bf1) && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 46
+ bf1) && // CHECK: store {{.*}} @[[FUNC]], i64 368
(bt2 ||
- bf2) && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 48
+ bf2) && // CHECK: store {{.*}} @[[FUNC]], i64 384
(bt3 ||
- bf3) && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 50
+ bf3) && // CHECK: store {{.*}} @[[FUNC]], i64 400
(bt4 ||
- bf4) && // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 52
+ bf4) && // CHECK: store {{.*}} @[[FUNC]], i64 416
(bt5 ||
- bf5); // CHECK: store {{.*}} @[[FUNC]], i32 0, i32 54
+ bf5); // CHECK: store {{.*}} @[[FUNC]], i64 432
return a && b && c && d;
}
diff --git a/clang/test/Profile/c-captured.c b/clang/test/Profile/c-captured.c
index e38798983b6c28..2efd139bed5adb 100644
--- a/clang/test/Profile/c-captured.c
+++ b/clang/test/Profile/c-captured.c
@@ -13,9 +13,9 @@ void debug_captured(void) {
int x = 10;
// Check both debug_captured counters, so we can do this all in one pass
-// PGOGEN: store {{.*}} @[[DCC]], i32 0, i32 1
+// PGOGEN: store {{.*}} @[[DCC]], i64 8
// PGOUSE: br {{.*}} !prof ![[DC1:[0-9]+]]
-// PGOGEN: store {{.*}} @[[DCC]], i32 0, i32 2
+// PGOGEN: store {{.*}} @[[DCC]], i64 16
// PGOUSE: br {{.*}} !prof ![[DC2:[0-9]+]]
// PGOALL: ret
@@ -23,7 +23,7 @@ void debug_captured(void) {
// PGOGEN: store {{.*}} @[[CSC]]
#pragma clang __debug captured
{
- // PGOGEN: store {{.*}} @[[CSC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[CSC]], i64 8
// PGOUSE: br {{.*}} !prof ![[CS1:[0-9]+]]
if (x) {}
// PGOALL: ret
@@ -35,10 +35,10 @@ void debug_captured(void) {
// PGOGEN: store {{.*}} @[[C1C]]
#pragma clang __debug captured
{
- // PGOGEN: store {{.*}} @[[C1C]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[C1C]], i64 8
// PGOUSE: br {{.*}} !prof ![[C11:[0-9]+]]
for (int i = 0; i < x; ++i) {}
- // PGOGEN: store {{.*}} @[[C1C]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[C1C]], i64 16
// PGOUSE: br {{.*}} !prof ![[C12:[0-9]+]]
if (x) {}
// PGOALL: ret
diff --git a/clang/test/Profile/c-general.c b/clang/test/Profile/c-general.c
index 6c865e608a037f..aea59d6316e047 100644
--- a/clang/test/Profile/c-general.c
+++ b/clang/test/Profile/c-general.c
@@ -38,15 +38,15 @@
// PGOGEN: store {{.*}} @[[SLC]]
void simple_loops(void) {
int i;
- // PGOGEN: store {{.*}} @[[SLC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[SLC]], i64 8
// PGOUSE: br {{.*}} !prof ![[SL1:[0-9]+]]
for (i = 0; i < 100; ++i) {
}
- // PGOGEN: store {{.*}} @[[SLC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[SLC]], i64 16
// PGOUSE: br {{.*}} !prof ![[SL2:[0-9]+]]
while (i > 0)
i--;
- // PGOGEN: store {{.*}} @[[SLC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[SLC]], i64 24
// PGOUSE: br {{.*}} !prof ![[SL3:[0-9]+]]
do {} while (i++ < 75);
@@ -58,35 +58,35 @@ void simple_loops(void) {
// PGOUSE-LABEL: @conditionals()
// PGOGEN: store {{.*}} @[[IFC]]
void conditionals(void) {
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[IFC]], i64 8
// PGOUSE: br {{.*}} !prof ![[IF1:[0-9]+]]
for (int i = 0; i < 100; ++i) {
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[IFC]], i64 16
// PGOUSE: br {{.*}} !prof ![[IF2:[0-9]+]]
if (i % 2) {
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[IFC]], i64 24
// PGOUSE: br {{.*}} !prof ![[IF3:[0-9]+]]
if (i) {}
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 4
+ // PGOGEN: store {{.*}} @[[IFC]], i64 32
// PGOUSE: br {{.*}} !prof ![[IF4:[0-9]+]]
} else if (i % 3) {
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 5
+ // PGOGEN: store {{.*}} @[[IFC]], i64 40
// PGOUSE: br {{.*}} !prof ![[IF5:[0-9]+]]
if (i) {}
} else {
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 6
+ // PGOGEN: store {{.*}} @[[IFC]], i64 48
// PGOUSE: br {{.*}} !prof ![[IF6:[0-9]+]]
if (i) {}
}
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 8
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 9
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 7
+ // PGOGEN: store {{.*}} @[[IFC]], i64 64
+ // PGOGEN: store {{.*}} @[[IFC]], i64 72
+ // PGOGEN: store {{.*}} @[[IFC]], i64 56
// PGOUSE: br {{.*}} !prof ![[IF7:[0-9]+]]
if (1 && i) {}
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 11
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 12
- // PGOGEN: store {{.*}} @[[IFC]], i32 0, i32 10
+ // PGOGEN: store {{.*}} @[[IFC]], i64 88
+ // PGOGEN: store {{.*}} @[[IFC]], i64 96
+ // PGOGEN: store {{.*}} @[[IFC]], i64 80
// PGOUSE: br {{.*}} !prof ![[IF8:[0-9]+]]
if (0 || i) {}
}
@@ -101,31 +101,31 @@ void conditionals(void) {
void early_exits(void) {
int i = 0;
- // PGOGEN: store {{.*}} @[[EEC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[EEC]], i64 8
// PGOUSE: br {{.*}} !prof ![[EE1:[0-9]+]]
if (i) {}
- // PGOGEN: store {{.*}} @[[EEC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[EEC]], i64 16
// PGOUSE: br {{.*}} !prof ![[EE2:[0-9]+]]
while (i < 100) {
i++;
- // PGOGEN: store {{.*}} @[[EEC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[EEC]], i64 24
// PGOUSE: br {{.*}} !prof ![[EE3:[0-9]+]]
if (i > 50)
break;
- // PGOGEN: store {{.*}} @[[EEC]], i32 0, i32 4
+ // PGOGEN: store {{.*}} @[[EEC]], i64 32
// PGOUSE: br {{.*}} !prof ![[EE4:[0-9]+]]
if (i % 2)
continue;
}
- // PGOGEN: store {{.*}} @[[EEC]], i32 0, i32 5
+ // PGOGEN: store {{.*}} @[[EEC]], i64 40
// PGOUSE: br {{.*}} !prof ![[EE5:[0-9]+]]
if (i) {}
- // PGOGEN: store {{.*}} @[[EEC]], i32 0, i32 6
+ // PGOGEN: store {{.*}} @[[EEC]], i64 48
do {
- // PGOGEN: store {{.*}} @[[EEC]], i32 0, i32 7
+ // PGOGEN: store {{.*}} @[[EEC]], i64 56
// PGOUSE: br {{.*}} !prof ![[EE6:[0-9]+]]
if (i > 75)
return;
@@ -134,7 +134,7 @@ void early_exits(void) {
// PGOUSE: br {{.*}} !prof ![[EE7:[0-9]+]]
} while (i < 100);
- // PGOGEN: store {{.*}} @[[EEC]], i32 0, i32 8
+ // PGOGEN: store {{.*}} @[[EEC]], i64 64
// Never reached -> no weights
if (i) {}
@@ -148,74 +148,74 @@ void early_exits(void) {
void jumps(void) {
int i;
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[JMC]], i64 8
// PGOUSE: br {{.*}} !prof ![[JM1:[0-9]+]]
for (i = 0; i < 2; ++i) {
goto outofloop;
// Never reached -> no weights
if (i) {}
}
-// PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 3
+// PGOGEN: store {{.*}} @[[JMC]], i64 24
outofloop:
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 4
+ // PGOGEN: store {{.*}} @[[JMC]], i64 32
// PGOUSE: br {{.*}} !prof ![[JM2:[0-9]+]]
if (i) {}
goto loop1;
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 5
+ // PGOGEN: store {{.*}} @[[JMC]], i64 40
// PGOUSE: br {{.*}} !prof ![[JM3:[0-9]+]]
while (i) {
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 6
+ // PGOGEN: store {{.*}} @[[JMC]], i64 48
loop1:
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 7
+ // PGOGEN: store {{.*}} @[[JMC]], i64 56
// PGOUSE: br {{.*}} !prof ![[JM4:[0-9]+]]
if (i) {}
}
goto loop2;
-// PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 8
+// PGOGEN: store {{.*}} @[[JMC]], i64 64
first:
-// PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 9
+// PGOGEN: store {{.*}} @[[JMC]], i64 72
second:
-// PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 10
+// PGOGEN: store {{.*}} @[[JMC]], i64 80
third:
i++;
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 11
+ // PGOGEN: store {{.*}} @[[JMC]], i64 88
// PGOUSE: br {{.*}} !prof ![[JM5:[0-9]+]]
if (i < 3)
goto loop2;
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 12
+ // PGOGEN: store {{.*}} @[[JMC]], i64 96
// PGOUSE: br {{.*}} !prof ![[JM6:[0-9]+]]
while (i < 3) {
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 13
+ // PGOGEN: store {{.*}} @[[JMC]], i64 104
loop2:
// PGOUSE: switch {{.*}} [
// PGOUSE: ], !prof ![[JM7:[0-9]+]]
switch (i) {
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 15
+ // PGOGEN: store {{.*}} @[[JMC]], i64 120
case 0:
goto first;
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 16
+ // PGOGEN: store {{.*}} @[[JMC]], i64 128
case 1:
goto second;
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 17
+ // PGOGEN: store {{.*}} @[[JMC]], i64 136
case 2:
goto third;
}
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 14
+ // PGOGEN: store {{.*}} @[[JMC]], i64 112
}
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 18
+ // PGOGEN: store {{.*}} @[[JMC]], i64 144
// PGOUSE: br {{.*}} !prof ![[JM8:[0-9]+]]
for (i = 0; i < 10; ++i) {
goto withinloop;
// never reached -> no weights
if (i) {}
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 20
+ // PGOGEN: store {{.*}} @[[JMC]], i64 160
withinloop:
- // PGOGEN: store {{.*}} @[[JMC]], i32 0, i32 21
+ // PGOGEN: store {{.*}} @[[JMC]], i64 168
// PGOUSE: br {{.*}} !prof ![[JM9:[0-9]+]]
if (i) {}
}
@@ -232,64 +232,64 @@ void switches(void) {
// No cases -> no weights
switch (weights[0]) {
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[SWC]], i64 16
default:
break;
}
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[SWC]], i64 8
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[SWC]], i64 24
// PGOUSE: br {{.*}} !prof ![[SW1:[0-9]+]]
for (int i = 0, len = sizeof(weights) / sizeof(weights[0]); i < len; ++i) {
// PGOUSE: switch {{.*}} [
// PGOUSE: ], !prof ![[SW2:[0-9]+]]
switch (i[weights]) {
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 5
+ // PGOGEN: store {{.*}} @[[SWC]], i64 40
case 1:
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 6
+ // PGOGEN: store {{.*}} @[[SWC]], i64 48
// PGOUSE: br {{.*}} !prof ![[SW3:[0-9]+]]
if (i) {}
// fallthrough
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 7
+ // PGOGEN: store {{.*}} @[[SWC]], i64 56
case 2:
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 8
+ // PGOGEN: store {{.*}} @[[SWC]], i64 64
// PGOUSE: br {{.*}} !prof ![[SW4:[0-9]+]]
if (i) {}
break;
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 9
+ // PGOGEN: store {{.*}} @[[SWC]], i64 72
case 3:
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 10
+ // PGOGEN: store {{.*}} @[[SWC]], i64 80
// PGOUSE: br {{.*}} !prof ![[SW5:[0-9]+]]
if (i) {}
continue;
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 11
+ // PGOGEN: store {{.*}} @[[SWC]], i64 88
case 4:
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 12
+ // PGOGEN: store {{.*}} @[[SWC]], i64 96
// PGOUSE: br {{.*}} !prof ![[SW6:[0-9]+]]
if (i) {}
// PGOUSE: switch {{.*}} [
// PGOUSE: ], !prof ![[SW7:[0-9]+]]
switch (i) {
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 14
+ // PGOGEN: store {{.*}} @[[SWC]], i64 112
case 6 ... 9:
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 15
+ // PGOGEN: store {{.*}} @[[SWC]], i64 120
// PGOUSE: br {{.*}} !prof ![[SW8:[0-9]+]]
if (i) {}
continue;
}
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 13
+ // PGOGEN: store {{.*}} @[[SWC]], i64 104
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 16
+ // PGOGEN: store {{.*}} @[[SWC]], i64 128
default:
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 17
+ // PGOGEN: store {{.*}} @[[SWC]], i64 136
// PGOUSE: br {{.*}} !prof ![[SW9:[0-9]+]]
if (i == len - 1)
return;
}
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 4
+ // PGOGEN: store {{.*}} @[[SWC]], i64 32
}
- // PGOGEN: store {{.*}} @[[SWC]], i32 0, i32 18
+ // PGOGEN: store {{.*}} @[[SWC]], i64 144
// Never reached -> no weights
if (weights[0]) {}
@@ -301,62 +301,62 @@ void switches(void) {
// PGOUSE-LABEL: @big_switch()
// PGOGEN: store {{.*}} @[[BSC]]
void big_switch(void) {
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[BSC]], i64 8
// PGOUSE: br {{.*}} !prof ![[BS1:[0-9]+]]
for (int i = 0; i < 32; ++i) {
// PGOUSE: switch {{.*}} [
// PGOUSE: ], !prof ![[BS2:[0-9]+]]
switch (1 << i) {
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[BSC]], i64 24
case (1 << 0):
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 4
+ // PGOGEN: store {{.*}} @[[BSC]], i64 32
// PGOUSE: br {{.*}} !prof ![[BS3:[0-9]+]]
if (i) {}
// fallthrough
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 5
+ // PGOGEN: store {{.*}} @[[BSC]], i64 40
case (1 << 1):
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 6
+ // PGOGEN: store {{.*}} @[[BSC]], i64 48
// PGOUSE: br {{.*}} !prof ![[BS4:[0-9]+]]
if (i) {}
break;
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 7
+ // PGOGEN: store {{.*}} @[[BSC]], i64 56
case (1 << 2) ... (1 << 12):
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 8
+ // PGOGEN: store {{.*}} @[[BSC]], i64 64
// PGOUSE: br {{.*}} !prof ![[BS5:[0-9]+]]
if (i) {}
break;
// The branch for the large case range above appears after the case body
// PGOUSE: br {{.*}} !prof ![[BS6:[0-9]+]]
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 9
+ // PGOGEN: store {{.*}} @[[BSC]], i64 72
case (1 << 13):
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 10
+ // PGOGEN: store {{.*}} @[[BSC]], i64 80
// PGOUSE: br {{.*}} !prof ![[BS7:[0-9]+]]
if (i) {}
break;
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 11
+ // PGOGEN: store {{.*}} @[[BSC]], i64 88
case (1 << 14) ... (1 << 28):
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 12
+ // PGOGEN: store {{.*}} @[[BSC]], i64 96
// PGOUSE: br {{.*}} !prof ![[BS8:[0-9]+]]
if (i) {}
break;
// The branch for the large case range above appears after the case body
// PGOUSE: br {{.*}} !prof ![[BS9:[0-9]+]]
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 13
+ // PGOGEN: store {{.*}} @[[BSC]], i64 104
case (1 << 29) ... ((1 << 29) + 1):
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 14
+ // PGOGEN: store {{.*}} @[[BSC]], i64 112
// PGOUSE: br {{.*}} !prof ![[BS10:[0-9]+]]
if (i) {}
break;
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 15
+ // PGOGEN: store {{.*}} @[[BSC]], i64 120
default:
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 16
+ // PGOGEN: store {{.*}} @[[BSC]], i64 128
// PGOUSE: br {{.*}} !prof ![[BS11:[0-9]+]]
if (i) {}
break;
}
- // PGOGEN: store {{.*}} @[[BSC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[BSC]], i64 16
}
// PGOGEN-NOT: store {{.*}} @[[BSC]],
@@ -369,31 +369,31 @@ void big_switch(void) {
// PGOGEN: store {{.*}} @[[BOC]]
void boolean_operators(void) {
int v;
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[BOC]], i64 8
// PGOUSE: br {{.*}} !prof ![[BO1:[0-9]+]]
for (int i = 0; i < 100; ++i) {
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 2
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[BOC]], i64 16
+ // PGOGEN: store {{.*}} @[[BOC]], i64 24
// PGOUSE: br {{.*}} !prof ![[BO2:[0-9]+]]
v = i % 3 || i;
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 4
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 5
+ // PGOGEN: store {{.*}} @[[BOC]], i64 32
+ // PGOGEN: store {{.*}} @[[BOC]], i64 40
// PGOUSE: br {{.*}} !prof ![[BO3:[0-9]+]]
v = i % 3 && i;
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 8
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 9
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 6
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 7
+ // PGOGEN: store {{.*}} @[[BOC]], i64 64
+ // PGOGEN: store {{.*}} @[[BOC]], i64 72
+ // PGOGEN: store {{.*}} @[[BOC]], i64 48
+ // PGOGEN: store {{.*}} @[[BOC]], i64 56
// PGOUSE: br {{.*}} !prof ![[BO4:[0-9]+]]
// PGOUSE: br {{.*}} !prof ![[BO5:[0-9]+]]
v = i % 3 || i % 2 || i;
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 12
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 13
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 10
- // PGOGEN: store {{.*}} @[[BOC]], i32 0, i32 11
+ // PGOGEN: store {{.*}} @[[BOC]], i64 96
+ // PGOGEN: store {{.*}} @[[BOC]], i64 104
+ // PGOGEN: store {{.*}} @[[BOC]], i64 80
+ // PGOGEN: store {{.*}} @[[BOC]], i64 88
// PGOUSE: br {{.*}} !prof ![[BO6:[0-9]+]]
// PGOUSE: br {{.*}} !prof ![[BO7:[0-9]+]]
v = i % 2 && i % 3 && i;
@@ -409,32 +409,32 @@ void boolean_operators(void) {
void boolop_loops(void) {
int i = 100;
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 2
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 3
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[BLC]], i64 16
+ // PGOGEN: store {{.*}} @[[BLC]], i64 24
+ // PGOGEN: store {{.*}} @[[BLC]], i64 8
// PGOUSE: br {{.*}} !prof ![[BL1:[0-9]+]]
// PGOUSE: br {{.*}} !prof ![[BL2:[0-9]+]]
while (i && i > 50)
i--;
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 5
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 6
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 4
+ // PGOGEN: store {{.*}} @[[BLC]], i64 40
+ // PGOGEN: store {{.*}} @[[BLC]], i64 48
+ // PGOGEN: store {{.*}} @[[BLC]], i64 32
// PGOUSE: br {{.*}} !prof ![[BL3:[0-9]+]]
// PGOUSE: br {{.*}} !prof ![[BL4:[0-9]+]]
while ((i % 2) || (i > 0))
i--;
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 8
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 9
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 7
+ // PGOGEN: store {{.*}} @[[BLC]], i64 64
+ // PGOGEN: store {{.*}} @[[BLC]], i64 72
+ // PGOGEN: store {{.*}} @[[BLC]], i64 56
// PGOUSE: br {{.*}} !prof ![[BL5:[0-9]+]]
// PGOUSE: br {{.*}} !prof ![[BL6:[0-9]+]]
for (i = 100; i && i > 50; --i);
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 11
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 12
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 10
+ // PGOGEN: store {{.*}} @[[BLC]], i64 88
+ // PGOGEN: store {{.*}} @[[BLC]], i64 96
+ // PGOGEN: store {{.*}} @[[BLC]], i64 80
// PGOUSE: br {{.*}} !prof ![[BL7:[0-9]+]]
// PGOUSE: br {{.*}} !prof ![[BL8:[0-9]+]]
for (; (i % 2) || (i > 0); --i);
@@ -449,11 +449,11 @@ void boolop_loops(void) {
void conditional_operator(void) {
int i = 100;
- // PGOGEN: store {{.*}} @[[COC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[COC]], i64 8
// PGOUSE: br {{.*}} !prof ![[CO1:[0-9]+]]
int j = i < 50 ? i : 1;
- // PGOGEN: store {{.*}} @[[COC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[COC]], i64 16
// PGOUSE: br {{.*}} !prof ![[CO2:[0-9]+]]
int k = i ?: 0;
@@ -465,16 +465,16 @@ void conditional_operator(void) {
// PGOUSE-LABEL: @do_fallthrough()
// PGOGEN: store {{.*}} @[[DFC]]
void do_fallthrough(void) {
- // PGOGEN: store {{.*}} @[[DFC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[DFC]], i64 8
// PGOUSE: br {{.*}} !prof ![[DF1:[0-9]+]]
for (int i = 0; i < 10; ++i) {
int j = 0;
- // PGOGEN: store {{.*}} @[[DFC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[DFC]], i64 16
do {
// The number of exits out of this do-loop via the break statement
// exceeds the counter value for the loop (which does not include the
// fallthrough count). Make sure that does not violate any assertions.
- // PGOGEN: store {{.*}} @[[DFC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[DFC]], i64 24
// PGOUSE: br {{.*}} !prof ![[DF3:[0-9]+]]
if (i < 8) break;
j++;
@@ -487,7 +487,7 @@ void do_fallthrough(void) {
// PGOUSE-LABEL: @static_func()
// PGOGEN: store {{.*}} @[[STC]]
static void static_func(void) {
- // PGOGEN: store {{.*}} @[[STC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[STC]], i64 8
// PGOUSE: br {{.*}} !prof ![[ST1:[0-9]+]]
for (int i = 0; i < 10; ++i) {
}
diff --git a/clang/test/Profile/c-ternary.c b/clang/test/Profile/c-ternary.c
index 680bb91317564a..0a52756ff4b187 100644
--- a/clang/test/Profile/c-ternary.c
+++ b/clang/test/Profile/c-ternary.c
@@ -7,7 +7,7 @@
int f1(int x) {
// CHECK: [[TOBOOL:%.*]] = icmp ne i32 %{{.*}}, 0
// CHECK-NEXT: [[STEP:%.*]] = zext i1 [[TOBOOL]] to i64
- // CHECK-NEXT: [[COUNTER:%.*]] = load i64, ptr getelementptr inbounds ([2 x i64], ptr @__profc_f1, i32 0, i32 1)
+ // CHECK-NEXT: [[COUNTER:%.*]] = load i64, ptr getelementptr inbounds (i8, ptr @__profc_f1, i64 8)
// CHECK-NEXT: add i64 [[COUNTER]], [[STEP]]
// CHECK: [[COND:%.*]] = select i1 [[TOBOOL]], i32 0, i32 1
return x ? 0 : 1;
diff --git a/clang/test/Profile/cxx-class.cpp b/clang/test/Profile/cxx-class.cpp
index ce9ddcfc4553ff..a15191dc7ff92d 100644
--- a/clang/test/Profile/cxx-class.cpp
+++ b/clang/test/Profile/cxx-class.cpp
@@ -24,7 +24,7 @@ class Simple {
// CTRUSE-LABEL: define {{.*}} @_ZN6SimpleC2Ei(
// CTRGEN: store {{.*}} @[[SCC:__profc__ZN6SimpleC2Ei]]
explicit Simple(int Member) : Member(Member) {
- // CTRGEN: store {{.*}} @[[SCC]], i32 0, i32 1
+ // CTRGEN: store {{.*}} @[[SCC]], i64 8
// CTRUSE: br {{.*}} !prof ![[SC1:[0-9]+]]
if (Member) {}
// CTRGEN-NOT: store {{.*}} @[[SCC]],
@@ -37,7 +37,7 @@ class Simple {
// DTRUSE-LABEL: define {{.*}} @_ZN6SimpleD2Ev(
// DTRGEN: store {{.*}} @[[SDC:__profc__ZN6SimpleD2Ev]]
~Simple() {
- // DTRGEN: store {{.*}} @[[SDC]], i32 0, i32 1
+ // DTRGEN: store {{.*}} @[[SDC]], i64 8
// DTRUSE: br {{.*}} !prof ![[SD1:[0-9]+]]
if (Member) {}
// DTRGEN-NOT: store {{.*}} @[[SDC]],
@@ -50,7 +50,7 @@ class Simple {
// MTHUSE-LABEL: define {{.*}} @_ZN6Simple6methodEv(
// MTHGEN: store {{.*}} @[[SMC:__profc__ZN6Simple6methodEv]]
void method() {
- // MTHGEN: store {{.*}} @[[SMC]], i32 0, i32 1
+ // MTHGEN: store {{.*}} @[[SMC]], i64 8
// MTHUSE: br {{.*}} !prof ![[SM1:[0-9]+]]
if (Member) {}
// MTHGEN-NOT: store {{.*}} @[[SMC]],
@@ -66,7 +66,7 @@ class Derived : virtual public Simple {
// VCTRUSE-LABEL: define {{.*}} @_ZN7DerivedC1Ev(
// VCTRGEN: store {{.*}} @[[SCC:__profc__ZN7DerivedC1Ev]]
Derived() : Simple(0) {
- // VCTRGEN: store {{.*}} @[[SCC]], i32 0, i32 1
+ // VCTRGEN: store {{.*}} @[[SCC]], i64 8
// VCTRUSE: br {{.*}} !prof ![[SC1:[0-9]+]]
if (Member) {}
// VCTRGEN-NOT: store {{.*}} @[[SCC]],
@@ -79,7 +79,7 @@ class Derived : virtual public Simple {
// VDTRUSE-LABEL: define {{.*}} @_ZN7DerivedD2Ev(
// VDTRGEN: store {{.*}} @[[SDC:__profc__ZN7DerivedD2Ev]]
~Derived() {
- // VDTRGEN: store {{.*}} @[[SDC]], i32 0, i32 1
+ // VDTRGEN: store {{.*}} @[[SDC]], i64 8
// VDTRUSE: br {{.*}} !prof ![[SD1:[0-9]+]]
if (Member) {}
// VDTRGEN-NOT: store {{.*}} @[[SDC]],
@@ -93,7 +93,7 @@ class Derived : virtual public Simple {
// WRPUSE-LABEL: define {{.*}} @_Z14simple_wrapperv(
// WRPGEN: store {{.*}} @[[SWC:__profc__Z14simple_wrapperv]]
void simple_wrapper() {
- // WRPGEN: store {{.*}} @[[SWC]], i32 0, i32 1
+ // WRPGEN: store {{.*}} @[[SWC]], i64 8
// WRPUSE: br {{.*}} !prof ![[SW1:[0-9]+]]
for (int I = 0; I < 100; ++I) {
Derived d;
diff --git a/clang/test/Profile/cxx-lambda.cpp b/clang/test/Profile/cxx-lambda.cpp
index b05fdd3d26b7cd..e2996c1168ea09 100644
--- a/clang/test/Profile/cxx-lambda.cpp
+++ b/clang/test/Profile/cxx-lambda.cpp
@@ -23,25 +23,25 @@ void lambdas() {
// LMBUSE-LABEL: define internal{{( [0-9_a-z]*cc)?( noundef)?( zeroext)?}} i1 @"_ZZ7lambdasvENK3$_0clEi"(
// LMBGEN: store {{.*}} @[[LFC]]
auto f = [&i](int k) {
- // LMBGEN: store {{.*}} @[[LFC]], i32 0, i32 1
+ // LMBGEN: store {{.*}} @[[LFC]], i64 8
// LMBUSE: br {{.*}} !prof ![[LF1:[0-9]+]]
if (i > 0) {
}
- // LMBGEN: store {{.*}} @[[LFC]], i32 0, i32 2
+ // LMBGEN: store {{.*}} @[[LFC]], i64 16
// LMBUSE: br {{.*}} !prof ![[LF2:[0-9]+]]
return k && i;
};
- // PGOGEN: store {{.*}} @[[LWC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[LWC]], i64 8
// PGOUSE: br {{.*}} !prof ![[LW1:[0-9]+]]
if (i) {}
- // PGOGEN: store {{.*}} @[[LWC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[LWC]], i64 16
// PGOUSE: br {{.*}} !prof ![[LW2:[0-9]+]]
for (i = 0; i < 10; ++i)
f(9 - i);
- // PGOGEN: store {{.*}} @[[LWC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[LWC]], i64 24
// PGOUSE: br {{.*}} !prof ![[LW3:[0-9]+]]
if (i) {}
}
diff --git a/clang/test/Profile/cxx-rangefor.cpp b/clang/test/Profile/cxx-rangefor.cpp
index 43bdaa9b70aebc..f10345d79790c1 100644
--- a/clang/test/Profile/cxx-rangefor.cpp
+++ b/clang/test/Profile/cxx-rangefor.cpp
@@ -14,21 +14,21 @@
void range_for() {
int arr[] = {1, 2, 3, 4, 5};
int sum = 0;
- // PGOGEN: store {{.*}} @[[RFC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[RFC]], i64 8
// PGOUSE: br {{.*}} !prof ![[RF1:[0-9]+]]
for (auto i : arr) {
- // PGOGEN: store {{.*}} @[[RFC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[RFC]], i64 16
// PGOUSE: br {{.*}} !prof ![[RF2:[0-9]+]]
if (i == 3)
continue;
sum += i;
- // PGOGEN: store {{.*}} @[[RFC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[RFC]], i64 24
// PGOUSE: br {{.*}} !prof ![[RF3:[0-9]+]]
if (sum >= 7)
break;
}
- // PGOGEN: store {{.*}} @[[RFC]], i32 0, i32 4
+ // PGOGEN: store {{.*}} @[[RFC]], i64 32
// PGOUSE: br {{.*}} !prof ![[RF4:[0-9]+]]
if (sum) {}
}
diff --git a/clang/test/Profile/cxx-stmt-initializers.cpp b/clang/test/Profile/cxx-stmt-initializers.cpp
index a02be89c8e14d5..3f3ddc3c95457c 100644
--- a/clang/test/Profile/cxx-stmt-initializers.cpp
+++ b/clang/test/Profile/cxx-stmt-initializers.cpp
@@ -13,8 +13,8 @@
// PGOGEN: store {{.*}} @[[SIC]]
void switch_init() {
switch (int i = true ? 0 : 1; i) {}
- // PGOGEN: store {{.*}} @[[SIC]], i32 0, i32 2
- // PGOGEN: store {{.*}} @[[SIC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[SIC]], i64 16
+ // PGOGEN: store {{.*}} @[[SIC]], i64 8
}
// Note: We expect counters for the function entry block, the condition in the
@@ -24,6 +24,6 @@ void switch_init() {
// PGOGEN: store {{.*}} @[[IIC]]
void if_init() {
if (int i = true ? 0 : 1; i) {}
- // PGOGEN: store {{.*}} @[[IIC]], i32 0, i32 2
- // PGOGEN: store {{.*}} @[[IIC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[IIC]], i64 16
+ // PGOGEN: store {{.*}} @[[IIC]], i64 8
}
diff --git a/clang/test/Profile/cxx-templates.cpp b/clang/test/Profile/cxx-templates.cpp
index 09cf11e841dc4e..8477c4cc0ea6c0 100644
--- a/clang/test/Profile/cxx-templates.cpp
+++ b/clang/test/Profile/cxx-templates.cpp
@@ -25,9 +25,9 @@ template <unsigned N> void loop() {
// T100GEN: store {{.*}} @[[T100C]]
// ALL-NOT: ret
- // T0GEN: store {{.*}} @[[T0C]], i32 0, i32 1
+ // T0GEN: store {{.*}} @[[T0C]], i64 8
// T0USE: br {{.*}} !prof ![[T01:[0-9]+]]
- // T100GEN: store {{.*}} @[[T100C]], i32 0, i32 1
+ // T100GEN: store {{.*}} @[[T100C]], i64 8
// T100USE: br {{.*}} !prof ![[T1001:[0-9]+]]
for (unsigned I = 0; I < N; ++I) {}
diff --git a/clang/test/Profile/cxx-throws.cpp b/clang/test/Profile/cxx-throws.cpp
index fc04add24b97d7..836ef509cb70a8 100644
--- a/clang/test/Profile/cxx-throws.cpp
+++ b/clang/test/Profile/cxx-throws.cpp
@@ -18,14 +18,14 @@
// PGOUSE-LABEL: @_Z6throwsv()
// PGOGEN: store {{.*}} @[[THC]]
void throws() {
- // PGOGEN: store {{.*}} @[[THC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[THC]], i64 8
// PGOUSE: br {{.*}} !prof ![[TH1:[0-9]+]]
for (int i = 0; i < 100; ++i) {
try {
- // PGOGEN: store {{.*}} @[[THC]], i32 0, i32 3
+ // PGOGEN: store {{.*}} @[[THC]], i64 24
// PGOUSE: br {{.*}} !prof ![[TH2:[0-9]+]]
if (i % 3) {
- // PGOGEN: store {{.*}} @[[THC]], i32 0, i32 4
+ // PGOGEN: store {{.*}} @[[THC]], i64 32
// PGOUSE: br {{.*}} !prof ![[TH3:[0-9]+]]
if (i < 50)
throw 1;
@@ -36,7 +36,7 @@ void throws() {
// PGOUSE: if.else{{.*}}:
// PGOGEN: if.else{{.*}}:
- // PGOGEN: store {{.*}} @[[THC]], i32 0, i32 5
+ // PGOGEN: store {{.*}} @[[THC]], i64 40
// PGOUSE: br {{.*}} !prof ![[TH4:[0-9]+]]
if (i >= 50)
throw 0;
@@ -45,14 +45,14 @@ void throws() {
// PGOUSE-EXC: catch{{.*}}:
// PGOGEN-EXC: catch{{.*}}:
- // PGOGEN-EXC: store {{.*}} @[[THC]], i32 0, i32 6
- // PGOGEN-EXC: store {{.*}} @[[THC]], i32 0, i32 7
+ // PGOGEN-EXC: store {{.*}} @[[THC]], i64 48
+ // PGOGEN-EXC: store {{.*}} @[[THC]], i64 56
// PGOUSE-EXC: br {{.*}} !prof ![[TH5:[0-9]+]]
if (e) {}
}
- // PGOGEN: store {{.*}} @[[THC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[THC]], i64 16
- // PGOGEN: store {{.*}} @[[THC]], i32 0, i32 8
+ // PGOGEN: store {{.*}} @[[THC]], i64 64
// PGOUSE: br {{.*}} !prof ![[TH6:[0-9]+]]
if (i < 100) {}
}
@@ -65,12 +65,12 @@ void throws() {
// PGOUSE-LABEL: @_Z11unreachablei(i32
// PGOGEN: store {{.*}} @[[UNC]]
void unreachable(int i) {
- // PGOGEN: store {{.*}} @[[UNC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[UNC]], i64 8
// PGOUSE: br {{.*}} !prof ![[UN1:[0-9]+]]
if (i)
throw i;
- // PGOGEN: store {{.*}} @[[UNC]], i32 0, i32 2
+ // PGOGEN: store {{.*}} @[[UNC]], i64 16
// Since we never reach here, the weights should all be zero (and skipped)
// PGOUSE-NOT: br {{.*}} !prof !{{.*}}
if (i) {}
diff --git a/clang/test/Profile/objc-general.m b/clang/test/Profile/objc-general.m
index a711645e7c833b..a434c4c947dc57 100644
--- a/clang/test/Profile/objc-general.m
+++ b/clang/test/Profile/objc-general.m
@@ -48,7 +48,7 @@ @implementation A
+ (void)foreach: (NSArray *)array
{
__block id result;
- // PGOGEN: store {{.*}} @[[FRC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[FRC]], i64 8
// PGOUSE: br {{.*}} !prof ![[FR1:[0-9]+]]
// PGOUSE: br {{.*}} !prof ![[FR2:[0-9]+]]
for (id x in array) {
@@ -57,7 +57,7 @@ + (void)foreach: (NSArray *)array
// PGOGEN: store {{.*}} @[[BLC]]
^{
static int init = 0;
- // PGOGEN: store {{.*}} @[[BLC]], i32 0, i32 1
+ // PGOGEN: store {{.*}} @[[BLC]], i64 8
// PGOUSE: br {{.*}} !prof ![[BL1:[0-9]+]]
if (init)
result = x;
diff --git a/llvm/include/llvm/Analysis/InstSimplifyFolder.h b/llvm/include/llvm/Analysis/InstSimplifyFolder.h
index 6414901a4f6ed4..4b1210fb51a91a 100644
--- a/llvm/include/llvm/Analysis/InstSimplifyFolder.h
+++ b/llvm/include/llvm/Analysis/InstSimplifyFolder.h
@@ -78,8 +78,8 @@ class LLVM_ABI InstSimplifyFolder final : public IRBuilderFolder {
return simplifyCmpInst(P, LHS, RHS, SQ);
}
- Value *FoldGEP(Type *Ty, Value *Ptr, ArrayRef<Value *> IdxList,
- GEPNoWrapFlags NW) const override {
+ Value *FoldGEP(const DataLayout &, Type *Ty, Value *Ptr,
+ ArrayRef<Value *> IdxList, GEPNoWrapFlags NW) const override {
return simplifyGEPInst(Ty, Ptr, IdxList, NW, SQ);
}
diff --git a/llvm/include/llvm/Analysis/TargetFolder.h b/llvm/include/llvm/Analysis/TargetFolder.h
index 5db0863e82a838..6229463d879375 100644
--- a/llvm/include/llvm/Analysis/TargetFolder.h
+++ b/llvm/include/llvm/Analysis/TargetFolder.h
@@ -116,8 +116,8 @@ class LLVM_ABI TargetFolder final : public IRBuilderFolder {
return nullptr;
}
- Value *FoldGEP(Type *Ty, Value *Ptr, ArrayRef<Value *> IdxList,
- GEPNoWrapFlags NW) const override {
+ Value *FoldGEP(const DataLayout &, Type *Ty, Value *Ptr,
+ ArrayRef<Value *> IdxList, GEPNoWrapFlags NW) const override {
if (!ConstantExpr::isSupportedGetElementPtr(Ty))
return nullptr;
diff --git a/llvm/include/llvm/IR/ConstantFolder.h b/llvm/include/llvm/IR/ConstantFolder.h
index a3f56a07370228..e843516b115b7a 100644
--- a/llvm/include/llvm/IR/ConstantFolder.h
+++ b/llvm/include/llvm/IR/ConstantFolder.h
@@ -104,8 +104,8 @@ class LLVM_ABI ConstantFolder final : public IRBuilderFolder {
return nullptr;
}
- Value *FoldGEP(Type *Ty, Value *Ptr, ArrayRef<Value *> IdxList,
- GEPNoWrapFlags NW) const override {
+ Value *FoldGEP(const DataLayout &DL, Type *Ty, Value *Ptr,
+ ArrayRef<Value *> IdxList, GEPNoWrapFlags NW) const override {
if (!ConstantExpr::isSupportedGetElementPtr(Ty))
return nullptr;
@@ -114,7 +114,9 @@ class LLVM_ABI ConstantFolder final : public IRBuilderFolder {
if (any_of(IdxList, [](Value *V) { return !isa<Constant>(V); }))
return nullptr;
- return ConstantExpr::getGetElementPtr(Ty, PC, IdxList, NW);
+ ArrayRef<Constant *> ConstIdxList =
+ ArrayRef((Constant *const *)IdxList.data(), IdxList.size());
+ return ConstantExpr::getGetElementPtr(DL, Ty, PC, ConstIdxList, NW);
}
return nullptr;
}
diff --git a/llvm/include/llvm/IR/IRBuilder.h b/llvm/include/llvm/IR/IRBuilder.h
index 6634cf4116bb47..7f6a8cc803afdc 100644
--- a/llvm/include/llvm/IR/IRBuilder.h
+++ b/llvm/include/llvm/IR/IRBuilder.h
@@ -2019,7 +2019,7 @@ class IRBuilderBase {
Value *CreateGEP(Type *Ty, Value *Ptr, ArrayRef<Value *> IdxList,
const Twine &Name = "",
GEPNoWrapFlags NW = GEPNoWrapFlags::none()) {
- if (auto *V = Folder.FoldGEP(Ty, Ptr, IdxList, NW))
+ if (auto *V = Folder.FoldGEP(BB->getDataLayout(), Ty, Ptr, IdxList, NW))
return V;
return Insert(GetElementPtrInst::Create(Ty, Ptr, IdxList, NW), Name);
}
diff --git a/llvm/include/llvm/IR/IRBuilderFolder.h b/llvm/include/llvm/IR/IRBuilderFolder.h
index 262d6c0d9e3903..5ed497a9323b8f 100644
--- a/llvm/include/llvm/IR/IRBuilderFolder.h
+++ b/llvm/include/llvm/IR/IRBuilderFolder.h
@@ -53,7 +53,8 @@ class LLVM_ABI IRBuilderFolder {
virtual Value *FoldCmp(CmpInst::Predicate P, Value *LHS,
Value *RHS) const = 0;
- virtual Value *FoldGEP(Type *Ty, Value *Ptr, ArrayRef<Value *> IdxList,
+ virtual Value *FoldGEP(const DataLayout &DL, Type *Ty, Value *Ptr,
+ ArrayRef<Value *> IdxList,
GEPNoWrapFlags NW) const = 0;
virtual Value *FoldSelect(Value *C, Value *True, Value *False,
diff --git a/llvm/include/llvm/IR/NoFolder.h b/llvm/include/llvm/IR/NoFolder.h
index 7b497053e36623..fbd3fcb6baf0c9 100644
--- a/llvm/include/llvm/IR/NoFolder.h
+++ b/llvm/include/llvm/IR/NoFolder.h
@@ -75,8 +75,8 @@ class LLVM_ABI NoFolder final : public IRBuilderFolder {
return nullptr;
}
- Value *FoldGEP(Type *Ty, Value *Ptr, ArrayRef<Value *> IdxList,
- GEPNoWrapFlags NW) const override {
+ Value *FoldGEP(const DataLayout &, Type *Ty, Value *Ptr,
+ ArrayRef<Value *> IdxList, GEPNoWrapFlags NW) const override {
return nullptr;
}
diff --git a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
index 9a07697f66762f..eaf908461d7dfc 100644
--- a/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
+++ b/llvm/lib/Transforms/Vectorize/VPlanUtils.cpp
@@ -1336,13 +1336,13 @@ VPIRValue *vputils::tryToFoldLiveIns(VPSingleDefRecipe &R,
case Instruction::GetElementPtr: {
auto &RFlags = cast<VPRecipeWithIRFlags>(R);
auto *GEP = cast<GetElementPtrInst>(RFlags.getUnderlyingInstr());
- return Folder.FoldGEP(GEP->getSourceElementType(), Ops[0],
+ return Folder.FoldGEP(DL, GEP->getSourceElementType(), Ops[0],
drop_begin(Ops), RFlags.getGEPNoWrapFlags());
}
case VPInstruction::PtrAdd:
case VPInstruction::WidePtrAdd:
- return Folder.FoldGEP(IntegerType::getInt8Ty(Plan.getContext()), Ops[0],
- Ops[1],
+ return Folder.FoldGEP(DL, IntegerType::getInt8Ty(Plan.getContext()),
+ Ops[0], Ops[1],
cast<VPRecipeWithIRFlags>(R).getGEPNoWrapFlags());
// An extract of a live-in is an extract of a broadcast, so return the
// broadcasted element.
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
index c17946a37fc580..9c1f5121956c8b 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test-asan.ll
@@ -23,17 +23,17 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]
; CHECK: Malloc:
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 8), align 4
; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP8]], [[TMP9]]
; CHECK-NEXT: [[TMP20:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP20]], i64 15
-; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 12), align 4
; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(4) [[TMP18]], align 4
-; CHECK-NEXT: store i32 [[TMP13]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP13]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 16), align 4
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], 0
; CHECK-NEXT: [[TMP15:%.*]] = udiv i32 [[TMP14]], 1
; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], 1
-; CHECK-NEXT: store i32 [[TMP16]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP16]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 20), align 4
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP24]], [[TMP16]]
; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP17]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test.ll
index 4a91f5c1c51d34..b5f0a3153271e5 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-dynamic-lds-test.ll
@@ -23,17 +23,17 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]
; CHECK: Malloc:
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, align 4
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 0, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 8), align 4
; CHECK-NEXT: [[TMP24:%.*]] = add i32 [[TMP8]], [[TMP9]]
; CHECK-NEXT: [[TMP20:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP20]], i64 15
-; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 12), align 4
; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(4) [[TMP18]], align 4
-; CHECK-NEXT: store i32 [[TMP13]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP13]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 16), align 4
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], 0
; CHECK-NEXT: [[TMP15:%.*]] = udiv i32 [[TMP14]], 1
; CHECK-NEXT: [[TMP16:%.*]] = mul i32 [[TMP15]], 1
-; CHECK-NEXT: store i32 [[TMP16]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP16]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 20), align 4
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP24]], [[TMP16]]
; CHECK-NEXT: [[TMP21:%.*]] = zext i32 [[TMP17]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-lower-all.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-lower-all.ll
index d9383c14f884ee..165646f6215186 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-lower-all.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-lower-all.ll
@@ -18,8 +18,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB20:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -81,8 +81,8 @@ define amdgpu_kernel void @k1() {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
index 4af7dcf8cd9bae..896397d7852002 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access-asan.ll
@@ -188,26 +188,26 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 28), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 7
; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 8
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 8
-; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]
-; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 36), align 4
; CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP25]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP25]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 40), align 4
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP25]], 7
; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP17]], 8
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8
-; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 44), align 4
; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP15]], [[TMP19]]
; CHECK-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64
; CHECK-NEXT: [[TMP28:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -285,26 +285,26 @@ define amdgpu_kernel void @k1() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP14:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 36), align 4
; CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP30]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 40), align 4
; CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP30]], 7
; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP33]], 8
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8
-; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 44), align 4
; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP8]], [[TMP19]]
-; CHECK-NEXT: store i32 [[TMP20]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP20]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 48), align 4
; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 52), align 4
; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], 7
; CHECK-NEXT: [[TMP23:%.*]] = udiv i32 [[TMP22]], 8
; CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[TMP23]], 8
-; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 56), align 4
; CHECK-NEXT: [[TMP25:%.*]] = add i32 [[TMP20]], [[TMP24]]
; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP25]] to i64
; CHECK-NEXT: [[TMP27:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll
index 931cceac6c3c21..938b1f6ecc877c 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multi-static-dynamic-indirect-access.ll
@@ -75,26 +75,26 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 28), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 7
; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 8
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 8
-; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]
-; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 36), align 4
; CHECK-NEXT: [[TMP25:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP25]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP25]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 40), align 4
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP25]], 7
; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP17]], 8
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8
-; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 44), align 4
; CHECK-NEXT: [[TMP26:%.*]] = add i32 [[TMP15]], [[TMP19]]
; CHECK-NEXT: [[TMP27:%.*]] = zext i32 [[TMP26]] to i64
; CHECK-NEXT: [[TMP28:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -150,26 +150,26 @@ define amdgpu_kernel void @k1() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP14:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 36), align 4
; CHECK-NEXT: [[TMP30:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP30]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP30]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 40), align 4
; CHECK-NEXT: [[TMP33:%.*]] = add i32 [[TMP30]], 7
; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP33]], 8
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8
-; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 3, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 44), align 4
; CHECK-NEXT: [[TMP20:%.*]] = add i32 [[TMP8]], [[TMP19]]
-; CHECK-NEXT: store i32 [[TMP20]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP20]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 48), align 4
; CHECK-NEXT: [[TMP21:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 52), align 4
; CHECK-NEXT: [[TMP22:%.*]] = add i32 [[TMP21]], 7
; CHECK-NEXT: [[TMP23:%.*]] = udiv i32 [[TMP22]], 8
; CHECK-NEXT: [[TMP24:%.*]] = mul i32 [[TMP23]], 8
-; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP24]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 56), align 4
; CHECK-NEXT: [[TMP25:%.*]] = add i32 [[TMP20]], [[TMP24]]
; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP25]] to i64
; CHECK-NEXT: [[TMP27:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll
index 0d004c3d4c0df8..21cb8c991f7ac1 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return-asan.ll
@@ -23,8 +23,8 @@ define amdgpu_kernel void @test_kernel() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_TEST_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.test_kernel.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_TEST_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.test_kernel.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.test_kernel.md, i64 24), align 4
+; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.test_kernel.md, i64 32), align 4
; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP15]], [[TMP16]]
; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP18]] to i64
; CHECK-NEXT: [[TMP14:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return.ll
index 49633a8d4d6f83..f75435474b06ff 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-multiple-blocks-return.ll
@@ -23,8 +23,8 @@ define amdgpu_kernel void @test_kernel() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_TEST_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.test_kernel.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_TEST_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.test_kernel.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP15:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.test_kernel.md, i64 24), align 4
+; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.test_kernel.md, i64 32), align 4
; CHECK-NEXT: [[TMP18:%.*]] = add i32 [[TMP15]], [[TMP16]]
; CHECK-NEXT: [[TMP17:%.*]] = zext i32 [[TMP18]] to i64
; CHECK-NEXT: [[TMP14:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
index 35ef4d5e36824b..ec09d0a4cdfdf8 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-non-kernel-declaration.ll
@@ -46,8 +46,8 @@ define amdgpu_kernel void @k1() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k1.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
index 59d1d56152ad04..ddb7fd1a5ddd43 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access-asan.ll
@@ -99,26 +99,26 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 36), align 4
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 40), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 7
; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 8
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 8
-; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 44), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]
-; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4
; CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP27]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP27]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 52), align 4
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP27]], 7
; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP17]], 8
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8
-; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4
; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[TMP15]], [[TMP19]]
; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP28]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
index 7d1478e6ee01db..610cf4bcf67eb3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-indirect-access.ll
@@ -55,26 +55,26 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 36), align 4
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 40), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 7
; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 8
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 8
-; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 44), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]
-; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4
; CHECK-NEXT: [[TMP27:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP27]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP27]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 52), align 4
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP27]], 7
; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP17]], 8
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8
-; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4
; CHECK-NEXT: [[TMP28:%.*]] = add i32 [[TMP15]], [[TMP19]]
; CHECK-NEXT: [[TMP26:%.*]] = zext i32 [[TMP28]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
index 12c88e016afe2a..50b73bc4f488ea 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test-asan.ll
@@ -24,26 +24,26 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 36), align 4
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 40), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 7
; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 8
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 8
-; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 44), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]
-; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4
; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP31]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP31]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 52), align 4
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP31]], 7
; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP17]], 8
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8
-; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4
; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[TMP15]], [[TMP19]]
; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP32]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test.ll
index b3b9139a59fd0f..203403ce5b34f0 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-dynamic-lds-test.ll
@@ -24,26 +24,26 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP21:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP9]], [[TMP7]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 36), align 4
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 40), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 7
; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 8
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 8
-; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 3, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 44), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]
-; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP15]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4
; CHECK-NEXT: [[TMP31:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP31]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP31]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 52), align 4
; CHECK-NEXT: [[TMP17:%.*]] = add i32 [[TMP31]], 7
; CHECK-NEXT: [[TMP18:%.*]] = udiv i32 [[TMP17]], 8
; CHECK-NEXT: [[TMP19:%.*]] = mul i32 [[TMP18]], 8
-; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP19]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4
; CHECK-NEXT: [[TMP32:%.*]] = add i32 [[TMP15]], [[TMP19]]
; CHECK-NEXT: [[TMP30:%.*]] = zext i32 [[TMP32]] to i64
; CHECK-NEXT: [[TMP22:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
index c20ddfebfaaf71..6d7dc0fd71c9d7 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-asan.ll
@@ -80,8 +80,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB24:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4
; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP13]], [[TMP14]]
; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP16]] to i64
; CHECK-NEXT: [[TMP23:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
index 53ff7be409ae23..5ecedbb5139a15 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param-asan.ll
@@ -92,8 +92,8 @@ define amdgpu_kernel void @my_kernel() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MY_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MY_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i64 12), align 4
+; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i64 20), align 4
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP14]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param.ll
index ec788ad004b842..f165750b91a9df 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-function-param.ll
@@ -45,8 +45,8 @@ define amdgpu_kernel void @my_kernel() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MY_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MY_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i64 12), align 4
+; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.my_kernel.md, i64 20), align 4
; CHECK-NEXT: [[TMP14:%.*]] = add i32 [[TMP11]], [[TMP12]]
; CHECK-NEXT: [[TMP13:%.*]] = zext i32 [[TMP14]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
index 1d5ac7269d62d0..b04a6a14763bae 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-lower-all.ll
@@ -58,8 +58,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB24:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
index 99cf16fe5d2e88..9cd9fd93821b81 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested-asan.ll
@@ -32,8 +32,8 @@ define amdgpu_kernel void @kernel_0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_0.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_0.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_0.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_0.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -83,17 +83,17 @@ define amdgpu_kernel void @kernel_1() sanitize_address {
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB23:.*]]
; CHECK: [[MALLOC]]:
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_1_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i32 0, i32 0, i32 2), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i64 8), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP9]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i64 12), align 4
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i32 0, i32 1, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i64 16), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 3
; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 4
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 4
-; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i64 20), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -140,8 +140,8 @@ define amdgpu_kernel void @kernel_2() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_2_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_2.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_2_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_2.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_2.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_2.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -191,17 +191,17 @@ define amdgpu_kernel void @kernel_3() sanitize_address {
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB23:.*]]
; CHECK: [[MALLOC]]:
; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_3_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i32 0, i32 0, i32 2), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i64 8), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP9]], i64 15
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_3_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i64 12), align 4
; CHECK-NEXT: [[TMP11:%.*]] = load i32, ptr addrspace(4) [[TMP10]], align 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_3_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i32 0, i32 1, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i64 16), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP11]], 3
; CHECK-NEXT: [[TMP13:%.*]] = udiv i32 [[TMP12]], 4
; CHECK-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 4
-; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_3_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP14]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i64 20), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP8]], [[TMP14]]
; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll
index 33b9e1e0567ce7..24444c7df20964 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-nested.ll
@@ -32,8 +32,8 @@ define amdgpu_kernel void @kernel_0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_0.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_0.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_0.md, i64 12), align 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_0.md, i64 20), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP9]], [[TMP10]]
; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP12]] to i64
; CHECK-NEXT: [[TMP13:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -83,17 +83,17 @@ define amdgpu_kernel void @kernel_1() sanitize_address {
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB23:.*]]
; CHECK: [[MALLOC]]:
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, align 4
-; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_1_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i32 0, i32 0, i32 2), align 4
+; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i64 8), align 4
; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i64 12), align 4
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(4) [[TMP7]], align 4
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i32 0, i32 1, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i64 16), align 4
; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = udiv i32 [[TMP9]], 4
; CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_1_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_1.md, i64 20), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP21]], [[TMP11]]
; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -140,8 +140,8 @@ define amdgpu_kernel void @kernel_2() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_2_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_2.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_2_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_2.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_2.md, i64 12), align 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_2.md, i64 20), align 4
; CHECK-NEXT: [[TMP12:%.*]] = add i32 [[TMP9]], [[TMP10]]
; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP12]] to i64
; CHECK-NEXT: [[TMP13:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -191,17 +191,17 @@ define amdgpu_kernel void @kernel_3() sanitize_address {
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB23:.*]]
; CHECK: [[MALLOC]]:
; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, align 4
-; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_3_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i32 0, i32 0, i32 2), align 4
+; CHECK-NEXT: [[TMP20:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i64 8), align 4
; CHECK-NEXT: [[TMP21:%.*]] = add i32 [[TMP12]], [[TMP20]]
; CHECK-NEXT: [[TMP6:%.*]] = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
; CHECK-NEXT: [[TMP7:%.*]] = getelementptr inbounds ptr addrspace(4), ptr addrspace(4) [[TMP6]], i64 15
-; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_3_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i32 0, i32 1, i32 0), align 4
+; CHECK-NEXT: store i32 [[TMP21]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i64 12), align 4
; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(4) [[TMP7]], align 4
-; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_3_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i32 0, i32 1, i32 1), align 4
+; CHECK-NEXT: store i32 [[TMP8]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i64 16), align 4
; CHECK-NEXT: [[TMP9:%.*]] = add i32 [[TMP8]], 3
; CHECK-NEXT: [[TMP10:%.*]] = udiv i32 [[TMP9]], 4
; CHECK-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], 4
-; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_KERNEL_3_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: store i32 [[TMP11]], ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.kernel_3.md, i64 20), align 4
; CHECK-NEXT: [[TMP15:%.*]] = add i32 [[TMP21]], [[TMP11]]
; CHECK-NEXT: [[TMP16:%.*]] = zext i32 [[TMP15]] to i64
; CHECK-NEXT: [[TMP17:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
index ca562291bd8ce7..01007d6121b088 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access-no-kernel-lds-id.ll
@@ -59,8 +59,8 @@ define amdgpu_kernel void @k0() sanitize_address #1 {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB24:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll
index 82dcfe2edbfcc6..185dd4d4c6c0bf 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-indirect-access.ll
@@ -58,8 +58,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB24:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 0), align 4
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 4, i32 2), align 4
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 48), align 4
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 56), align 4
; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP13]], [[TMP14]]
; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP16]] to i64
; CHECK-NEXT: [[TMP23:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-O0.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-O0.ll
index fa0326b61f70dc..722ee0ae4169b8 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-O0.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-O0.ll
@@ -18,8 +18,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
index 199149b87b05f9..e84950c5e03172 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-no-heap-ptr.ll
@@ -22,8 +22,8 @@ define amdgpu_kernel void @k0() sanitize_address #1 {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB20:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll
index ff2a632b3d22f2..c8b58c92ed5aa1 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-asan.ll
@@ -21,8 +21,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP13]], [[TMP14]]
; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP16]] to i64
; CHECK-NEXT: [[TMP23:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
index c35102a44f5f8c..51dbb556dea212 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomic-cmpxchg-asan.ll
@@ -19,8 +19,8 @@ define amdgpu_kernel void @atomic_xchg_kernel(ptr addrspace(1) %out, [8 x i32],
; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i32 [[TMP6]], 0
; CHECK-NEXT: br i1 [[TMP7]], label [[MALLOC:%.*]], label [[TMP20:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_ATOMIC_XCHG_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.atomic_xchg_kernel.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_ATOMIC_XCHG_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.atomic_xchg_kernel.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.atomic_xchg_kernel.md, i64 12), align 4
+; CHECK-NEXT: [[TMP9:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.atomic_xchg_kernel.md, i64 20), align 4
; CHECK-NEXT: [[TMP10:%.*]] = add i32 [[TMP8]], [[TMP9]]
; CHECK-NEXT: [[TMP11:%.*]] = zext i32 [[TMP10]] to i64
; CHECK-NEXT: [[TMP12:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
index e63233b2556635..c6d3ca2194fa8e 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-atomicrmw-asan.ll
@@ -21,8 +21,8 @@ define amdgpu_kernel void @atomicrmw_kernel(ptr addrspace(1) %arg0) sanitize_add
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP65]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP20:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_ATOMICRMW_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.atomicrmw_kernel.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_ATOMICRMW_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.atomicrmw_kernel.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.atomicrmw_kernel.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.atomicrmw_kernel.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-memintrinsic-asan.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-memintrinsic-asan.ll
index a480999c05fb17..391f55bc0f52a3 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-memintrinsic-asan.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test-memintrinsic-asan.ll
@@ -20,8 +20,8 @@ define amdgpu_kernel void @memset_kernel() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMSET_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memset_kernel.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMSET_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memset_kernel.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memset_kernel.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memset_kernel.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -76,8 +76,8 @@ define amdgpu_kernel void @memcpy_kernel(ptr addrspace(1) %src) sanitize_address
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMCPY_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memcpy_kernel.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMCPY_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memcpy_kernel.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memcpy_kernel.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memcpy_kernel.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -132,8 +132,8 @@ define amdgpu_kernel void @memmove_kernel() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB20:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMMOVE_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memmove_kernel.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMMOVE_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memmove_kernel.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memmove_kernel.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memmove_kernel.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -197,8 +197,8 @@ define amdgpu_kernel void @memset_atomic_kernel() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMSET_ATOMIC_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memset_atomic_kernel.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMSET_ATOMIC_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memset_atomic_kernel.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memset_atomic_kernel.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memset_atomic_kernel.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -253,8 +253,8 @@ define amdgpu_kernel void @memcpy_atomic_kernel(ptr addrspace(1) %src) sanitize_
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB18:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMCPY_ATOMIC_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memcpy_atomic_kernel.md, i32 0, i32 1, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMCPY_ATOMIC_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memcpy_atomic_kernel.md, i32 0, i32 1, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memcpy_atomic_kernel.md, i64 12), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memcpy_atomic_kernel.md, i64 20), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
@@ -309,8 +309,8 @@ define amdgpu_kernel void @memmove_atomic_kernel() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[BB20:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMMOVE_ATOMIC_KERNEL_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memmove_atomic_kernel.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_MEMMOVE_ATOMIC_KERNEL_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.memmove_atomic_kernel.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memmove_atomic_kernel.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.memmove_atomic_kernel.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test.ll
index 2338da4434bb54..d559b16040f110 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-test.ll
@@ -22,8 +22,8 @@ define amdgpu_kernel void @k0() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label [[MALLOC:%.*]], label [[TMP7:%.*]]
; CHECK: Malloc:
-; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_K0_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP13:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 24), align 4
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.k0.md, i64 32), align 4
; CHECK-NEXT: [[TMP16:%.*]] = add i32 [[TMP13]], [[TMP14]]
; CHECK-NEXT: [[TMP15:%.*]] = zext i32 [[TMP16]] to i64
; CHECK-NEXT: [[TMP23:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll
index 96fdb36900262f..3433a3f1ef30a8 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-sw-lower-lds-static-lds-vector-ptrs.ll
@@ -21,8 +21,8 @@ define amdgpu_kernel void @example() sanitize_address {
; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[TMP4]], 0
; CHECK-NEXT: br i1 [[TMP5]], label %[[MALLOC:.*]], label %[[ENTRY:.*]]
; CHECK: [[MALLOC]]:
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_EXAMPLE_MD_TYPE:%.*]], ptr addrspace(1) @llvm.amdgcn.sw.lds.example.md, i32 0, i32 2, i32 0), align 4
-; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds ([[LLVM_AMDGCN_SW_LDS_EXAMPLE_MD_TYPE]], ptr addrspace(1) @llvm.amdgcn.sw.lds.example.md, i32 0, i32 2, i32 2), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.example.md, i64 24), align 4
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @llvm.amdgcn.sw.lds.example.md, i64 32), align 4
; CHECK-NEXT: [[TMP8:%.*]] = add i32 [[TMP6]], [[TMP7]]
; CHECK-NEXT: [[TMP9:%.*]] = zext i32 [[TMP8]] to i64
; CHECK-NEXT: [[TMP10:%.*]] = call ptr @llvm.returnaddress.p0(i32 0)
diff --git a/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll b/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
index 55808d1f6d9f90..6deed9dee37533 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor-constexpr-alias.ll
@@ -62,10 +62,10 @@ define void @bar() addrspace(1) {
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.fini(
; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP3:%.*]] = icmp uge ptr addrspace(1) getelementptr inbounds (ptr addrspace(1), ptr addrspace(1) @__fini_array_end, i64 -1), @__fini_array_start
+; CHECK-NEXT: [[TMP3:%.*]] = icmp uge ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @__fini_array_end, i64 -8), @__fini_array_start
; CHECK-NEXT: br i1 [[TMP3]], label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
; CHECK: while.entry:
-; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ getelementptr inbounds (ptr addrspace(1), ptr addrspace(1) @__fini_array_end, i64 -1), [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
+; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ getelementptr inbounds (i8, ptr addrspace(1) @__fini_array_end, i64 -8), [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
; CHECK-NEXT: [[CALLBACK:%.*]] = load ptr, ptr addrspace(1) [[PTR]], align 8
; CHECK-NEXT: call void [[CALLBACK]]()
; CHECK-NEXT: [[NEXT]] = getelementptr ptr addrspace(1), ptr addrspace(1) [[PTR]], i64 -1
diff --git a/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll b/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
index d4f3ec2387e600..a9771628fbf713 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-ctor-dtor.ll
@@ -79,10 +79,10 @@ define internal void @bar() {
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.fini(
; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP3:%.*]] = icmp uge ptr addrspace(1) getelementptr inbounds (ptr addrspace(1), ptr addrspace(1) @__fini_array_end, i64 -1), @__fini_array_start
+; CHECK-NEXT: [[TMP3:%.*]] = icmp uge ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @__fini_array_end, i64 -8), @__fini_array_start
; CHECK-NEXT: br i1 [[TMP3]], label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
; CHECK: while.entry:
-; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ getelementptr inbounds (ptr addrspace(1), ptr addrspace(1) @__fini_array_end, i64 -1), [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
+; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ getelementptr inbounds (i8, ptr addrspace(1) @__fini_array_end, i64 -8), [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
; CHECK-NEXT: [[CALLBACK:%.*]] = load ptr, ptr addrspace(1) [[PTR]], align 8
; CHECK-NEXT: call void [[CALLBACK]]()
; CHECK-NEXT: [[NEXT]] = getelementptr ptr addrspace(1), ptr addrspace(1) [[PTR]], i64 -1
diff --git a/llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll b/llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
index 5a6a523ec522ff..dff627906c6a22 100644
--- a/llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
+++ b/llvm/test/CodeGen/AMDGPU/lower-multiple-ctor-dtor.ll
@@ -71,10 +71,10 @@ define internal void @bar.5() {
; CHECK-LABEL: define weak_odr amdgpu_kernel void @amdgcn.device.fini(
; CHECK-SAME: ) #[[ATTR1:[0-9]+]] {
; CHECK-NEXT: entry:
-; CHECK-NEXT: [[TMP3:%.*]] = icmp uge ptr addrspace(1) getelementptr inbounds (ptr addrspace(1), ptr addrspace(1) @__fini_array_end, i64 -1), @__fini_array_start
+; CHECK-NEXT: [[TMP3:%.*]] = icmp uge ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @__fini_array_end, i64 -8), @__fini_array_start
; CHECK-NEXT: br i1 [[TMP3]], label [[WHILE_ENTRY:%.*]], label [[WHILE_END:%.*]]
; CHECK: while.entry:
-; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ getelementptr inbounds (ptr addrspace(1), ptr addrspace(1) @__fini_array_end, i64 -1), [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
+; CHECK-NEXT: [[PTR:%.*]] = phi ptr addrspace(1) [ getelementptr inbounds (i8, ptr addrspace(1) @__fini_array_end, i64 -8), [[ENTRY:%.*]] ], [ [[NEXT:%.*]], [[WHILE_ENTRY]] ]
; CHECK-NEXT: [[CALLBACK:%.*]] = load ptr, ptr addrspace(1) [[PTR]], align 8
; CHECK-NEXT: call void [[CALLBACK]]()
; CHECK-NEXT: [[NEXT]] = getelementptr ptr addrspace(1), ptr addrspace(1) [[PTR]], i64 -1
diff --git a/llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll b/llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
index def886f933d081..5bfafae6a88e88 100644
--- a/llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
+++ b/llvm/test/CodeGen/DirectX/bugfix_150050_data_scalarize_const_gep.ll
@@ -11,7 +11,7 @@ define void @CSMain() {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: [[AFRAGPACKED_I_SCALARIZE:%.*]] = alloca [4 x i32], align 16
;
-; SCHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds [10 x [10 x [4 x i32]]], ptr addrspace(3) @aTile.scalarized, i32 0, i32 1
+; SCHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i8, ptr addrspace(3) @aTile.scalarized, i32 160
; SCHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds [10 x [4 x i32]], ptr addrspace(3) [[GEP0]], i32 0, i32 2
; SCHECK-NEXT: [[LOAD:%.*]] = load <4 x i32>, ptr addrspace(3) [[GEP1]], align 16
; SCHECK-NEXT: store <4 x i32> [[LOAD]], ptr [[AFRAGPACKED_I_SCALARIZE]], align 16
@@ -19,10 +19,10 @@ define void @CSMain() {
; FCHECK-NEXT: [[AFRAGPACKED_I_SCALARIZE_I14:%.*]] = getelementptr [4 x i32], ptr [[AFRAGPACKED_I_SCALARIZE]], i32 0, i32 1
; FCHECK-NEXT: [[AFRAGPACKED_I_SCALARIZE_I25:%.*]] = getelementptr [4 x i32], ptr [[AFRAGPACKED_I_SCALARIZE]], i32 0, i32 2
; FCHECK-NEXT: [[AFRAGPACKED_I_SCALARIZE_I36:%.*]] = getelementptr [4 x i32], ptr [[AFRAGPACKED_I_SCALARIZE]], i32 0, i32 3
-; FCHECK-NEXT: [[DOTI07:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds ([400 x i32], ptr addrspace(3) @aTile.scalarized.1dim, i32 0, i32 48), align 16
-; FCHECK-NEXT: [[DOTI119:%.*]] = load i32, ptr addrspace(3) getelementptr ([400 x i32], ptr addrspace(3) @aTile.scalarized.1dim, i32 0, i32 49), align 4
-; FCHECK-NEXT: [[DOTI2211:%.*]] = load i32, ptr addrspace(3) getelementptr ([400 x i32], ptr addrspace(3) @aTile.scalarized.1dim, i32 0, i32 50), align 8
-; FCHECK-NEXT: [[DOTI3313:%.*]] = load i32, ptr addrspace(3) getelementptr ([400 x i32], ptr addrspace(3) @aTile.scalarized.1dim, i32 0, i32 51), align 4
+; FCHECK-NEXT: [[DOTI07:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds (i8, ptr addrspace(3) @aTile.scalarized.1dim, i32 192), align 16
+; FCHECK-NEXT: [[DOTI119:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @aTile.scalarized.1dim, i32 196), align 4
+; FCHECK-NEXT: [[DOTI2211:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @aTile.scalarized.1dim, i32 200), align 8
+; FCHECK-NEXT: [[DOTI3313:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @aTile.scalarized.1dim, i32 204), align 4
; FCHECK-NEXT: store i32 [[DOTI07]], ptr [[AFRAGPACKED_I_SCALARIZE]], align 16
; FCHECK-NEXT: store i32 [[DOTI119]], ptr [[AFRAGPACKED_I_SCALARIZE_I14]], align 4
; FCHECK-NEXT: store i32 [[DOTI2211]], ptr [[AFRAGPACKED_I_SCALARIZE_I25]], align 8
@@ -46,7 +46,7 @@ define void @Main() {
; SCHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(3) [[GEP1]], align 16
; SCHECK-NEXT: store i32 [[LOAD]], ptr [[BFRAGPACKED_I]], align 16
;
-; FCHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds ([100 x i32], ptr addrspace(3) @bTile.1dim, i32 0, i32 11), align 16
+; FCHECK-NEXT: [[LOAD:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds (i8, ptr addrspace(3) @bTile.1dim, i32 44), align 16
; FCHECK-NEXT: store i32 [[LOAD]], ptr [[BFRAGPACKED_I]], align 16
;
; CHECK-NEXT: ret void
@@ -59,12 +59,12 @@ entry:
define void @global_nested_geps_3d() {
; CHECK-LABEL: define void @global_nested_geps_3d() {
-; SCHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds [2 x [2 x [2 x i32]]], ptr @cTile.scalarized, i32 0, i32 1
+; SCHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i8, ptr @cTile.scalarized, i32 16
; SCHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds [2 x [2 x i32]], ptr [[GEP0]], i32 0, i32 1
; SCHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds [2 x i32], ptr [[GEP1]], i32 0, i32 1
; SCHECK-NEXT: load i32, ptr [[GEP2]], align 4
;
-; FCHECK-NEXT: load i32, ptr getelementptr inbounds ([8 x i32], ptr @cTile.scalarized.1dim, i32 0, i32 7), align 4
+; FCHECK-NEXT: load i32, ptr getelementptr inbounds (i8, ptr @cTile.scalarized.1dim, i32 28), align 4
;
; CHECK-NEXT: ret void
%1 = load i32, i32* getelementptr inbounds (<2 x i32>, <2 x i32>* getelementptr inbounds ([2 x <2 x i32>], [2 x <2 x i32>]* getelementptr inbounds ([2 x [2 x <2 x i32>]], [2 x [2 x <2 x i32>]]* @cTile, i32 0, i32 1), i32 0, i32 1), i32 0, i32 1), align 4
@@ -73,13 +73,13 @@ define void @global_nested_geps_3d() {
define void @global_nested_geps_4d() {
; CHECK-LABEL: define void @global_nested_geps_4d() {
-; SCHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds [2 x [2 x [2 x [2 x i32]]]], ptr @dTile.scalarized, i32 0, i32 1
+; SCHECK-NEXT: [[GEP0:%.*]] = getelementptr inbounds i8, ptr @dTile.scalarized, i32 32
; SCHECK-NEXT: [[GEP1:%.*]] = getelementptr inbounds [2 x [2 x [2 x i32]]], ptr [[GEP0]], i32 0, i32 1
; SCHECK-NEXT: [[GEP2:%.*]] = getelementptr inbounds [2 x [2 x i32]], ptr [[GEP1]], i32 0, i32 1
; SCHECK-NEXT: [[GEP3:%.*]] = getelementptr inbounds [2 x i32], ptr [[GEP2]], i32 0, i32 1
; SCHECK-NEXT: load i32, ptr [[GEP3]], align 4
;
-; FCHECK-NEXT: load i32, ptr getelementptr inbounds ([16 x i32], ptr @dTile.scalarized.1dim, i32 0, i32 15), align 4
+; FCHECK-NEXT: load i32, ptr getelementptr inbounds (i8, ptr @dTile.scalarized.1dim, i32 60), align 4
;
; CHECK-NEXT: ret void
%1 = load i32, i32* getelementptr inbounds (<2 x i32>, <2 x i32>* getelementptr inbounds ([2 x <2 x i32>], [2 x <2 x i32>]* getelementptr inbounds ([2 x [2 x <2 x i32>]], [2 x [2 x <2 x i32>]]* getelementptr inbounds ([2 x [2 x [2 x <2 x i32>]]], [2 x [2 x [2 x <2 x i32>]]]* @dTile, i32 0, i32 1), i32 0, i32 1), i32 0, i32 1), i32 0, i32 1), align 4
diff --git a/llvm/test/CodeGen/DirectX/flatten-array.ll b/llvm/test/CodeGen/DirectX/flatten-array.ll
index a2e105537ab883..b9476543c5335d 100644
--- a/llvm/test/CodeGen/DirectX/flatten-array.ll
+++ b/llvm/test/CodeGen/DirectX/flatten-array.ll
@@ -124,7 +124,7 @@ define void @gep_4d_test () {
define void @global_gep_load() {
; CHECK-LABEL: define void @global_gep_load(
- ; CHECK: {{.*}} = load i32, ptr getelementptr inbounds ([24 x i32], ptr @a.1dim, i32 0, i32 6), align 4
+ ; CHECK: {{.*}} = load i32, ptr getelementptr inbounds (i8, ptr @a.1dim, i64 24), align 4
; CHECK-NEXT: ret void
%1 = getelementptr inbounds [2 x [3 x [4 x i32]]], [2 x [3 x [4 x i32]]]* @a, i32 0, i32 0
%2 = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]]* %1, i32 0, i32 1
@@ -135,7 +135,7 @@ define void @global_gep_load() {
define void @global_nested_geps() {
; CHECK-LABEL: define void @global_nested_geps(
- ; CHECK: {{.*}} = load i32, ptr getelementptr inbounds ([24 x i32], ptr @a.1dim, i32 0, i32 6), align 4
+ ; CHECK: {{.*}} = load i32, ptr getelementptr inbounds (i8, ptr @a.1dim, i64 24), align 4
; CHECK-NEXT: ret void
%1 = load i32, i32* getelementptr inbounds ([4 x i32], [4 x i32]* getelementptr inbounds ([3 x [4 x i32]], [3 x [4 x i32]]* getelementptr inbounds ([2 x [3 x [4 x i32]]], [2 x [3 x [4 x i32]]]* @a, i32 0, i32 0), i32 0, i32 1), i32 0, i32 2), align 4
ret void
@@ -185,7 +185,7 @@ define void @global_incomplete_gep_chain(i32 %row, i32 %col) {
}
define void @global_gep_store() {
- ; CHECK: store i32 1, ptr getelementptr inbounds ([24 x i32], ptr @b.1dim, i32 0, i32 13), align 4
+ ; CHECK: store i32 1, ptr getelementptr inbounds (i8, ptr @b.1dim, i64 52), align 4
; CHECK-NEXT: ret void
%1 = getelementptr inbounds [2 x [3 x [4 x i32]]], [2 x [3 x [4 x i32]]]* @b, i32 0, i32 1
%2 = getelementptr inbounds [3 x [4 x i32]], [3 x [4 x i32]]* %1, i32 0, i32 0
@@ -211,7 +211,7 @@ define void @two_index_gep() {
define void @two_index_gep_const() {
; CHECK-LABEL: define void @two_index_gep_const(
- ; CHECK-NEXT: load float, ptr addrspace(3) getelementptr inbounds nuw ([4 x float], ptr addrspace(3) @g.1dim, i32 0, i32 3), align 4
+ ; CHECK-NEXT: load float, ptr addrspace(3) getelementptr inbounds nuw (i8, ptr addrspace(3) @g.1dim, i64 12), align 4
; CHECK-NEXT: ret void
%1 = getelementptr inbounds nuw [2 x [2 x float]], ptr addrspace(3) @g, i32 0, i32 1, i32 1
%3 = load float, ptr addrspace(3) %1, align 4
diff --git a/llvm/test/CodeGen/DirectX/flatten-bug-117273.ll b/llvm/test/CodeGen/DirectX/flatten-bug-117273.ll
index 78971b8954150c..1eaf0e6bf233ff 100644
--- a/llvm/test/CodeGen/DirectX/flatten-bug-117273.ll
+++ b/llvm/test/CodeGen/DirectX/flatten-bug-117273.ll
@@ -8,8 +8,8 @@
define internal void @main() {
; CHECK-LABEL: define internal void @main() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[DOTI0:%.*]] = load float, ptr getelementptr ([6 x float], ptr @ZerroInitArr.1dim, i32 0, i32 3), align 16
-; CHECK-NEXT: [[DOTI03:%.*]] = load float, ptr getelementptr ([6 x float], ptr @ZerroInitArr.1dim, i32 0, i32 6), align 16
+; CHECK-NEXT: [[DOTI01:%.*]] = load float, ptr getelementptr (i8, ptr @ZerroInitArr.1dim, i32 12), align 16
+; CHECK-NEXT: [[DOTI032:%.*]] = load float, ptr getelementptr (i8, ptr @ZerroInitArr.1dim, i32 24), align 16
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/CodeGen/DirectX/legalize-i8.ll b/llvm/test/CodeGen/DirectX/legalize-i8.ll
index 7eb47ba661f4cd..cd56d2d1750cdb 100644
--- a/llvm/test/CodeGen/DirectX/legalize-i8.ll
+++ b/llvm/test/CodeGen/DirectX/legalize-i8.ll
@@ -166,7 +166,7 @@ define i32 @i8_gep_store() {
@g = local_unnamed_addr addrspace(3) global [2 x float] zeroinitializer, align 4
define float @i8_gep_global_index() {
; CHECK-LABEL: define float @i8_gep_global_index(
- ; CHECK-NEXT: [[LOAD:%.*]] = load float, ptr addrspace(3) getelementptr inbounds nuw ([2 x float], ptr addrspace(3) @g, i32 0, i32 1), align 4
+ ; CHECK-NEXT: [[LOAD:%.*]] = load float, ptr addrspace(3) getelementptr inbounds nuw (i8, ptr addrspace(3) @g, i32 4), align 4
; CHECK-NEXT: ret float [[LOAD]]
%1 = getelementptr inbounds nuw i8, ptr addrspace(3) @g, i32 4
%2 = load float, ptr addrspace(3) %1, align 4
@@ -175,7 +175,7 @@ define float @i8_gep_global_index() {
define float @i8_gep_global_constexpr() {
; CHECK-LABEL: define float @i8_gep_global_constexpr(
- ; CHECK-NEXT: [[LOAD:%.*]] = load float, ptr addrspace(3) getelementptr inbounds nuw ([2 x float], ptr addrspace(3) @g, i32 0, i32 1), align 4
+ ; CHECK-NEXT: [[LOAD:%.*]] = load float, ptr addrspace(3) getelementptr inbounds nuw (i8, ptr addrspace(3) @g, i32 4), align 4
; CHECK-NEXT: ret float [[LOAD]]
%1 = load float, ptr addrspace(3) getelementptr inbounds nuw (i8, ptr addrspace(3) @g, i32 4), align 4
ret float %1
diff --git a/llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll b/llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
index a57130a038fdcf..788fe640f11e78 100644
--- a/llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
+++ b/llvm/test/CodeGen/DirectX/llc-vector-load-scalarize.ll
@@ -24,15 +24,16 @@
define <4 x i32> @load_array_vec_test() #0 {
; CHECK-LABEL: define <4 x i32> @load_array_vec_test(
; CHECK-SAME: ) #[[ATTR0:[0-9]+]] {
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 0
+; CHECK-NEXT: [[TMP1:%.*]] = bitcast ptr addrspace(3) @arrayofVecData.scalarized.1dim to ptr addrspace(3)
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [8 x i32], ptr addrspace(3) [[TMP1]], i32 0, i32 0
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(3) [[GEP]], align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 1), align 4
-; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 2), align 4
-; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 3), align 4
-; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 4), align 4
-; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 5), align 4
-; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 6), align 4
-; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 7), align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 4), align 4
+; CHECK-NEXT: [[TMP6:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 8), align 4
+; CHECK-NEXT: [[TMP8:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 12), align 4
+; CHECK-NEXT: [[TMP10:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 16), align 4
+; CHECK-NEXT: [[TMP12:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 20), align 4
+; CHECK-NEXT: [[TMP14:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 24), align 4
+; CHECK-NEXT: [[TMP16:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 28), align 4
; CHECK-NEXT: [[DOTI05:%.*]] = add i32 [[TMP2]], [[TMP10]]
; CHECK-NEXT: [[DOTI16:%.*]] = add i32 [[TMP4]], [[TMP12]]
; CHECK-NEXT: [[DOTI27:%.*]] = add i32 [[TMP6]], [[TMP14]]
@@ -53,11 +54,12 @@ define <4 x i32> @load_array_vec_test() #0 {
define <4 x i32> @load_vec_test() #0 {
; CHECK-LABEL: define <4 x i32> @load_vec_test(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [4 x i32], ptr addrspace(3) @vecData.scalarized, i32 0, i32 0
+; CHECK-NEXT: [[TMP6:%.*]] = bitcast ptr addrspace(3) @vecData.scalarized to ptr addrspace(3)
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [4 x i32], ptr addrspace(3) [[TMP6]], i32 0, i32 0
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(3) [[GEP]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(3) getelementptr ([4 x i32], ptr addrspace(3) @vecData.scalarized, i32 0, i32 1), align 4
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) getelementptr ([4 x i32], ptr addrspace(3) @vecData.scalarized, i32 0, i32 2), align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) getelementptr ([4 x i32], ptr addrspace(3) @vecData.scalarized, i32 0, i32 3), align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @vecData.scalarized, i32 4), align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @vecData.scalarized, i32 8), align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @vecData.scalarized, i32 12), align 4
; CHECK-NEXT: [[DOTUPTO0:%.*]] = insertelement <4 x i32> poison, i32 [[TMP1]], i32 0
; CHECK-NEXT: [[DOTUPTO1:%.*]] = insertelement <4 x i32> [[DOTUPTO0]], i32 [[TMP2]], i32 1
; CHECK-NEXT: [[DOTUPTO2:%.*]] = insertelement <4 x i32> [[DOTUPTO1]], i32 [[TMP3]], i32 2
@@ -71,10 +73,10 @@ define <4 x i32> @load_vec_test() #0 {
define <4 x i32> @load_vec_from_scalar_gep_test() #0 {
; CHECK-LABEL: define <4 x i32> @load_vec_from_scalar_gep_test(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[DOTI04:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds nuw ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 4), align 4
-; CHECK-NEXT: [[DOTI116:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 5), align 4
-; CHECK-NEXT: [[DOTI228:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 6), align 4
-; CHECK-NEXT: [[DOTI3310:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 7), align 4
+; CHECK-NEXT: [[DOTI04:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds nuw (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 16), align 4
+; CHECK-NEXT: [[DOTI116:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 20), align 4
+; CHECK-NEXT: [[DOTI228:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 24), align 4
+; CHECK-NEXT: [[DOTI3310:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 28), align 4
; CHECK-NEXT: [[DOTUPTO011:%.*]] = insertelement <4 x i32> poison, i32 [[DOTI04]], i32 0
; CHECK-NEXT: [[DOTUPTO112:%.*]] = insertelement <4 x i32> [[DOTUPTO011]], i32 [[DOTI116]], i32 1
; CHECK-NEXT: [[DOTUPTO213:%.*]] = insertelement <4 x i32> [[DOTUPTO112]], i32 [[DOTI228]], i32 2
@@ -89,10 +91,10 @@ define <4 x i32> @load_vec_from_scalar_gep_test() #0 {
define <4 x i32> @load_vec_from_i8_gep_test() #0 {
; CHECK-LABEL: define <4 x i32> @load_vec_from_i8_gep_test(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[DOTI04:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds nuw ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 4), align 4
-; CHECK-NEXT: [[DOTI116:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 5), align 4
-; CHECK-NEXT: [[DOTI228:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 6), align 4
-; CHECK-NEXT: [[DOTI3310:%.*]] = load i32, ptr addrspace(3) getelementptr ([8 x i32], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 7), align 4
+; CHECK-NEXT: [[DOTI04:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds nuw (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 16), align 4
+; CHECK-NEXT: [[DOTI116:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 20), align 4
+; CHECK-NEXT: [[DOTI228:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 24), align 4
+; CHECK-NEXT: [[DOTI3310:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 28), align 4
; CHECK-NEXT: [[DOTUPTO011:%.*]] = insertelement <4 x i32> poison, i32 [[DOTI04]], i32 0
; CHECK-NEXT: [[DOTUPTO112:%.*]] = insertelement <4 x i32> [[DOTUPTO011]], i32 [[DOTI116]], i32 1
; CHECK-NEXT: [[DOTUPTO213:%.*]] = insertelement <4 x i32> [[DOTUPTO112]], i32 [[DOTI228]], i32 2
@@ -205,15 +207,16 @@ define <4 x i32> @load_static_array_of_vec_from_i8_gep_test(i32 %index) #0 {
define <4 x i32> @multid_load_test() #0 {
; CHECK-LABEL: define <4 x i32> @multid_load_test(
; CHECK-SAME: ) #[[ATTR0]] {
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [36 x i32], ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 0, i32 0
+; CHECK-NEXT: [[TMP7:%.*]] = bitcast ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim to ptr addrspace(3)
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [36 x i32], ptr addrspace(3) [[TMP7]], i32 0, i32 0
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr addrspace(3) [[GEP]], align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(3) getelementptr ([36 x i32], ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 0, i32 1), align 4
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) getelementptr ([36 x i32], ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 0, i32 2), align 4
-; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) getelementptr ([36 x i32], ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 0, i32 3), align 4
-; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds ([36 x i32], ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 0, i32 16), align 4
-; CHECK-NEXT: [[DOTI13:%.*]] = load i32, ptr addrspace(3) getelementptr ([36 x i32], ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 0, i32 17), align 4
-; CHECK-NEXT: [[DOTI25:%.*]] = load i32, ptr addrspace(3) getelementptr ([36 x i32], ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 0, i32 18), align 4
-; CHECK-NEXT: [[DOTI37:%.*]] = load i32, ptr addrspace(3) getelementptr ([36 x i32], ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 0, i32 19), align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 4), align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 8), align 4
+; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 12), align 4
+; CHECK-NEXT: [[TMP5:%.*]] = load i32, ptr addrspace(3) getelementptr inbounds (i8, ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 64), align 4
+; CHECK-NEXT: [[DOTI13:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 68), align 4
+; CHECK-NEXT: [[DOTI25:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 72), align 4
+; CHECK-NEXT: [[DOTI37:%.*]] = load i32, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @groupshared2dArrayofVectors.scalarized.1dim, i32 76), align 4
; CHECK-NEXT: [[DOTI08:%.*]] = add i32 [[TMP1]], [[TMP5]]
; CHECK-NEXT: [[DOTI19:%.*]] = add i32 [[TMP2]], [[DOTI13]]
; CHECK-NEXT: [[DOTI210:%.*]] = add i32 [[TMP3]], [[DOTI25]]
diff --git a/llvm/test/CodeGen/DirectX/llc-vector-store-scalarize.ll b/llvm/test/CodeGen/DirectX/llc-vector-store-scalarize.ll
index e5ec62cee759ef..f98c7a317f8d9f 100644
--- a/llvm/test/CodeGen/DirectX/llc-vector-store-scalarize.ll
+++ b/llvm/test/CodeGen/DirectX/llc-vector-store-scalarize.ll
@@ -21,7 +21,7 @@ define void @store_array_vec_test () local_unnamed_addr #0 {
; CHECK-LABEL: store_vec_test
define void @store_vec_test(<4 x i32> %inputVec) #0 {
- ; CHECK-COUNT-4: store i32 %inputVec.{{.*}}, ptr addrspace(3) {{(@vecData.scalarized|getelementptr \(i32, ptr addrspace\(3\) @vecData.scalarized, i32 .*\)|%.*)}}, align 4
+ ; CHECK-COUNT-4: store i32 %inputVec.{{.*}}, ptr addrspace(3) {{(@vecData.scalarized|getelementptr \(i8, ptr addrspace\(3\) @vecData.scalarized, i32 .*\)|%.*)}}, align 4
; CHECK-NEXT: ret void
store <4 x i32> %inputVec, <4 x i32> addrspace(3)* @"vecData", align 4
ret void
diff --git a/llvm/test/CodeGen/DirectX/scalar-load.ll b/llvm/test/CodeGen/DirectX/scalar-load.ll
index ed1e9109b7b182..b200849c70f4d6 100644
--- a/llvm/test/CodeGen/DirectX/scalar-load.ll
+++ b/llvm/test/CodeGen/DirectX/scalar-load.ll
@@ -29,7 +29,7 @@ define <3 x float> @load_array_vec_test() #0 {
; CHECK-LABEL: load_vec_test
define <4 x i32> @load_vec_test() #0 {
- ; CHECK-COUNT-4: load i32, ptr addrspace(3) {{(@vecData.scalarized|getelementptr \(i32, ptr addrspace\(3\) @vecData.scalarized, i32 .*\)|%.*)}}, align {{.*}}
+ ; CHECK-COUNT-4: load i32, ptr addrspace(3) {{(@vecData.scalarized|getelementptr \(i8, ptr addrspace\(3\) @vecData.scalarized, i32 .*\)|%.*)}}, align {{.*}}
%1 = load <4 x i32>, <4 x i32> addrspace(3)* @"vecData", align 4
ret <4 x i32> %1
}
diff --git a/llvm/test/CodeGen/DirectX/scalar-store.ll b/llvm/test/CodeGen/DirectX/scalar-store.ll
index 6cf97bda984fce..af8dd9b1820d1c 100644
--- a/llvm/test/CodeGen/DirectX/scalar-store.ll
+++ b/llvm/test/CodeGen/DirectX/scalar-store.ll
@@ -14,15 +14,15 @@
; CHECK-LABEL: store_array_vec_test
define void @store_array_vec_test () local_unnamed_addr #0 {
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [6 x float], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 0
+; CHECK-NEXT: [[BC:%.*]] = bitcast ptr addrspace(3) @arrayofVecData.scalarized.1dim to ptr addrspace(3)
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [6 x float], ptr addrspace(3) [[BC]], i32 0, i32 0
; CHECK-NEXT: store float 1.000000e+00, ptr addrspace(3) [[GEP]], align 16
-; CHECK-NEXT: store float 2.000000e+00, ptr addrspace(3) getelementptr ([6 x float], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 1), align 4
-; CHECK-NEXT: store float 3.000000e+00, ptr addrspace(3) getelementptr ([6 x float], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 2), align 8
-; CHECK-NEXT: store float 2.000000e+00, ptr addrspace(3) getelementptr inbounds ([6 x float], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 3), align 16
-; CHECK-NEXT: store float 4.000000e+00, ptr addrspace(3) getelementptr ([6 x float], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 4), align 4
-; CHECK-NEXT: store float 6.000000e+00, ptr addrspace(3) getelementptr ([6 x float], ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 0, i32 5), align 8
+; CHECK-NEXT: store float 2.000000e+00, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 4), align 4
+; CHECK-NEXT: store float 3.000000e+00, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 8), align 8
+; CHECK-NEXT: store float 2.000000e+00, ptr addrspace(3) getelementptr inbounds (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 12), align 16
+; CHECK-NEXT: store float 4.000000e+00, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 16), align 4
+; CHECK-NEXT: store float 6.000000e+00, ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @arrayofVecData.scalarized.1dim, i32 20), align 8
; CHECK-NEXT: ret void
-;
store <3 x float> <float 1.000000e+00, float 2.000000e+00, float 3.000000e+00>, ptr addrspace(3) @"arrayofVecData", align 16
store <3 x float> <float 2.000000e+00, float 4.000000e+00, float 6.000000e+00>, ptr addrspace(3) getelementptr inbounds (i8, ptr addrspace(3) @"arrayofVecData", i32 12), align 16
ret void
@@ -31,14 +31,15 @@ define void @store_array_vec_test () local_unnamed_addr #0 {
; CHECK-LABEL: store_vec_test
define void @store_vec_test(<4 x i32> %inputVec) #0 {
; CHECK-NEXT: [[INPUTVEC_I01:%.*]] = extractelement <4 x i32> %inputVec, i32 0
-; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [4 x i32], ptr addrspace(3) @vecData.scalarized, i32 0, i32 0
+; CHECK-NEXT: [[BC:%.*]] = bitcast ptr addrspace(3) @vecData.scalarized to ptr
+; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds nuw [4 x i32], ptr addrspace(3) [[BC]], i32 0, i32 0
; CHECK-NEXT: store i32 [[INPUTVEC_I01]], ptr addrspace(3) [[GEP]], align 4
; CHECK-NEXT: [[INPUTVEC_I12:%.*]] = extractelement <4 x i32> %inputVec, i32 1
-; CHECK-NEXT: store i32 [[INPUTVEC_I12]], ptr addrspace(3) getelementptr ([4 x i32], ptr addrspace(3) @vecData.scalarized, i32 0, i32 1), align 4
+; CHECK-NEXT: store i32 [[INPUTVEC_I12]], ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @vecData.scalarized, i32 4), align 4
; CHECK-NEXT: [[INPUTVEC_I23:%.*]] = extractelement <4 x i32> %inputVec, i32 2
-; CHECK-NEXT: store i32 [[INPUTVEC_I23]], ptr addrspace(3) getelementptr ([4 x i32], ptr addrspace(3) @vecData.scalarized, i32 0, i32 2), align 4
+; CHECK-NEXT: store i32 [[INPUTVEC_I23]], ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @vecData.scalarized, i32 8), align 4
; CHECK-NEXT: [[INPUTVEC_I34:%.*]] = extractelement <4 x i32> %inputVec, i32 3
-; CHECK-NEXT: store i32 [[INPUTVEC_I34]], ptr addrspace(3) getelementptr ([4 x i32], ptr addrspace(3) @vecData.scalarized, i32 0, i32 3), align 4
+; CHECK-NEXT: store i32 [[INPUTVEC_I34]], ptr addrspace(3) getelementptr (i8, ptr addrspace(3) @vecData.scalarized, i32 12), align 4
; CHECK-NEXT: ret void
;
store <4 x i32> %inputVec, <4 x i32> addrspace(3)* @"vecData", align 4
diff --git a/llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll b/llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll
index 420b77645f0b70..08e58d0feb0d19 100644
--- a/llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll
+++ b/llvm/test/CodeGen/DirectX/scalarize-static-array-of-float-vectors.ll
@@ -7,12 +7,12 @@
define internal void @main() #1 {
; CHECK-LABEL: define internal void @main() {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[DOTI0:%.*]] = load float, ptr getelementptr inbounds ([24 x float], ptr @StaticArr.scalarized.1dim, i32 0, i32 3), align 16
-; CHECK-NEXT: [[DOTI11:%.*]] = load float, ptr getelementptr (float, ptr getelementptr inbounds ([24 x float], ptr @StaticArr.scalarized.1dim, i32 0, i32 3), i32 1), align 4
-; CHECK-NEXT: [[DOTI22:%.*]] = load float, ptr getelementptr (float, ptr getelementptr inbounds ([24 x float], ptr @StaticArr.scalarized.1dim, i32 0, i32 3), i32 2), align 8
-; CHECK-NEXT: [[DOTI03:%.*]] = load float, ptr getelementptr inbounds ([24 x float], ptr @StaticArr.scalarized.1dim, i32 0, i32 6), align 16
-; CHECK-NEXT: [[DOTI15:%.*]] = load float, ptr getelementptr (float, ptr getelementptr inbounds ([24 x float], ptr @StaticArr.scalarized.1dim, i32 0, i32 6), i32 1), align 4
-; CHECK-NEXT: [[DOTI27:%.*]] = load float, ptr getelementptr (float, ptr getelementptr inbounds ([24 x float], ptr @StaticArr.scalarized.1dim, i32 0, i32 6), i32 2), align 8
+; CHECK-NEXT: [[DOTI0:%.*]] = load float, ptr getelementptr inbounds (i8, ptr @StaticArr.scalarized.1dim, i32 12), align 16
+; CHECK-NEXT: [[DOTI1:%.*]] = load float, ptr getelementptr (i8, ptr getelementptr inbounds (i8, ptr @StaticArr.scalarized.1dim, i32 12), i32 4), align 4
+; CHECK-NEXT: [[DOTI2:%.*]] = load float, ptr getelementptr (i8, ptr getelementptr inbounds (i8, ptr @StaticArr.scalarized.1dim, i32 12), i32 8), align 8
+; CHECK-NEXT: [[DOTI01:%.*]] = load float, ptr getelementptr inbounds (i8, ptr @StaticArr.scalarized.1dim, i32 24), align 16
+; CHECK-NEXT: [[DOTI12:%.*]] = load float, ptr getelementptr (i8, ptr getelementptr inbounds (i8, ptr @StaticArr.scalarized.1dim, i32 24), i32 4), align 4
+; CHECK-NEXT: [[DOTI23:%.*]] = load float, ptr getelementptr (i8, ptr getelementptr inbounds (i8, ptr @StaticArr.scalarized.1dim, i32 24), i32 8), align 8
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/CodeGen/RISCV/riscv-promote-constant.ll b/llvm/test/CodeGen/RISCV/riscv-promote-constant.ll
index 2bde6013b3640c..821b23cc6ebfab 100644
--- a/llvm/test/CodeGen/RISCV/riscv-promote-constant.ll
+++ b/llvm/test/CodeGen/RISCV/riscv-promote-constant.ll
@@ -37,7 +37,7 @@ define double @multiple_doubles(double %a, double %b) {
; CHECK-LABEL: define double @multiple_doubles(
; CHECK-SAME: double [[A:%.*]], double [[B:%.*]]) #[[ATTR0]] {
; CHECK-NEXT: [[ENTRY:.*:]]
-; CHECK-NEXT: [[DOUBLE_VAL1:%.*]] = load double, ptr getelementptr inbounds ([2 x double], ptr @.promoted_doubles.multiple_doubles, i64 0, i64 1), align 8
+; CHECK-NEXT: [[DOUBLE_VAL1:%.*]] = load double, ptr getelementptr inbounds (i8, ptr @.promoted_doubles.multiple_doubles, i64 8), align 8
; CHECK-NEXT: [[ADD3:%.*]] = load double, ptr @.promoted_doubles.multiple_doubles, align 8
; CHECK-NEXT: [[ADD2:%.*]] = fadd double [[A]], [[ADD3]]
; CHECK-NEXT: [[ADD4:%.*]] = fadd double [[B]], [[DOUBLE_VAL1]]
@@ -80,14 +80,14 @@ define double @multiple_doubles_multi_bb(double %a, i1 %cond) {
; CHECK-NEXT: [[ENTRY:.*:]]
; CHECK-NEXT: br i1 [[COND]], label %[[IF_TRUE:.*]], label %[[IF_FALSE:.*]]
; CHECK: [[IF_TRUE]]:
-; CHECK-NEXT: [[DOUBLE_VAL2:%.*]] = load double, ptr getelementptr inbounds ([2 x double], ptr @.promoted_doubles.multiple_doubles_multi_bb, i64 0, i64 1), align 8
+; CHECK-NEXT: [[DOUBLE_VAL2:%.*]] = load double, ptr getelementptr inbounds (i8, ptr @.promoted_doubles.multiple_doubles_multi_bb, i64 8), align 8
; CHECK-NEXT: [[DOUBLE_VAL:%.*]] = load double, ptr @.promoted_doubles.multiple_doubles_multi_bb, align 8
; CHECK-NEXT: [[ADD_T:%.*]] = fadd double [[A]], [[DOUBLE_VAL]]
; CHECK-NEXT: [[MUL_T:%.*]] = fmul double [[ADD_T]], [[DOUBLE_VAL2]]
; CHECK-NEXT: [[SUB_T:%.*]] = fsub double [[MUL_T]], [[DOUBLE_VAL]]
; CHECK-NEXT: br label %[[IF_END:.*]]
; CHECK: [[IF_FALSE]]:
-; CHECK-NEXT: [[DOUBLE_VAL3:%.*]] = load double, ptr getelementptr inbounds ([2 x double], ptr @.promoted_doubles.multiple_doubles_multi_bb, i64 0, i64 1), align 8
+; CHECK-NEXT: [[DOUBLE_VAL3:%.*]] = load double, ptr getelementptr inbounds (i8, ptr @.promoted_doubles.multiple_doubles_multi_bb, i64 8), align 8
; CHECK-NEXT: [[DOUBLE_VAL1:%.*]] = load double, ptr @.promoted_doubles.multiple_doubles_multi_bb, align 8
; CHECK-NEXT: [[ADD_F:%.*]] = fadd double [[A]], [[DOUBLE_VAL1]]
; CHECK-NEXT: [[MUL_F:%.*]] = fmul double [[ADD_F]], [[DOUBLE_VAL3]]
@@ -130,7 +130,7 @@ define double @multiple_doubles_phi(double %a, i1 %cond) {
; CHECK-NEXT: br label %[[IF_END]]
; CHECK: [[IF_END]]:
; CHECK-NEXT: [[PHI_VAL:%.*]] = phi double [ [[DOUBLE_VAL]], %[[IF_THEN]] ], [ [[A]], %[[ENTRY]] ]
-; CHECK-NEXT: [[DOUBLE_VAL1:%.*]] = load double, ptr getelementptr inbounds ([2 x double], ptr @.promoted_doubles.multiple_doubles_phi, i64 0, i64 1), align 8
+; CHECK-NEXT: [[DOUBLE_VAL1:%.*]] = load double, ptr getelementptr inbounds (i8, ptr @.promoted_doubles.multiple_doubles_phi, i64 8), align 8
; CHECK-NEXT: [[RES:%.*]] = fadd double [[PHI_VAL]], [[DOUBLE_VAL1]]
; CHECK-NEXT: ret double [[RES]]
;
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll
index fbcdb3d50afae3..133f3e3854b9d1 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_abilist.ll
@@ -25,7 +25,7 @@ define i32 @functional(i32 %a, i32 %b) {
define i32 @call_functional(i32 %a, i32 %b) {
; CHECK-LABEL: @call_functional.dfsan
- ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+ ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls
; CHECK: [[RO:%.*]] = select i1 {{.*}}, i32 [[BO]], i32 [[AO]]
; CHECK: store i32 [[RO]], ptr @__dfsan_retval_origin_tls, align 4
@@ -112,7 +112,7 @@ define ptr @ret_custom() {
define void @call_custom_without_ret(i32 %a, i32 %b) {
; CHECK: @call_custom_without_ret.dfsan
- ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+ ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK: [[AS:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -126,7 +126,7 @@ define void @call_custom_without_ret(i32 %a, i32 %b) {
define i32 @call_custom_with_ret(i32 %a, i32 %b) {
; CHECK: @call_custom_with_ret.dfsan
; CHECK: %originreturn = alloca i32, align 4
- ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+ ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK: %labelreturn = alloca i8, align 1
; CHECK: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
@@ -144,7 +144,7 @@ define i32 @call_custom_with_ret(i32 %a, i32 %b) {
define void @call_custom_varg_without_ret(i32 %a, i32 %b) {
; CHECK: @call_custom_varg_without_ret.dfsan
; CHECK: %originva = alloca [1 x i32], align 4
- ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+ ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK: %labelva = alloca [1 x i8], align 1
; CHECK: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
@@ -166,7 +166,7 @@ define i32 @call_custom_varg_with_ret(i32 %a, i32 %b) {
; CHECK: @call_custom_varg_with_ret.dfsan
; CHECK: %originreturn = alloca i32, align 4
; CHECK: %originva = alloca [1 x i32], align 4
- ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+ ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls
; CHECK: %labelreturn = alloca i8, align 1
; CHECK: %labelva = alloca [1 x i8], align 1
@@ -191,7 +191,7 @@ define i32 @call_custom_varg_with_ret(i32 %a, i32 %b) {
define i32 @call_custom_cb_with_ret(i32 %a, i32 %b) {
; CHECK: @call_custom_cb_with_ret.dfsan
; CHECK: %originreturn = alloca i32, align 4
- ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+ ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK: %labelreturn = alloca i8, align 1
; CHECK: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
@@ -208,7 +208,7 @@ define i32 @call_custom_cb_with_ret(i32 %a, i32 %b) {
define void @call_custom_cb_without_ret(i32 %a, i32 %b) {
; CHECK-LABEL: @call_custom_cb_without_ret.dfsan
- ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+ ; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK: [[AS:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -226,7 +226,7 @@ define void @call_custom_cb_without_ret(i32 %a, i32 %b) {
; CHECK-NEXT: ret i32 [[R]]
; CHECK: define linkonce_odr void @"dfso$custom_without_ret"(i32 %0, i32 %1)
-; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK-NEXT: [[AS:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -235,7 +235,7 @@ define void @call_custom_cb_without_ret(i32 %a, i32 %b) {
; CHECK: define linkonce_odr i32 @"dfso$custom_with_ret"(i32 %0, i32 %1)
; CHECK: %originreturn = alloca i32, align 4
-; CHECK-NEXT: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[AO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: %labelreturn = alloca i8, align 1
; CHECK-NEXT: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
@@ -257,8 +257,8 @@ define void @call_custom_cb_without_ret(i32 %a, i32 %b) {
; CHECK: define linkonce_odr i32 @"dfso$custom_cb_with_ret"(ptr %0, i32 %1, i32 %2)
; CHECK: %originreturn = alloca i32, align 4
-; CHECK-NEXT: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
-; CHECK-NEXT: [[AO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 8), align 4
+; CHECK-NEXT: [[AO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: %labelreturn = alloca i8, align 1
; CHECK-NEXT: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
@@ -272,8 +272,8 @@ define void @call_custom_cb_without_ret(i32 %a, i32 %b) {
; CHECK-NEXT: ret i32 [[R]]
; CHECK: define linkonce_odr void @"dfso$custom_cb_without_ret"(ptr %0, i32 %1, i32 %2)
-; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
-; CHECK-NEXT: [[AO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK: [[BO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 8), align 4
+; CHECK-NEXT: [[AO:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[BS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
; CHECK-NEXT: [[AS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_call.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_call.ll
index 9e8d015db12a17..f33d3047b65ef8 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_call.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_call.ll
@@ -27,7 +27,7 @@ i1 %a190, i1 %a191, i1 %a192, i1 %a193, i1 %a194, i1 %a195, i1 %a196, i1 %a197,
i1 %a200
) {
; CHECK: @arg_overflow.dfsan
- ; CHECK: [[A199:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 199), align 4
+ ; CHECK: [[A199:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 796), align 4
; CHECK: store i32 [[A199]], ptr @__dfsan_retval_origin_tls, align 4
%r = add i1 %a199, %a200
@@ -36,7 +36,7 @@ i1 %a200
define i1 @param_overflow(i1 %a) {
; CHECK: @param_overflow.dfsan
- ; CHECK: store i32 %1, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 199), align 4
+ ; CHECK: store i32 %1, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 796), align 4
; CHECK-NEXT: store i8 %2, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 398), align 2
; CHECK-NEXT: store i8 %2, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 400), align 2
; CHECK-NEXT: %r = call i1 @arg_overflow.dfsan
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
index 5d6a5b0b0af7f3..59bdbdc459d468 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
@@ -112,7 +112,7 @@ define i1 @load1(ptr %p) {
define i16 @load16(i1 %i, ptr %p) {
; COMBINE_LOAD_PTR-LABEL: define i16 @load16(
; COMBINE_LOAD_PTR-SAME: i1 [[I:%.*]], ptr [[P:%.*]]) {
-; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
; COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll
index f4f3cb5aac54ff..e49f8c99c23aa2 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_mem_intrinsic.ll
@@ -50,7 +50,7 @@ define void @memmove(ptr %d, ptr %s, i32 %l) {
define void @memset(ptr %p, i8 %v) {
; CHECK-LABEL: define void @memset(
; CHECK-SAME: ptr [[P:%.*]], i8 [[V:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK-NEXT: call void @__dfsan_set_label(i8 [[TMP2]], i32 [[TMP1]], ptr [[P]], i64 1)
; CHECK-NEXT: call void @llvm.memset.p0.i64(ptr [[P]], i8 [[V]], i64 1, i1 true)
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_other_ops.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_other_ops.ll
index f4091434992f82..b59800c7b407b3 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_other_ops.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_other_ops.ll
@@ -20,7 +20,7 @@ define float @unop(float %f) {
define i1 @binop(i1 %a, i1 %b) {
; CHECK-LABEL: define i1 @binop(
; CHECK-SAME: i1 [[A:%.*]], i1 [[B:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -53,7 +53,7 @@ define i8 @castop(ptr %p) {
define i1 @cmpop(i1 %a, i1 %b) {
; CHECK-LABEL: define i1 @cmpop(
; CHECK-SAME: i1 [[A:%.*]], i1 [[B:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -72,9 +72,9 @@ define i1 @cmpop(i1 %a, i1 %b) {
define ptr @gepop(ptr %p, i32 %a, i32 %b, i32 %c) {
; CHECK-LABEL: define ptr @gepop(
; CHECK-SAME: ptr [[P:%.*]], i32 [[A:%.*]], i32 [[B:%.*]], i32 [[C:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 3), align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
-; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 12), align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 8), align 4
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 6), align 2
; CHECK-NEXT: [[TMP6:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
@@ -101,7 +101,7 @@ define ptr @gepop(ptr %p, i32 %a, i32 %b, i32 %c) {
define i32 @eeop(<4 x i32> %a, i32 %b) {
; CHECK-LABEL: define i32 @eeop(
; CHECK-SAME: <4 x i32> [[A:%.*]], i32 [[B:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -120,8 +120,8 @@ define i32 @eeop(<4 x i32> %a, i32 %b) {
define <4 x i32> @ieop(<4 x i32> %p, i32 %a, i32 %b) {
; CHECK-LABEL: define <4 x i32> @ieop(
; CHECK-SAME: <4 x i32> [[P:%.*]], i32 [[A:%.*]], i32 [[B:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
-; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 8), align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
; CHECK-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
@@ -144,7 +144,7 @@ define <4 x i32> @ieop(<4 x i32> %p, i32 %a, i32 %b) {
define <4 x i32> @svop(<4 x i32> %a, <4 x i32> %b) {
; CHECK-LABEL: define <4 x i32> @svop(
; CHECK-SAME: <4 x i32> [[A:%.*]], <4 x i32> [[B:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -180,7 +180,7 @@ define i32 @evop({i32, float} %a) {
define {i32, {float, float}} @ivop({i32, {float, float}} %a, {float, float} %b) {
; CHECK-LABEL: define { i32, { float, float } } @ivop(
; CHECK-SAME: { i32, { float, float } } [[A:%.*]], { float, float } [[B:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[TMP3:%.*]] = load { i8, i8 }, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
; CHECK-NEXT: [[TMP4:%.*]] = load { i8, { i8, i8 } }, ptr @__dfsan_arg_tls, align 2
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_phi.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_phi.ll
index b69c383c93c1c6..bc4b3e581f6f4e 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_phi.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_phi.ll
@@ -7,7 +7,7 @@ define i32 @phiop(i32 %a, i32 %b, i1 %c) {
; CHECK-LABEL: define i32 @phiop(
; CHECK-SAME: i32 [[A:%.*]], i32 [[B:%.*]], i1 [[C:%.*]]) {
; CHECK-NEXT: [[ENTRY:.*]]:
-; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK-NEXT: [[TMP3:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
index 1eb32f4ed361ad..e67c85489636b8 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
@@ -8,8 +8,8 @@ define i8 @select8(i1 %c, i8 %t, i8 %f) {
; TRACK_CONTROL_FLOW-LABEL: define i8 @select8(
; TRACK_CONTROL_FLOW-SAME: i1 [[C:%.*]], i8 [[T:%.*]], i8 [[F:%.*]]) {
; TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
-; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
-; TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 8), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
; TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; TRACK_CONTROL_FLOW-NEXT: [[TMP6:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -25,8 +25,8 @@ define i8 @select8(i1 %c, i8 %t, i8 %f) {
;
; NO_TRACK_CONTROL_FLOW-LABEL: define i8 @select8(
; NO_TRACK_CONTROL_FLOW-SAME: i1 [[C:%.*]], i8 [[T:%.*]], i8 [[F:%.*]]) {
-; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
-; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 8), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -45,7 +45,7 @@ define i8 @select8e(i1 %c, i8 %tf) {
; TRACK_CONTROL_FLOW-LABEL: define i8 @select8e(
; TRACK_CONTROL_FLOW-SAME: i1 [[C:%.*]], i8 [[TF:%.*]]) {
; TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
-; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
; TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP3]]
@@ -58,7 +58,7 @@ define i8 @select8e(i1 %c, i8 %tf) {
;
; NO_TRACK_CONTROL_FLOW-LABEL: define i8 @select8e(
; NO_TRACK_CONTROL_FLOW-SAME: i1 [[C:%.*]], i8 [[TF:%.*]]) {
-; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
; NO_TRACK_CONTROL_FLOW-NEXT: [[A:%.*]] = select i1 [[C]], i8 [[TF]], i8 [[TF]]
@@ -74,8 +74,8 @@ define <4 x i8> @select8v(<4 x i1> %c, <4 x i8> %t, <4 x i8> %f) {
; TRACK_CONTROL_FLOW-LABEL: define <4 x i8> @select8v(
; TRACK_CONTROL_FLOW-SAME: <4 x i1> [[C:%.*]], <4 x i8> [[T:%.*]], <4 x i8> [[F:%.*]]) {
; TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
-; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
-; TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 8), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
; TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; TRACK_CONTROL_FLOW-NEXT: [[TMP6:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
@@ -92,8 +92,8 @@ define <4 x i8> @select8v(<4 x i1> %c, <4 x i8> %t, <4 x i8> %f) {
;
; NO_TRACK_CONTROL_FLOW-LABEL: define <4 x i8> @select8v(
; NO_TRACK_CONTROL_FLOW-SAME: <4 x i1> [[C:%.*]], <4 x i8> [[T:%.*]], <4 x i8> [[F:%.*]]) {
-; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
-; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 8), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
index 8f54408b5e8317..dbe6ed83b6405c 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
@@ -93,7 +93,7 @@ define void @store_nonzero_to_escaped_alloca(i16 %a) {
define void @store64_align8(ptr %p, i64 %a) {
; NO_COMBINE_STORE_PTR-LABEL: define void @store64_align8(
; NO_COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i64 [[A:%.*]]) {
-; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; NO_COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; NO_COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
; NO_COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
@@ -127,7 +127,7 @@ define void @store64_align8(ptr %p, i64 %a) {
; COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i64 [[A:%.*]]) {
; COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
-; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP2]]
; COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP2]], 0
@@ -167,7 +167,7 @@ define void @store64_align8(ptr %p, i64 %a) {
define void @store64_align2(ptr %p, i64 %a) {
; NO_COMBINE_STORE_PTR-LABEL: define void @store64_align2(
; NO_COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i64 [[A:%.*]]) {
-; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; NO_COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; NO_COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
; NO_COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
@@ -201,7 +201,7 @@ define void @store64_align2(ptr %p, i64 %a) {
; COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i64 [[A:%.*]]) {
; COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
-; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP2]]
; COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP2]], 0
@@ -241,7 +241,7 @@ define void @store64_align2(ptr %p, i64 %a) {
define void @store96_align8(ptr %p, i96 %a) {
; NO_COMBINE_STORE_PTR-LABEL: define void @store96_align8(
; NO_COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i96 [[A:%.*]]) {
-; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; NO_COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; NO_COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
; NO_COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
@@ -285,7 +285,7 @@ define void @store96_align8(ptr %p, i96 %a) {
; COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i96 [[A:%.*]]) {
; COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
; COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
-; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP2]]
; COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP2]], 0
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store_threshold.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store_threshold.ll
index 8b526f1044b2a7..8021a2fb68064d 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store_threshold.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store_threshold.ll
@@ -6,7 +6,7 @@ target triple = "x86_64-unknown-linux-gnu"
define void @store_threshold(ptr %p, [2 x i64] %a) {
; CHECK-LABEL: define void @store_threshold(
; CHECK-SAME: ptr [[P:%.*]], [2 x i64] [[A:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @__dfsan_arg_origin_tls, i64 4), align 4
; CHECK-NEXT: [[TMP2:%.*]] = load [2 x i8], ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
; CHECK-NEXT: [[TMP3:%.*]] = extractvalue [2 x i8] [[TMP2]], 0
; CHECK-NEXT: [[TMP4:%.*]] = extractvalue [2 x i8] [[TMP2]], 1
diff --git a/llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll b/llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll
index 67865f666832e2..eb503e35271cc4 100644
--- a/llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/amdgpu-contiguous-counters.ll
@@ -29,4 +29,4 @@ declare void @llvm.instrprof.increment(ptr, i64, i32, i32)
;; Second counter slot uses a GEP into the per-kernel counter array and the
;; matching uniform-counter array.
-; CHECK: call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ([2 x i64], ptr addrspace(1) @__profc_kernel1, i32 0, i32 1) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds ([2 x i64], ptr addrspace(1) @__llvm_prf_unifcnt_kernel1, i32 0, i32 1) to ptr), i64 1)
+; CHECK: call void @__llvm_profile_instrument_gpu(ptr addrspacecast (ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @__profc_kernel1, i64 8) to ptr), ptr addrspacecast (ptr addrspace(1) getelementptr inbounds (i8, ptr addrspace(1) @__llvm_prf_unifcnt_kernel1, i64 8) to ptr), i64 1)
diff --git a/llvm/test/Instrumentation/InstrProfiling/conditional-counter-updates.ll b/llvm/test/Instrumentation/InstrProfiling/conditional-counter-updates.ll
index d9d702d7482802..a6bceb008b26fc 100644
--- a/llvm/test/Instrumentation/InstrProfiling/conditional-counter-updates.ll
+++ b/llvm/test/Instrumentation/InstrProfiling/conditional-counter-updates.ll
@@ -39,21 +39,21 @@ define i32 @bar(i32 %cond) #0 {
; CHECK-NEXT: [[CMP:%.*]] = icmp slt i32 [[TMP2]], 0
; CHECK-NEXT: br i1 [[CMP]], label %[[IF_THEN:.*]], label %[[IF_END:.*]]
; CHECK: [[IF_THEN]]:
-; CHECK-NEXT: [[PGOCOUNT1:%.*]] = load i8, ptr getelementptr inbounds ([3 x i8], ptr @__profc_bar, i32 0, i32 1), align 1
+; CHECK-NEXT: [[PGOCOUNT1:%.*]] = load i8, ptr getelementptr inbounds (i8, ptr @__profc_bar, i64 1), align 1
; CHECK-NEXT: [[PGOCOUNT_IFNONZERO2:%.*]] = icmp ne i8 [[PGOCOUNT1]], 0
; CHECK-NEXT: br i1 [[PGOCOUNT_IFNONZERO2]], label %[[BB3:.*]], label %[[BB4:.*]]
; CHECK: [[BB3]]:
-; CHECK-NEXT: store i8 0, ptr getelementptr inbounds ([3 x i8], ptr @__profc_bar, i32 0, i32 1), align 1
+; CHECK-NEXT: store i8 0, ptr getelementptr inbounds (i8, ptr @__profc_bar, i64 1), align 1
; CHECK-NEXT: br label %[[BB4]]
; CHECK: [[BB4]]:
; CHECK-NEXT: store i32 -1, ptr [[RETVAL]], align 4
; CHECK-NEXT: br label %[[RETURN:.*]]
; CHECK: [[IF_END]]:
-; CHECK-NEXT: [[PGOCOUNT3:%.*]] = load i8, ptr getelementptr inbounds ([3 x i8], ptr @__profc_bar, i32 0, i32 2), align 1
+; CHECK-NEXT: [[PGOCOUNT3:%.*]] = load i8, ptr getelementptr inbounds (i8, ptr @__profc_bar, i64 2), align 1
; CHECK-NEXT: [[PGOCOUNT_IFNONZERO4:%.*]] = icmp ne i8 [[PGOCOUNT3]], 0
; CHECK-NEXT: br i1 [[PGOCOUNT_IFNONZERO4]], label %[[BB5:.*]], label %[[BB6:.*]]
; CHECK: [[BB5]]:
-; CHECK-NEXT: store i8 0, ptr getelementptr inbounds ([3 x i8], ptr @__profc_bar, i32 0, i32 2), align 1
+; CHECK-NEXT: store i8 0, ptr getelementptr inbounds (i8, ptr @__profc_bar, i64 2), align 1
; CHECK-NEXT: br label %[[BB6]]
; CHECK: [[BB6]]:
; CHECK-NEXT: store i32 0, ptr [[RETVAL]], align 4
diff --git a/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll b/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll
index 66c477609c234e..1c70ead8af3647 100644
--- a/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll
+++ b/llvm/test/Instrumentation/NumericalStabilitySanitizer/basic.ll
@@ -481,8 +481,8 @@ define void @call_fn_taking_float() sanitize_numerical_stability {
; DQQ-NEXT: entry:
; DQQ-NEXT: store ptr @takes_floats, ptr @__nsan_shadow_args_tag, align 8
; DQQ-NEXT: store double 1.000000e+00, ptr @__nsan_shadow_args_ptr, align 1
-; DQQ-NEXT: store fp128 3.000000e+00, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 8), align 1
-; DQQ-NEXT: store fp128 f0x3FC9CD2B297D889BC000000000000000, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 24), align 1
+; DQQ-NEXT: store fp128 3.000000e+00, ptr getelementptr (i8, ptr @__nsan_shadow_args_ptr, i64 8), align 1
+; DQQ-NEXT: store fp128 f0x3FC9CD2B297D889BC000000000000000, ptr getelementptr (i8, ptr @__nsan_shadow_args_ptr, i64 24), align 1
; DQQ-NEXT: call void @takes_floats(float 1.000000e+00, i8 2, double 3.000000e+00, x86_fp80 f0x3FC9E69594BEC44DE000)
; DQQ-NEXT: ret void
;
@@ -490,8 +490,8 @@ define void @call_fn_taking_float() sanitize_numerical_stability {
; DLQ-NEXT: entry:
; DLQ-NEXT: store ptr @takes_floats, ptr @__nsan_shadow_args_tag, align 8
; DLQ-NEXT: store double 1.000000e+00, ptr @__nsan_shadow_args_ptr, align 1
-; DLQ-NEXT: store x86_fp80 3.000000e+00, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 8), align 1
-; DLQ-NEXT: store fp128 f0x3FC9CD2B297D889BC000000000000000, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 18), align 1
+; DLQ-NEXT: store x86_fp80 3.000000e+00, ptr getelementptr (i8, ptr @__nsan_shadow_args_ptr, i64 8), align 1
+; DLQ-NEXT: store fp128 f0x3FC9CD2B297D889BC000000000000000, ptr getelementptr (i8, ptr @__nsan_shadow_args_ptr, i64 18), align 1
; DLQ-NEXT: call void @takes_floats(float 1.000000e+00, i8 2, double 3.000000e+00, x86_fp80 f0x3FC9E69594BEC44DE000)
; DLQ-NEXT: ret void
;
@@ -673,7 +673,7 @@ define void @freeze_vector_insert(<2 x float> %vec, i32 %idx, float %scalar) san
; CHECK-NEXT: [[TMP2:%.*]] = load <2 x double>, ptr @__nsan_shadow_args_ptr, align 1
; CHECK-NEXT: [[TMP3:%.*]] = fpext <2 x float> [[VEC:%.*]] to <2 x double>
; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], <2 x double> [[TMP2]], <2 x double> [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = load double, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 16), align 1
+; CHECK-NEXT: [[TMP5:%.*]] = load double, ptr getelementptr (i8, ptr @__nsan_shadow_args_ptr, i64 16), align 1
; CHECK-NEXT: [[TMP6:%.*]] = fpext float [[SCALAR:%.*]] to double
; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP1]], double [[TMP5]], double [[TMP6]]
; CHECK-NEXT: store i64 0, ptr @__nsan_shadow_args_tag, align 8
@@ -762,7 +762,7 @@ define float @sub_fabs(float %a, float %b) sanitize_numerical_stability {
; CHECK-NEXT: [[TMP2:%.*]] = load double, ptr @__nsan_shadow_args_ptr, align 1
; CHECK-NEXT: [[TMP3:%.*]] = fpext float [[A:%.*]] to double
; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP1]], double [[TMP2]], double [[TMP3]]
-; CHECK-NEXT: [[TMP5:%.*]] = load double, ptr getelementptr ([16384 x i8], ptr @__nsan_shadow_args_ptr, i64 0, i64 8), align 1
+; CHECK-NEXT: [[TMP5:%.*]] = load double, ptr getelementptr (i8, ptr @__nsan_shadow_args_ptr, i64 8), align 1
; CHECK-NEXT: [[TMP6:%.*]] = fpext float [[B:%.*]] to double
; CHECK-NEXT: [[TMP7:%.*]] = select i1 [[TMP1]], double [[TMP5]], double [[TMP6]]
; CHECK-NEXT: store i64 0, ptr @__nsan_shadow_args_tag, align 8
diff --git a/llvm/test/Instrumentation/SanitizerCoverage/missing_dbg.ll b/llvm/test/Instrumentation/SanitizerCoverage/missing_dbg.ll
index a253fef64f00d8..059136e9b6b125 100644
--- a/llvm/test/Instrumentation/SanitizerCoverage/missing_dbg.ll
+++ b/llvm/test/Instrumentation/SanitizerCoverage/missing_dbg.ll
@@ -12,7 +12,7 @@ define i32 @with_dbg(ptr %a, ptr %b) !dbg !3 {
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 42
; CHECK-NEXT: br i1 [[CMP]], label %[[BB0:.*]], label %[[BB1:.*]]
; CHECK: [[BB0]]:
-; CHECK-NEXT: call void @__sanitizer_cov_trace_pc_guard(ptr getelementptr inbounds ([2 x i32], ptr @__sancov_gen_, i64 0, i64 1)) #[[ATTR1]], !dbg [[DBG7:![0-9]+]]
+; CHECK-NEXT: call void @__sanitizer_cov_trace_pc_guard(ptr getelementptr inbounds (i8, ptr @__sancov_gen_, i64 4)) #[[ATTR1]], !dbg [[DBG7:![0-9]+]]
; CHECK-NEXT: store i32 [[TMP1]], ptr [[B]], align 4
; CHECK-NEXT: br label %[[BB1]]
; CHECK: [[BB1]]:
@@ -38,7 +38,7 @@ define i32 @without_dbg(ptr %a, ptr %b) {
; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[TMP1]], 42
; CHECK-NEXT: br i1 [[CMP]], label %[[BB0:.*]], label %[[BB1:.*]]
; CHECK: [[BB0]]:
-; CHECK-NEXT: call void @__sanitizer_cov_trace_pc_guard(ptr getelementptr inbounds ([2 x i32], ptr @__sancov_gen_.1, i64 0, i64 1)) #[[ATTR1]]
+; CHECK-NEXT: call void @__sanitizer_cov_trace_pc_guard(ptr getelementptr inbounds (i8, ptr @__sancov_gen_.1, i64 4)) #[[ATTR1]]
; CHECK-NEXT: store i32 [[TMP1]], ptr [[B]], align 4
; CHECK-NEXT: br label %[[BB1]]
; CHECK: [[BB1]]:
diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll
index 0c48d0c47dc74a..2073e5eb2f4029 100644
--- a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt-inseltpoison.ll
@@ -73,7 +73,7 @@ define <vscale x 4 x i32> @test_global_array(<vscale x 4 x i64> %indxs, <vscale
define <vscale x 4 x i32> @global_struct_splat(<vscale x 4 x i1> %mask) #0 {
; CHECK-LABEL: @global_struct_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 shufflevector (<vscale x 4 x ptr> insertelement (<vscale x 4 x ptr> poison, ptr getelementptr ([[STRUCT_A:%.*]], ptr @c, i64 0, i32 1), i64 0), <vscale x 4 x ptr> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 shufflevector (<vscale x 4 x ptr> insertelement (<vscale x 4 x ptr> poison, ptr getelementptr (i8, ptr @c, i64 4), i64 0), <vscale x 4 x ptr> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
;
%1 = insertelement <vscale x 4 x ptr> poison, ptr @c, i32 0
diff --git a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll
index c82a5411b83e4e..8487f6c56ec9c7 100644
--- a/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/AArch64/gather-scatter-opt.ll
@@ -73,7 +73,7 @@ define <vscale x 4 x i32> @test_global_array(<vscale x 4 x i64> %indxs, <vscale
define <vscale x 4 x i32> @global_struct_splat(<vscale x 4 x i1> %mask) #0 {
; CHECK-LABEL: @global_struct_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 shufflevector (<vscale x 4 x ptr> insertelement (<vscale x 4 x ptr> poison, ptr getelementptr ([[STRUCT_A:%.*]], ptr @c, i64 0, i32 1), i64 0), <vscale x 4 x ptr> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
+; CHECK-NEXT: [[TMP1:%.*]] = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0(<vscale x 4 x ptr> align 4 shufflevector (<vscale x 4 x ptr> insertelement (<vscale x 4 x ptr> poison, ptr getelementptr (i8, ptr @c, i64 4), i64 0), <vscale x 4 x ptr> poison, <vscale x 4 x i32> zeroinitializer), <vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x i32> undef)
; CHECK-NEXT: ret <vscale x 4 x i32> [[TMP1]]
;
%1 = insertelement <vscale x 4 x ptr> undef, ptr @c, i32 0
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
index 136f6aa451fdeb..ab6eca39d1efda 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt-inseltpoison.ll
@@ -76,7 +76,7 @@ define <4 x i32> @test_global_array(<4 x i64> %indxs) {
define <4 x i32> @global_struct_splat() {
; CHECK-LABEL: @global_struct_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> align 4 <ptr getelementptr ([[STRUCT_A:%.*]], ptr @c, i64 0, i32 1), ptr getelementptr ([[STRUCT_A]], ptr @c, i64 0, i32 1), ptr getelementptr ([[STRUCT_A]], ptr @c, i64 0, i32 1), ptr getelementptr ([[STRUCT_A]], ptr @c, i64 0, i32 1)>, <4 x i1> splat (i1 true), <4 x i32> undef)
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> align 4 <ptr getelementptr (i8, ptr @c, i64 4), ptr getelementptr (i8, ptr @c, i64 4), ptr getelementptr (i8, ptr @c, i64 4), ptr getelementptr (i8, ptr @c, i64 4)>, <4 x i1> splat (i1 true), <4 x i32> undef)
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
;
%1 = insertelement <4 x ptr> poison, ptr @c, i32 0
diff --git a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll
index 22a007df1ca96e..8140c483d7a69e 100644
--- a/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll
+++ b/llvm/test/Transforms/CodeGenPrepare/X86/gather-scatter-opt.ll
@@ -75,7 +75,7 @@ define <4 x i32> @test_global_array(<4 x i64> %indxs) {
define <4 x i32> @global_struct_splat() {
; CHECK-LABEL: @global_struct_splat(
-; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> align 4 <ptr getelementptr ([[STRUCT_A:%.*]], ptr @c, i64 0, i32 1), ptr getelementptr ([[STRUCT_A]], ptr @c, i64 0, i32 1), ptr getelementptr ([[STRUCT_A]], ptr @c, i64 0, i32 1), ptr getelementptr ([[STRUCT_A]], ptr @c, i64 0, i32 1)>, <4 x i1> splat (i1 true), <4 x i32> undef)
+; CHECK-NEXT: [[TMP1:%.*]] = call <4 x i32> @llvm.masked.gather.v4i32.v4p0(<4 x ptr> align 4 <ptr getelementptr (i8, ptr @c, i64 4), ptr getelementptr (i8, ptr @c, i64 4), ptr getelementptr (i8, ptr @c, i64 4), ptr getelementptr (i8, ptr @c, i64 4)>, <4 x i1> splat (i1 true), <4 x i32> undef)
; CHECK-NEXT: ret <4 x i32> [[TMP1]]
;
%1 = insertelement <4 x ptr> undef, ptr @c, i32 0
diff --git a/llvm/test/Transforms/LowerIFunc/ifunc-alias.ll b/llvm/test/Transforms/LowerIFunc/ifunc-alias.ll
index 64c6ab838d1e2b..2d1f88d96d0514 100644
--- a/llvm/test/Transforms/LowerIFunc/ifunc-alias.ll
+++ b/llvm/test/Transforms/LowerIFunc/ifunc-alias.ll
@@ -37,7 +37,7 @@ define float @call_alias_of_ifunc(i64 %arg) {
;
; CHECK-LABEL: define float @call_ifunc_aliasee(
; CHECK-SAME: i64 [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds ([3 x ptr], ptr @[[GLOB0]], i32 0, i32 1), align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 8), align 8
; CHECK-NEXT: [[CALL:%.*]] = call float [[TMP1]](i64 [[ARG]])
; CHECK-NEXT: ret float [[CALL]]
;
@@ -52,8 +52,8 @@ define float @call_alias_of_ifunc(i64 %arg) {
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @resolver()
; CHECK-NEXT: store ptr [[TMP1]], ptr @[[GLOB0]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = call ptr @resolver()
-; CHECK-NEXT: store ptr [[TMP2]], ptr getelementptr inbounds ([3 x ptr], ptr @[[GLOB0]], i32 0, i32 1), align 8
+; CHECK-NEXT: store ptr [[TMP2]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 8), align 8
; CHECK-NEXT: [[TMP3:%.*]] = call ptr @resolver()
-; CHECK-NEXT: store ptr [[TMP3]], ptr getelementptr inbounds ([3 x ptr], ptr @[[GLOB0]], i32 0, i32 2), align 8
+; CHECK-NEXT: store ptr [[TMP3]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 16), align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LowerIFunc/ifunc-program-addrspace.ll b/llvm/test/Transforms/LowerIFunc/ifunc-program-addrspace.ll
index 79e4b625942cdb..29ff2991415d12 100644
--- a/llvm/test/Transforms/LowerIFunc/ifunc-program-addrspace.ll
+++ b/llvm/test/Transforms/LowerIFunc/ifunc-program-addrspace.ll
@@ -66,12 +66,12 @@ define void @load_ifuncs() addrspace(0) {
;
;
; CHECK-LABEL: define void @call_ifuncs() addrspace(0) {
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr addrspace(1), ptr getelementptr inbounds ([6 x ptr addrspace(1)], ptr @[[GLOB0]], i32 0, i32 3), align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr addrspace(1), ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 24), align 8
; CHECK-NEXT: [[TMP2:%.*]] = addrspacecast ptr addrspace(1) [[TMP1]] to ptr
; CHECK-NEXT: call addrspace(0) void [[TMP2]]()
-; CHECK-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr getelementptr inbounds ([6 x ptr addrspace(1)], ptr @[[GLOB0]], i32 0, i32 4), align 8
+; CHECK-NEXT: [[TMP3:%.*]] = load ptr addrspace(1), ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 32), align 8
; CHECK-NEXT: call addrspace(1) void [[TMP3]]()
-; CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(1), ptr getelementptr inbounds ([6 x ptr addrspace(1)], ptr @[[GLOB0]], i32 0, i32 5), align 8
+; CHECK-NEXT: [[TMP4:%.*]] = load ptr addrspace(1), ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 40), align 8
; CHECK-NEXT: call addrspace(1) void [[TMP4]]()
; CHECK-NEXT: ret void
;
@@ -87,15 +87,15 @@ define void @load_ifuncs() addrspace(0) {
; CHECK-NEXT: [[TMP1:%.*]] = call addrspace(1) ptr addrspace(1) @resolver1_in_1()
; CHECK-NEXT: store ptr addrspace(1) [[TMP1]], ptr @[[GLOB0]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = call addrspace(0) ptr addrspace(1) @resolver1_in_0()
-; CHECK-NEXT: store ptr addrspace(1) [[TMP2]], ptr getelementptr inbounds ([6 x ptr addrspace(1)], ptr @[[GLOB0]], i32 0, i32 1), align 8
+; CHECK-NEXT: store ptr addrspace(1) [[TMP2]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 8), align 8
; CHECK-NEXT: [[TMP3:%.*]] = call addrspace(1) ptr @resolver0_in_1()
; CHECK-NEXT: [[TMP4:%.*]] = addrspacecast ptr [[TMP3]] to ptr addrspace(1)
-; CHECK-NEXT: store ptr addrspace(1) [[TMP4]], ptr getelementptr inbounds ([6 x ptr addrspace(1)], ptr @[[GLOB0]], i32 0, i32 2), align 8
+; CHECK-NEXT: store ptr addrspace(1) [[TMP4]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 16), align 8
; CHECK-NEXT: [[TMP5:%.*]] = call addrspace(0) ptr addrspace(1) @resolver1_in_0()
-; CHECK-NEXT: store ptr addrspace(1) [[TMP5]], ptr getelementptr inbounds ([6 x ptr addrspace(1)], ptr @[[GLOB0]], i32 0, i32 3), align 8
+; CHECK-NEXT: store ptr addrspace(1) [[TMP5]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 24), align 8
; CHECK-NEXT: [[TMP6:%.*]] = call addrspace(1) ptr addrspace(1) @resolver1_in_1()
-; CHECK-NEXT: store ptr addrspace(1) [[TMP6]], ptr getelementptr inbounds ([6 x ptr addrspace(1)], ptr @[[GLOB0]], i32 0, i32 4), align 8
+; CHECK-NEXT: store ptr addrspace(1) [[TMP6]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 32), align 8
; CHECK-NEXT: [[TMP7:%.*]] = call addrspace(0) ptr addrspace(1) @resolver1_in_0()
-; CHECK-NEXT: store ptr addrspace(1) [[TMP7]], ptr getelementptr inbounds ([6 x ptr addrspace(1)], ptr @[[GLOB0]], i32 0, i32 5), align 8
+; CHECK-NEXT: store ptr addrspace(1) [[TMP7]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 40), align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LowerIFunc/lower-ifunc.ll b/llvm/test/Transforms/LowerIFunc/lower-ifunc.ll
index 26fb18ae86534d..29713795a09e37 100644
--- a/llvm/test/Transforms/LowerIFunc/lower-ifunc.ll
+++ b/llvm/test/Transforms/LowerIFunc/lower-ifunc.ll
@@ -121,38 +121,38 @@ define i32 @call_used_in_initializer(double %arg) {
; CHECK-SAME: ptr [[PTR:%.*]]) {
; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr @[[GLOB0]], align 8
; CHECK-NEXT: call void [[TMP1]]()
-; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 1), align 8
+; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 8), align 8
; CHECK-NEXT: call void [[TMP2]]()
; CHECK-NEXT: ret void
;
;
; CHECK-LABEL: define void @store_ifunc_2(
; CHECK-SAME: ptr [[PTR:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 1), align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 8), align 8
; CHECK-NEXT: store ptr [[TMP1]], ptr [[PTR]], align 8
-; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 1), align 8
+; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 8), align 8
; CHECK-NEXT: store ptr [[PTR]], ptr [[TMP2]], align 8
; CHECK-NEXT: ret void
;
;
; CHECK-LABEL: define void @call_ifunc_is_argument(
; CHECK-SAME: ptr [[PTR:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 1), align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 8), align 8
; CHECK-NEXT: call void @other_func(ptr [[TMP1]])
; CHECK-NEXT: ret void
;
;
; CHECK-LABEL: define void @call_ifunc_both_call_argument(
; CHECK-SAME: ptr [[PTR:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 4), align 8
-; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 4), align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 32), align 8
+; CHECK-NEXT: [[TMP2:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 32), align 8
; CHECK-NEXT: call void [[TMP1]](ptr [[TMP1]])
; CHECK-NEXT: ret void
;
;
; CHECK-LABEL: define i32 @call_ifunc_nonvoid(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 5), align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 40), align 8
; CHECK-NEXT: [[RET:%.*]] = call i32 [[TMP1]](double [[ARG]])
; CHECK-NEXT: ret i32 [[RET]]
;
@@ -160,7 +160,7 @@ define i32 @call_used_in_initializer(double %arg) {
; CHECK-LABEL: define float @call_different_type_ifunc_nonvoid(
; CHECK-SAME: double [[ARG:%.*]]) {
; CHECK-NEXT: [[CAST_ARG:%.*]] = bitcast double [[ARG]] to i64
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 5), align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 40), align 8
; CHECK-NEXT: [[RET:%.*]] = call float [[TMP1]](i64 [[CAST_ARG]])
; CHECK-NEXT: ret float [[RET]]
;
@@ -173,7 +173,7 @@ define i32 @call_used_in_initializer(double %arg) {
;
; CHECK-LABEL: define i32 @call_used_in_initializer(
; CHECK-SAME: double [[ARG:%.*]]) {
-; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 7), align 8
+; CHECK-NEXT: [[TMP1:%.*]] = load ptr, ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 56), align 8
; CHECK-NEXT: [[RET:%.*]] = call i32 [[TMP1]](double [[ARG]])
; CHECK-NEXT: ret i32 [[RET]]
;
@@ -182,18 +182,18 @@ define i32 @call_used_in_initializer(double %arg) {
; CHECK-NEXT: [[TMP1:%.*]] = call ptr @resolver1()
; CHECK-NEXT: store ptr [[TMP1]], ptr @[[GLOB0]], align 8
; CHECK-NEXT: [[TMP2:%.*]] = call ptr @resolver1()
-; CHECK-NEXT: store ptr [[TMP2]], ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 1), align 8
+; CHECK-NEXT: store ptr [[TMP2]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 8), align 8
; CHECK-NEXT: [[TMP3:%.*]] = call ptr @resolver2()
-; CHECK-NEXT: store ptr [[TMP3]], ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 2), align 8
+; CHECK-NEXT: store ptr [[TMP3]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 16), align 8
; CHECK-NEXT: [[TMP4:%.*]] = call ptr @resolver3()
-; CHECK-NEXT: store ptr [[TMP4]], ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 3), align 8
+; CHECK-NEXT: store ptr [[TMP4]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 24), align 8
; CHECK-NEXT: [[TMP5:%.*]] = call ptr @resolver4()
-; CHECK-NEXT: store ptr [[TMP5]], ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 4), align 8
+; CHECK-NEXT: store ptr [[TMP5]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 32), align 8
; CHECK-NEXT: [[TMP6:%.*]] = call ptr @resolver5()
-; CHECK-NEXT: store ptr [[TMP6]], ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 5), align 8
+; CHECK-NEXT: store ptr [[TMP6]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 40), align 8
; CHECK-NEXT: [[TMP7:%.*]] = call ptr @resolver5()
-; CHECK-NEXT: store ptr [[TMP7]], ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 6), align 8
+; CHECK-NEXT: store ptr [[TMP7]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 48), align 8
; CHECK-NEXT: [[TMP8:%.*]] = call ptr @resolver5()
-; CHECK-NEXT: store ptr [[TMP8]], ptr getelementptr inbounds ([8 x ptr], ptr @[[GLOB0]], i32 0, i32 7), align 8
+; CHECK-NEXT: store ptr [[TMP8]], ptr getelementptr inbounds (i8, ptr @[[GLOB0]], i64 56), align 8
; CHECK-NEXT: ret void
;
diff --git a/llvm/test/Transforms/LowerMatrixIntrinsics/const-gep.ll b/llvm/test/Transforms/LowerMatrixIntrinsics/const-gep.ll
index 81a9eeef7e11e0..191134eefe79c7 100644
--- a/llvm/test/Transforms/LowerMatrixIntrinsics/const-gep.ll
+++ b/llvm/test/Transforms/LowerMatrixIntrinsics/const-gep.ll
@@ -14,7 +14,7 @@ define void @test(i32 %r, i32 %c) {
; CHECK-NEXT: store i32 [[R:%.*]], ptr [[R_ADDR]], align 4
; CHECK-NEXT: store i32 [[C:%.*]], ptr [[C_ADDR]], align 4
; CHECK-NEXT: [[COL_LOAD:%.*]] = load <2 x double>, ptr @foo, align 8
-; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr getelementptr inbounds (double, ptr @foo, i64 2), align 8
+; CHECK-NEXT: [[COL_LOAD1:%.*]] = load <2 x double>, ptr getelementptr inbounds (i8, ptr @foo, i64 16), align 8
; CHECK-NEXT: [[BLOCK:%.*]] = shufflevector <2 x double> [[COL_LOAD]], <2 x double> poison, <1 x i32> zeroinitializer
; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x double> [[COL_LOAD]], i64 0
; CHECK-NEXT: [[SPLAT_SPLATINSERT:%.*]] = insertelement <1 x double> poison, double [[TMP0]], i64 0
@@ -68,7 +68,7 @@ define void @test(i32 %r, i32 %c) {
; CHECK-NEXT: [[TMP26:%.*]] = shufflevector <1 x double> [[TMP25]], <1 x double> poison, <2 x i32> <i32 0, i32 poison>
; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <2 x double> [[TMP20]], <2 x double> [[TMP26]], <2 x i32> <i32 0, i32 2>
; CHECK-NEXT: store <2 x double> [[COL_LOAD]], ptr getelementptr inbounds ([5 x <4 x double>], ptr @foo, i64 0, i64 2), align 8
-; CHECK-NEXT: store <2 x double> [[COL_LOAD1]], ptr getelementptr inbounds (double, ptr getelementptr inbounds ([5 x <4 x double>], ptr @foo, i64 0, i64 2), i64 2), align 8
+; CHECK-NEXT: store <2 x double> [[COL_LOAD1]], ptr getelementptr inbounds (i8, ptr getelementptr inbounds ([5 x <4 x double>], ptr @foo, i64 0, i64 2), i64 16), align 8
; CHECK-NEXT: ret void
;
entry:
diff --git a/llvm/test/Transforms/PGOProfile/counter_promo.ll b/llvm/test/Transforms/PGOProfile/counter_promo.ll
index 16ff170c107c61..03b57f6129c67e 100644
--- a/llvm/test/Transforms/PGOProfile/counter_promo.ll
+++ b/llvm/test/Transforms/PGOProfile/counter_promo.ll
@@ -3,9 +3,9 @@
define void @foo(i32 %n, i32 %N) {
; PROMO-LABEL: @foo
-; PROMO: {{.*}} = load {{.*}} @__profc_foo{{.*}} 3)
+; PROMO: {{.*}} = load {{.*}} @__profc_foo{{.*}} 24)
; PROMO-NEXT: add
-; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}3)
+; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}} 24)
bb:
%tmp = add nsw i32 %n, 1
%tmp1 = add nsw i32 %n, -1
@@ -49,15 +49,15 @@ bb12: ; preds = %bb9
; NONATOMIC_PROMO: %[[PROMO1:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}}
; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO1]], %[[LIVEOUT1]]
; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}
-; NONATOMIC_PROMO-NEXT: %[[PROMO2:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 1)
+; NONATOMIC_PROMO-NEXT: %[[PROMO2:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 8)
; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO2]], %[[LIVEOUT2]]
-; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}1)
-; NONATOMIC_PROMO-NEXT: %[[PROMO3:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 2)
+; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}} 8)
+; NONATOMIC_PROMO-NEXT: %[[PROMO3:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 16)
; NONATOMIC_PROMO-NEXT: add {{.*}} %[[PROMO3]], %[[LIVEOUT3]]
-; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}2)
+; NONATOMIC_PROMO-NEXT: store {{.*}}@__profc_foo{{.*}} 16)
; ATOMIC_PROMO: atomicrmw add {{.*}} @__profc_foo{{.*}}, i64 %[[LIVEOUT1]] monotonic
-; ATOMIC_PROMO-NEXT: atomicrmw add {{.*}} @__profc_foo{{.*}}1), i64 %[[LIVEOUT2]] monotonic
-; ATOMIC_PROMO-NEXT: atomicrmw add {{.*}} @__profc_foo{{.*}}2), i64 %[[LIVEOUT3]] monotonic
+; ATOMIC_PROMO-NEXT: atomicrmw add {{.*}} @__profc_foo{{.*}} 8), i64 %[[LIVEOUT2]] monotonic
+; ATOMIC_PROMO-NEXT: atomicrmw add {{.*}} @__profc_foo{{.*}} 16), i64 %[[LIVEOUT3]] monotonic
; PROMO-NOT: @__profc_foo{{.*}})
diff --git a/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll b/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll
index d279f342666a78..9e1dee962d2aa3 100644
--- a/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll
+++ b/llvm/test/Transforms/PGOProfile/counter_promo_exit_catchswitch.ll
@@ -37,10 +37,10 @@ for.cond: ; preds = %for.inc, %entry
for.body: ; preds = %for.cond
; CHECK: for.body:
; NOTENTRY: %pgocount1 = load i64, ptr @"__profc_?run@@YAXH at Z"
-; TENTRY: %pgocount1 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 1)
+; TENTRY: %pgocount1 = load i64, ptr getelementptr inbounds (i8, ptr @"__profc_?run@@YAXH at Z", i64 8)
; CHECK: %1 = add i64 %pgocount1, 1
; NOTENTRY: store i64 %1, ptr @"__profc_?run@@YAXH at Z"
-; ENTRY: store i64 %1, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 1)
+; ENTRY: store i64 %1, ptr getelementptr inbounds (i8, ptr @"__profc_?run@@YAXH at Z", i64 8)
%idxprom = zext i32 %i.0 to i64
%arrayidx = getelementptr inbounds [200 x i8], ptr @"?buffer@@3PADA", i64 0, i64 %idxprom
%0 = load i8, ptr %arrayidx, align 1
@@ -53,11 +53,11 @@ if.end: ; preds = %for.body
for.inc: ; preds = %if.end
; CHECK: for.inc:
-; NOTENTRY: %pgocount2 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 1)
-; ENTRY: %pgocount2 = load i64, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 2)
+; NOTENTRY: %pgocount2 = load i64, ptr getelementptr inbounds (i8, ptr @"__profc_?run@@YAXH at Z", i64 8)
+; ENTRY: %pgocount2 = load i64, ptr getelementptr inbounds (i8, ptr @"__profc_?run@@YAXH at Z", i64 16)
; CHECK: %3 = add i64 %pgocount2, 1
-; NOTENTRY: store i64 %3, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 1)
-; ENTRY: store i64 %3, ptr getelementptr inbounds ([3 x i64], ptr @"__profc_?run@@YAXH at Z", i32 0, i32 2)
+; NOTENTRY: store i64 %3, ptr getelementptr inbounds (i8, ptr @"__profc_?run@@YAXH at Z", i64 8)
+; ENTRY: store i64 %3, ptr getelementptr inbounds (i8, ptr @"__profc_?run@@YAXH at Z", i64 16)
%inc = add nuw nsw i32 %i.0, 1
br label %for.cond
diff --git a/llvm/test/Transforms/PGOProfile/counter_promo_exit_merge.ll b/llvm/test/Transforms/PGOProfile/counter_promo_exit_merge.ll
index c2af706df787e1..631f0a8551dcdb 100644
--- a/llvm/test/Transforms/PGOProfile/counter_promo_exit_merge.ll
+++ b/llvm/test/Transforms/PGOProfile/counter_promo_exit_merge.ll
@@ -49,15 +49,15 @@ bb14: ; preds = %bb4.bb14_crit_edge,
; PROMO: %[[MERGE1:[a-z0-9]+]] = phi {{.*}}
; PROMO-NEXT: %[[MERGE2:[a-z0-9.]+]] = phi {{.*}}
; PROMO-NEXT: %[[MERGE3:[a-z0-9.]+]] = phi {{.*}}
-; PROMO-NEXT: %[[PROMO3:[a-z0-9.]+]] = load{{.*}}@__profc_foo{{.*}}1)
+; PROMO-NEXT: %[[PROMO3:[a-z0-9.]+]] = load{{.*}}@__profc_foo{{.*}} 8)
; PROMO-NEXT: {{.*}} = add {{.*}}%[[PROMO3]], %[[MERGE3]]
-; PROMO-NEXT: store{{.*}}@__profc_foo{{.*}}1)
-; PROMO-NEXT: %[[PROMO2:[a-z0-9.]+]] = load{{.*}}@__profc_foo{{.*}}2)
+; PROMO-NEXT: store{{.*}}@__profc_foo{{.*}} 8)
+; PROMO-NEXT: %[[PROMO2:[a-z0-9.]+]] = load{{.*}}@__profc_foo{{.*}} 16)
; PROMO-NEXT: {{.*}} = add {{.*}}%[[PROMO2]], %[[MERGE2]]
-; PROMO-NEXT: store{{.*}}@__profc_foo{{.*}}2)
-; PROMO-NEXT: %[[PROMO1:[a-z0-9.]+]] = load{{.*}}@__profc_foo{{.*}}3)
+; PROMO-NEXT: store{{.*}}@__profc_foo{{.*}} 16)
+; PROMO-NEXT: %[[PROMO1:[a-z0-9.]+]] = load{{.*}}@__profc_foo{{.*}} 24)
; PROMO-NEXT: {{.*}} = add {{.*}}%[[PROMO1]], %[[MERGE1]]
-; PROMO-NEXT: store{{.*}}@__profc_foo{{.*}}3)
+; PROMO-NEXT: store{{.*}}@__profc_foo{{.*}} 24)
bb15: ; preds = %bb14
call void @llvm.instrprof.increment(ptr @__profn_foo, i64 63969943867, i32 5, i32 4)
diff --git a/llvm/test/Transforms/PGOProfile/counter_promo_mexits.ll b/llvm/test/Transforms/PGOProfile/counter_promo_mexits.ll
index 7c0411fcb9921d..52a47c74866972 100644
--- a/llvm/test/Transforms/PGOProfile/counter_promo_mexits.ll
+++ b/llvm/test/Transforms/PGOProfile/counter_promo_mexits.ll
@@ -42,15 +42,15 @@ bb14: ; preds = %bb11
; PROMO: %pgocount.promoted{{.*}} = load i64, ptr @__profc_foo, align 4
; PROMO-NEXT: add
; PROMO-NEXT: store i64 %3, ptr @__profc_foo, align 4
-; PROMO-NEXT: %pgocount.promoted{{.*}} = load i64, ptr getelementptr inbounds ([5 x i64], ptr @__profc_foo, i32 0, i32 1), align 4
+; PROMO-NEXT: %pgocount.promoted{{.*}} = load i64, ptr getelementptr inbounds (i8, ptr @__profc_foo, i64 8), align 4
; PROMO-NEXT: add
-; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}1)
-; PROMO-NEXT: %pgocount.promoted{{.*}} = load i64, ptr getelementptr inbounds ([5 x i64], ptr @__profc_foo, i32 0, i32 2), align 4
+; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}} 8)
+; PROMO-NEXT: %pgocount.promoted{{.*}} = load i64, ptr getelementptr inbounds (i8, ptr @__profc_foo, i64 16), align 4
; PROMO-NEXT: add
-; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}2)
-; PROMO-NEXT: %pgocount{{.*}} = load i64, ptr getelementptr inbounds ([5 x i64], ptr @__profc_foo, i32 0, i32 3), align 4
+; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}} 16)
+; PROMO-NEXT: %pgocount{{.*}} = load i64, ptr getelementptr inbounds (i8, ptr @__profc_foo, i64 24), align 4
; PROMO-NEXT: add
-; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}3)
+; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}} 24)
bb15_0: ; preds = %bb11
@@ -59,15 +59,15 @@ bb15_0: ; preds = %bb11
; PROMO: %pgocount.promoted{{.*}} = load i64, ptr @__profc_foo, align 4
; PROMO-NEXT: add
; PROMO-NEXT: store {{.*}} @__profc_foo, align 4
-; PROMO-NEXT: %pgocount.promoted{{.*}} = load i64, ptr getelementptr inbounds ([5 x i64], ptr @__profc_foo, i32 0, i32 1), align 4
+; PROMO-NEXT: %pgocount.promoted{{.*}} = load i64, ptr getelementptr inbounds (i8, ptr @__profc_foo, i64 8), align 4
; PROMO-NEXT: add
-; PROMO-NEXT: store {{.*}} ptr getelementptr inbounds ([5 x i64], ptr @__profc_foo, i32 0, i32 1), align 4
-; PROMO-NEXT: %pgocount.promoted{{.*}} = load i64, ptr getelementptr inbounds ([5 x i64], ptr @__profc_foo, i32 0, i32 2), align 4
+; PROMO-NEXT: store {{.*}} ptr getelementptr inbounds (i8, ptr @__profc_foo, i64 8), align 4
+; PROMO-NEXT: %pgocount.promoted{{.*}} = load i64, ptr getelementptr inbounds (i8, ptr @__profc_foo, i64 16), align 4
; PROMO-NEXT: add
-; PROMO-NEXT: store {{.*}} ptr getelementptr inbounds ([5 x i64], ptr @__profc_foo, i32 0, i32 2), align 4
-; PROMO-NEXT: %pgocount{{.*}} = load {{.*}} @__profc_foo{{.*}} 4)
+; PROMO-NEXT: store {{.*}} ptr getelementptr inbounds (i8, ptr @__profc_foo, i64 16), align 4
+; PROMO-NEXT: %pgocount{{.*}} = load {{.*}} @__profc_foo{{.*}} 32)
; PROMO-NEXT: add
-; PROMO-NEXT: store {{.*}} ptr getelementptr inbounds ([5 x i64], ptr @__profc_foo, i32 0, i32 4), align 4
+; PROMO-NEXT: store {{.*}} ptr getelementptr inbounds (i8, ptr @__profc_foo, i64 32), align 4
; PROMO-NOT: @__profc_foo{{.*}})
diff --git a/llvm/test/Transforms/PGOProfile/counter_promo_sampling.ll b/llvm/test/Transforms/PGOProfile/counter_promo_sampling.ll
index 43377f695be675..816849b136d51f 100644
--- a/llvm/test/Transforms/PGOProfile/counter_promo_sampling.ll
+++ b/llvm/test/Transforms/PGOProfile/counter_promo_sampling.ll
@@ -8,9 +8,9 @@ define void @foo(i32 %n, i32 %N) {
; SAMPLING: %[[VV0:[0-9]+]] = load i16, ptr @__llvm_profile_sampling, align 2
; SAMPLING: %[[VV1:[0-9]+]] = icmp ule i16 %[[VV0]], 199
; SAMPLING: br i1 %[[VV1]], label {{.*}}, label {{.*}}, !prof !0
-; SAMPLING: {{.*}} = load {{.*}} @__profc_foo{{.*}} 3)
+; SAMPLING: {{.*}} = load {{.*}} @__profc_foo{{.*}} 24)
; SAMPLING-NEXT: add
-; SAMPLING-NEXT: store {{.*}}@__profc_foo{{.*}}3)
+; SAMPLING-NEXT: store {{.*}}@__profc_foo{{.*}} 24)
bb:
%tmp = add nsw i32 %n, 1
%tmp1 = add nsw i32 %n, -1
@@ -63,12 +63,12 @@ bb12:
; PROMO: %[[CHECK1:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}}
; PROMO-NEXT: add {{.*}} %[[CHECK1]], %[[LIVEOUT1]]
; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}
-; PROMO-NEXT: %[[CHECK2:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 1)
+; PROMO-NEXT: %[[CHECK2:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 8)
; PROMO-NEXT: add {{.*}} %[[CHECK2]], %[[LIVEOUT2]]
-; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}1)
-; PROMO-NEXT: %[[CHECK3:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 2)
+; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}} 8)
+; PROMO-NEXT: %[[CHECK3:[a-z0-9.]+]] = load {{.*}} @__profc_foo{{.*}} 16)
; PROMO-NEXT: add {{.*}} %[[CHECK3]], %[[LIVEOUT3]]
-; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}}2)
+; PROMO-NEXT: store {{.*}}@__profc_foo{{.*}} 16)
; PROMO-NOT: @__profc_foo{{.*}})
}
diff --git a/llvm/test/Transforms/PGOProfile/instr_entry_bb.ll b/llvm/test/Transforms/PGOProfile/instr_entry_bb.ll
index ee088674e35e27..cc40867e427a00 100644
--- a/llvm/test/Transforms/PGOProfile/instr_entry_bb.ll
+++ b/llvm/test/Transforms/PGOProfile/instr_entry_bb.ll
@@ -32,9 +32,9 @@ if.else:
; GEN: if.else:
; GEN: call void @llvm.instrprof.increment(ptr @__profn_test_br_2, i64 {{[0-9]+}}, i32 2, i32 1)
; GENA: if.else:
-; GENA: %pgocount = load i64, ptr getelementptr inbounds ([2 x i64], ptr @__profc_test_br_2, i32 0, i32 1), align 8
+; GENA: %pgocount = load i64, ptr getelementptr inbounds (i8, ptr @__profc_test_br_2, i64 8), align 8
; GENA: [[V:%[0-9]*]] = add i64 %pgocount, 1
-; GENA: store i64 [[V]], ptr getelementptr inbounds ([2 x i64], ptr @__profc_test_br_2, i32 0, i32 1), align 8
+; GENA: store i64 [[V]], ptr getelementptr inbounds (i8, ptr @__profc_test_br_2, i64 8), align 8
%sub = sub nsw i32 %i, 2
br label %if.end
diff --git a/llvm/test/Transforms/SROA/phi-gep.ll b/llvm/test/Transforms/SROA/phi-gep.ll
index 22d69d801c3d7d..b01b999bd31ef0 100644
--- a/llvm/test/Transforms/SROA/phi-gep.ll
+++ b/llvm/test/Transforms/SROA/phi-gep.ll
@@ -97,7 +97,7 @@ define i32 @test_sroa_phi_gep_global(i1 %cond) {
; CHECK-NEXT: entry:
; CHECK-NEXT: br i1 [[COND:%.*]], label [[IF_THEN:%.*]], label [[END:%.*]]
; CHECK: if.then:
-; CHECK-NEXT: [[PHI_SROA_PHI_SROA_SPECULATE_LOAD_IF_THEN:%.*]] = load i32, ptr getelementptr inbounds ([[PAIR:%.*]], ptr @g, i32 0, i32 1), align 4
+; CHECK-NEXT: [[PHI_SROA_PHI_SROA_SPECULATE_LOAD_IF_THEN:%.*]] = load i32, ptr getelementptr inbounds (i8, ptr @g, i64 4), align 4
; CHECK-NEXT: br label [[END]]
; CHECK: end:
; CHECK-NEXT: [[PHI_SROA_PHI_SROA_SPECULATED:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[PHI_SROA_PHI_SROA_SPECULATE_LOAD_IF_THEN]], [[IF_THEN]] ]
diff --git a/llvm/test/tools/llvm-reduce/ifunc-alias.ll b/llvm/test/tools/llvm-reduce/ifunc-alias.ll
index 258eb00383f7e6..c9b9204d401f3f 100644
--- a/llvm/test/tools/llvm-reduce/ifunc-alias.ll
+++ b/llvm/test/tools/llvm-reduce/ifunc-alias.ll
@@ -52,7 +52,7 @@ define float @call_ifunc_aliasee(i64 %arg) {
; ALL-LABEL: @call_alias_of_ifunc(
; CHECK-FINAL-IFUNCS: call float @alias_of_ifunc(
-; CHECK-FINAL-BOTH-NEXT: %1 = load ptr, ptr getelementptr inbounds ([2 x ptr], ptr [[TABLE]], i32 0, i32 1), align 8
+; CHECK-FINAL-BOTH-NEXT: %1 = load ptr, ptr getelementptr inbounds (i8, ptr [[TABLE]], i64 8), align 8
; CHECK-FINAL-BOTH-NEXT: %call = call float %1(i64 %arg)
; CHECK-FINAL-BOTH-NEXT: ret float %call
define float @call_alias_of_ifunc(i64 %arg) {
@@ -64,5 +64,5 @@ define float @call_alias_of_ifunc(i64 %arg) {
; CHECK-FINAL-BOTH-NEXT: %1 = call ptr @resolver()
; CHECK-FINAL-BOTH-NEXT: store ptr %1, ptr [[TABLE]], align 8
; CHECK-FINAL-BOTH-NEXT: %2 = call ptr @resolver()
-; CHECK-FINAL-BOTH-NEXT: store ptr %2, ptr getelementptr inbounds ([2 x ptr], ptr [[TABLE]], i32 0, i32 1), align 8
+; CHECK-FINAL-BOTH-NEXT: store ptr %2, ptr getelementptr inbounds (i8, ptr [[TABLE]], i64 8), align 8
; CHECK-FINAL-BOTH-NEXT: ret void
diff --git a/llvm/test/tools/llvm-reduce/remove-ifunc-program-addrspace.ll b/llvm/test/tools/llvm-reduce/remove-ifunc-program-addrspace.ll
index e275d61764b216..7ccaa5893e2ba8 100644
--- a/llvm/test/tools/llvm-reduce/remove-ifunc-program-addrspace.ll
+++ b/llvm/test/tools/llvm-reduce/remove-ifunc-program-addrspace.ll
@@ -64,12 +64,12 @@ define ptr addrspace(0) @resolver0_in_1() addrspace(1) {
define void @call_removed() addrspace(0) {
; CHECK-FINAL-LABEL: @call_removed(
- ; CHECK-FINAL-NEXT: %1 = load ptr addrspace(1), ptr addrspace(2) getelementptr inbounds ([6 x ptr addrspace(1)], ptr addrspace(2) [[TABLE]], i32 0, i32 3), align 8
+ ; CHECK-FINAL-NEXT: %1 = load ptr addrspace(1), ptr addrspace(2) getelementptr inbounds (i8, ptr addrspace(2) [[TABLE]], i64 24), align 8
; CHECK-FINAL-NEXT: %2 = addrspacecast ptr addrspace(1) %1 to ptr
; CHECK-FINAL-NEXT: call addrspace(0) void %2()
- ; CHECK-FINAL-NEXT: %3 = load ptr addrspace(1), ptr addrspace(2) getelementptr inbounds ([6 x ptr addrspace(1)], ptr addrspace(2) [[TABLE]], i32 0, i32 4), align 8
+ ; CHECK-FINAL-NEXT: %3 = load ptr addrspace(1), ptr addrspace(2) getelementptr inbounds (i8, ptr addrspace(2) [[TABLE]], i64 32), align 8
; CHECK-FINAL-NEXT: call addrspace(1) void %3()
- ; CHECK-FINAL-NEXT: %4 = load ptr addrspace(1), ptr addrspace(2) getelementptr inbounds ([6 x ptr addrspace(1)], ptr addrspace(2) [[TABLE]], i32 0, i32 5), align 8
+ ; CHECK-FINAL-NEXT: %4 = load ptr addrspace(1), ptr addrspace(2) getelementptr inbounds (i8, ptr addrspace(2) [[TABLE]], i64 40), align 8
; CHECK-FINAL-NEXT: call addrspace(1) void %4()
; CHECK-FINAL-NEXT: ret void
call addrspace(0) void @ifunc_remove_as1_resolver_in_0()
@@ -94,14 +94,14 @@ define void @load_removed() addrspace(0) {
; CHECK-FINAL-NEXT: %1 = call addrspace(1) ptr addrspace(1) @resolver1_in_1()
; CHECK-FINAL-NEXT: store ptr addrspace(1) %1, ptr addrspace(2) [[TABLE]], align 8
; CHECK-FINAL-NEXT: %2 = call addrspace(0) ptr addrspace(1) @resolver1_in_0()
-; CHECK-FINAL-NEXT: store ptr addrspace(1) %2, ptr addrspace(2) getelementptr inbounds ([6 x ptr addrspace(1)], ptr addrspace(2) [[TABLE]], i32 0, i32 1), align 8
+; CHECK-FINAL-NEXT: store ptr addrspace(1) %2, ptr addrspace(2) getelementptr inbounds (i8, ptr addrspace(2) [[TABLE]], i64 8), align 8
; CHECK-FINAL-NEXT: %3 = call addrspace(1) ptr @resolver0_in_1()
; CHECK-FINAL-NEXT: %4 = addrspacecast ptr %3 to ptr addrspace(1)
-; CHECK-FINAL-NEXT: store ptr addrspace(1) %4, ptr addrspace(2) getelementptr inbounds ([6 x ptr addrspace(1)], ptr addrspace(2) [[TABLE]], i32 0, i32 2), align 8
+; CHECK-FINAL-NEXT: store ptr addrspace(1) %4, ptr addrspace(2) getelementptr inbounds (i8, ptr addrspace(2) [[TABLE]], i64 16), align 8
; CHECK-FINAL-NEXT: %5 = call addrspace(0) ptr addrspace(1) @resolver1_in_0()
-; CHECK-FINAL-NEXT: store ptr addrspace(1) %5, ptr addrspace(2) getelementptr inbounds ([6 x ptr addrspace(1)], ptr addrspace(2) [[TABLE]], i32 0, i32 3), align 8
+; CHECK-FINAL-NEXT: store ptr addrspace(1) %5, ptr addrspace(2) getelementptr inbounds (i8, ptr addrspace(2) [[TABLE]], i64 24), align 8
; CHECK-FINAL-NEXT: %6 = call addrspace(1) ptr addrspace(1) @resolver1_in_1()
-; CHECK-FINAL-NEXT: store ptr addrspace(1) %6, ptr addrspace(2) getelementptr inbounds ([6 x ptr addrspace(1)], ptr addrspace(2) [[TABLE]], i32 0, i32 4), align 8
+; CHECK-FINAL-NEXT: store ptr addrspace(1) %6, ptr addrspace(2) getelementptr inbounds (i8, ptr addrspace(2) [[TABLE]], i64 32), align 8
; CHECK-FINAL-NEXT: %7 = call addrspace(0) ptr addrspace(1) @resolver1_in_0()
-; CHECK-FINAL-NEXT: store ptr addrspace(1) %7, ptr addrspace(2) getelementptr inbounds ([6 x ptr addrspace(1)], ptr addrspace(2) [[TABLE]], i32 0, i32 5), align 8
+; CHECK-FINAL-NEXT: store ptr addrspace(1) %7, ptr addrspace(2) getelementptr inbounds (i8, ptr addrspace(2) [[TABLE]], i64 40), align 8
; CHECK-FINAL-NEXT: ret void
diff --git a/llvm/test/tools/llvm-reduce/remove-ifunc.ll b/llvm/test/tools/llvm-reduce/remove-ifunc.ll
index a7853d937d9a65..f7dbe689e0951c 100644
--- a/llvm/test/tools/llvm-reduce/remove-ifunc.ll
+++ b/llvm/test/tools/llvm-reduce/remove-ifunc.ll
@@ -117,8 +117,8 @@ define void @call_ifunc_removed_is_argument(ptr %ptr) {
; Check a call user calling the ifunc, and using the ifunc as an argument
define void @call_ifunc_removed_both_call_argument(ptr %ptr) {
; CHECK-FINAL-LABEL: define void @call_ifunc_removed_both_call_argument(
- ; CHECK-FINAL-NEXT: %1 = load ptr, ptr getelementptr inbounds ([[[TABLE_SIZE]] x ptr], ptr [[TABLE]], i32 0, i32 3), align 8
- ; CHECK-FINAL-NEXT: %2 = load ptr, ptr getelementptr inbounds ([[[TABLE_SIZE]] x ptr], ptr [[TABLE]], i32 0, i32 3), align 8
+ ; CHECK-FINAL-NEXT: %1 = load ptr, ptr getelementptr inbounds (i8, ptr [[TABLE]], i64 24), align 8
+ ; CHECK-FINAL-NEXT: %2 = load ptr, ptr getelementptr inbounds (i8, ptr [[TABLE]], i64 24), align 8
; CHECK-FINAL-NEXT: call void %1(ptr %1)
; CHECK-FINAL-NEXT: ret void
call void @ifunc_ptr_arg(ptr @ifunc_ptr_arg)
@@ -128,7 +128,7 @@ define void @call_ifunc_removed_both_call_argument(ptr %ptr) {
define i32 @call_ifunc_nonvoid(double %arg) {
; CHECK-FINAL-LABEL: define i32 @call_ifunc_nonvoid(double %arg) {
; CHECK-FINAL-NEXT: %ret0 = call i32 @ifunc_nonvoid_kept0(double %arg)
- ; CHECK-FINAL-NEXT: %1 = load ptr, ptr getelementptr inbounds ([[[TABLE_SIZE]] x ptr], ptr [[TABLE]], i32 0, i32 4), align 8
+ ; CHECK-FINAL-NEXT: %1 = load ptr, ptr getelementptr inbounds (i8, ptr [[TABLE]], i64 32), align 8
; CHECK-FINAL-NEXT: %ret1 = call i32 %1(double %arg)
; CHECK-FINAL-NEXT: %add = add i32 %ret0, %ret1
; CHECK-FINAL-NEXT: ret i32 %add
@@ -143,7 +143,7 @@ define float @call_different_type_ifunc_nonvoid(double %arg) {
; CHECK-FINAL-LABEL: define float @call_different_type_ifunc_nonvoid(double %arg) {
; CHECK-FINAL-NEXT: %cast.arg = bitcast double %arg to i64
; CHECK-FINAL-NEXT: %ret0 = call float @ifunc_nonvoid_kept0(i64 %cast.arg)
- ; CHECK-FINAL-NEXT: %1 = load ptr, ptr getelementptr inbounds ([[[TABLE_SIZE]] x ptr], ptr [[TABLE]], i32 0, i32 4), align 8
+ ; CHECK-FINAL-NEXT: %1 = load ptr, ptr getelementptr inbounds (i8, ptr [[TABLE]], i64 32), align 8
; CHECK-FINAL-NEXT: %ret1 = call float %1(i64 %cast.arg)
; CHECK-FINAL-NEXT: %fadd = fadd float %ret0, %ret1
; CHECK-FINAL-NEXT: ret float %fadd
@@ -170,7 +170,7 @@ define i32 @call_addrspacecast_callee_type_ifunc_nonvoid(double %arg) {
define i32 @call_used_in_initializer(double %arg) {
; CHECK-FINAL-LABEL: define i32 @call_used_in_initializer(double %arg) {
- ; CHECK-FINAL-NEXT: %1 = load ptr, ptr getelementptr inbounds ([8 x ptr], ptr @0, i32 0, i32 7), align 8
+ ; CHECK-FINAL-NEXT: %1 = load ptr, ptr getelementptr inbounds (i8, ptr @0, i64 56), align 8
; CHECK-FINAL-NEXT: %ret = call i32 %1(double %arg)
; CHECK-FINAL-NEXT: ret i32 %ret
%ret = call i32 @ifunc_constant_initializer_user(double %arg)
@@ -181,18 +181,18 @@ define i32 @call_used_in_initializer(double %arg) {
; CHECK-FINAL-NEXT: %1 = call ptr @resolver1()
; CHECK-FINAL-NEXT: store ptr %1, ptr @0, align 8
; CHECK-FINAL-NEXT: %2 = call ptr @resolver2()
-; CHECK-FINAL-NEXT: store ptr %2, ptr getelementptr inbounds ([8 x ptr], ptr @0, i32 0, i32 1), align 8
+; CHECK-FINAL-NEXT: store ptr %2, ptr getelementptr inbounds (i8, ptr @0, i64 8), align 8
; CHECK-FINAL-NEXT: %3 = call ptr @resolver3()
-; CHECK-FINAL-NEXT: store ptr %3, ptr getelementptr inbounds ([8 x ptr], ptr @0, i32 0, i32 2), align 8
+; CHECK-FINAL-NEXT: store ptr %3, ptr getelementptr inbounds (i8, ptr @0, i64 16), align 8
; CHECK-FINAL-NEXT: %4 = call ptr @resolver4()
-; CHECK-FINAL-NEXT: store ptr %4, ptr getelementptr inbounds ([8 x ptr], ptr @0, i32 0, i32 3), align 8
+; CHECK-FINAL-NEXT: store ptr %4, ptr getelementptr inbounds (i8, ptr @0, i64 24), align 8
; CHECK-FINAL-NEXT: %5 = call ptr @resolver5()
-; CHECK-FINAL-NEXT: store ptr %5, ptr getelementptr inbounds ([8 x ptr], ptr @0, i32 0, i32 4), align 8
+; CHECK-FINAL-NEXT: store ptr %5, ptr getelementptr inbounds (i8, ptr @0, i64 32), align 8
; CHECK-FINAL-NEXT: %6 = call ptr @resolver5()
-; CHECK-FINAL-NEXT: store ptr %6, ptr getelementptr inbounds ([8 x ptr], ptr @0, i32 0, i32 5), align 8
+; CHECK-FINAL-NEXT: store ptr %6, ptr getelementptr inbounds (i8, ptr @0, i64 40), align 8
; CHECK-FINAL-NEXT: %7 = call ptr @resolver5()
-; CHECK-FINAL-NEXT: store ptr %7, ptr getelementptr inbounds ([8 x ptr], ptr @0, i32 0, i32 6), align 8
+; CHECK-FINAL-NEXT: store ptr %7, ptr getelementptr inbounds (i8, ptr @0, i64 48), align 8
; CHECK-FINAL-NEXT: %8 = call ptr @resolver5()
-; CHECK-FINAL-NEXT: store ptr %8, ptr getelementptr inbounds ([8 x ptr], ptr @0, i32 0, i32 7), align 8
+; CHECK-FINAL-NEXT: store ptr %8, ptr getelementptr inbounds (i8, ptr @0, i64 56), align 8
; CHECK-FINAL-NEXT: ret void
; CHECK-FINAL-NEXT: }
More information about the llvm-commits
mailing list