[llvm] d689d0f - [DFSan] Generate test checks (NFC) (#226410)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 02:31:19 PDT 2026
Author: Nikita Popov
Date: 2026-09-25T11:31:11+02:00
New Revision: d689d0fd01a0ffcfbc1c947ec3a14997f96217d0
URL: https://github.com/llvm/llvm-project/commit/d689d0fd01a0ffcfbc1c947ec3a14997f96217d0
DIFF: https://github.com/llvm/llvm-project/commit/d689d0fd01a0ffcfbc1c947ec3a14997f96217d0.diff
LOG: [DFSan] Generate test checks (NFC) (#226410)
Added:
Modified:
llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
Removed:
################################################################################
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
index a0c642a3cd0e1..5d6a5b0b0af7f 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_load.ll
@@ -1,51 +1,57 @@
-; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,COMBINE_LOAD_PTR
-; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-combine-pointer-labels-on-load=false -S | FileCheck %s
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-add-global-name-suffix=0 -S | FileCheck %s --check-prefixes=CHECK,COMBINE_LOAD_PTR
+; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-combine-pointer-labels-on-load=false -dfsan-add-global-name-suffix=0 -S | FileCheck %s --check-prefixes=CHECK,NO_COMBINE_LOAD_PTR
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define {} @load0(ptr %p) {
- ; CHECK-LABEL: @load0.dfsan
- ; CHECK-NEXT: %a = load {}, ptr %p, align 1
- ; CHECK-NEXT: store {} zeroinitializer, ptr @__dfsan_retval_tls, align [[ALIGN:2]]
- ; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4
- ; CHECK-NEXT: ret {} %a
-
+; CHECK-LABEL: define {} @load0(
+; CHECK-SAME: ptr [[P:%.*]]) {
+; CHECK-NEXT: [[A:%.*]] = load {}, ptr [[P]], align 1
+; CHECK-NEXT: store {} zeroinitializer, ptr @__dfsan_retval_tls, align 2
+; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4
+; CHECK-NEXT: ret {} [[A]]
+;
%a = load {}, ptr %p
ret {} %a
}
define i16 @load_non_escaped_alloca() {
- ; CHECK-LABEL: @load_non_escaped_alloca.dfsan
- ; CHECK-NEXT: %[[#S_ALLOCA:]] = alloca i8, align 1
- ; CHECK-NEXT: %_dfsa = alloca i32, align 4
- ; CHECK: %[[#SHADOW:]] = load i8, ptr %[[#S_ALLOCA]], align 1
- ; CHECK-NEXT: %[[#ORIGIN:]] = load i32, ptr %_dfsa, align 4
- ; CHECK-NEXT: %a = load i16, ptr %p, align 2
- ; CHECK-NEXT: store i8 %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4
-
+; CHECK-LABEL: define i16 @load_non_escaped_alloca() {
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 1
+; CHECK-NEXT: [[_DFSA:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[P:%.*]] = alloca i16, align 2
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr [[TMP1]], align 1
+; CHECK-NEXT: [[TMP3:%.*]] = load i32, ptr [[_DFSA]], align 4
+; CHECK-NEXT: [[A:%.*]] = load i16, ptr [[P]], align 2
+; CHECK-NEXT: store i8 [[TMP2]], ptr @__dfsan_retval_tls, align 2
+; CHECK-NEXT: store i32 [[TMP3]], ptr @__dfsan_retval_origin_tls, align 4
+; CHECK-NEXT: ret i16 [[A]]
+;
%p = alloca i16
%a = load i16, ptr %p
ret i16 %a
}
define ptr @load_escaped_alloca() {
- ; CHECK-LABEL: @load_escaped_alloca.dfsan
- ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64
- ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]]
- ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN_OFFSET:]] = add i64 %[[#SHADOW_OFFSET]], [[#%.10d,ORIGIN_BASE:]]
- ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = and i64 %[[#ORIGIN_OFFSET]], -4
- ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr
- ; CHECK-NEXT: {{%.*}} = load i32, ptr %[[#ORIGIN_PTR]], align 4
- ; CHECK-NEXT: %[[#SHADOW_PTR1:]] = getelementptr i8, ptr %[[#SHADOW_PTR0]], i64 1
- ; CHECK-NEXT: %[[#SHADOW:]] = load i8, ptr %[[#SHADOW_PTR0]], align 1
- ; CHECK-NEXT: %[[#SHADOW+1]] = load i8, ptr %[[#SHADOW_PTR1]], align 1
- ; CHECK-NEXT: {{%.*}} = or i8 %[[#SHADOW]], %[[#SHADOW+1]]
- ; CHECK-NEXT: %a = load i16, ptr %p, align 2
- ; CHECK-NEXT: store i8 0, ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4
-
+; CHECK-LABEL: define ptr @load_escaped_alloca() {
+; CHECK-NEXT: [[P:%.*]] = alloca i16, align 2
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; CHECK-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4
+; CHECK-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; CHECK-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP3]], i64 1
+; CHECK-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP3]], align 1
+; CHECK-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP8]], align 1
+; CHECK-NEXT: [[TMP11:%.*]] = or i8 [[TMP9]], [[TMP10]]
+; CHECK-NEXT: [[A:%.*]] = load i16, ptr [[P]], align 2
+; CHECK-NEXT: store i8 0, ptr @__dfsan_retval_tls, align 2
+; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4
+; CHECK-NEXT: ret ptr [[P]]
+;
%p = alloca i16
%a = load i16, ptr %p
ret ptr %p
@@ -53,235 +59,358 @@ define ptr @load_escaped_alloca() {
@X = constant i1 1
define i1 @load_global() {
- ; CHECK-LABEL: @load_global.dfsan
- ; CHECK: %a = load i1, ptr @X, align 1
- ; CHECK-NEXT: store i8 0, ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4
-
+; CHECK-LABEL: define i1 @load_global() {
+; CHECK-NEXT: [[A:%.*]] = load i1, ptr @X, align 1
+; CHECK-NEXT: store i8 0, ptr @__dfsan_retval_tls, align 2
+; CHECK-NEXT: store i32 0, ptr @__dfsan_retval_origin_tls, align 4
+; CHECK-NEXT: ret i1 [[A]]
+;
%a = load i1, ptr @X
ret i1 %a
}
define i1 @load1(ptr %p) {
- ; CHECK-LABEL: @load1.dfsan
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64
- ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]]
- ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN_OFFSET:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]]
- ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = and i64 %[[#ORIGIN_OFFSET]], -4
- ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr
- ; CHECK-NEXT: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 4
- ; CHECK-NEXT: %[[#AS:]] = load i8, ptr %[[#SHADOW_PTR]], align 1
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#AS:]] = or i8 %[[#AS]], %[[#PS]]
- ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_LOAD_PTR-NEXT: %[[#AO:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#AO]]
-
- ; CHECK-NEXT: %a = load i1, ptr %p, align 1
- ; CHECK-NEXT: store i8 %[[#AS]], ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 %[[#AO]], ptr @__dfsan_retval_origin_tls, align 4
-
+; COMBINE_LOAD_PTR-LABEL: define i1 @load1(
+; COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -4
+; COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP5]], align 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = or i8 [[TMP10]], [[TMP2]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP12:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP13:%.*]] = select i1 [[TMP12]], i32 [[TMP1]], i32 [[TMP9]]
+; COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i1, ptr [[P]], align 1
+; COMBINE_LOAD_PTR-NEXT: store i8 [[TMP11]], ptr @__dfsan_retval_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: store i32 [[TMP13]], ptr @__dfsan_retval_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: ret i1 [[A]]
+;
+; NO_COMBINE_LOAD_PTR-LABEL: define i1 @load1(
+; NO_COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = load i8, ptr [[TMP3]], align 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i1, ptr [[P]], align 1
+; NO_COMBINE_LOAD_PTR-NEXT: store i8 [[TMP8]], ptr @__dfsan_retval_tls, align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i32 [[TMP7]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_COMBINE_LOAD_PTR-NEXT: ret i1 [[A]]
+;
%a = load i1, ptr %p
ret i1 %a
}
define i16 @load16(i1 %i, ptr %p) {
- ; CHECK-LABEL: @load16.dfsan
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64
- ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]]
- ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN_OFFSET:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]]
- ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = and i64 %[[#ORIGIN_OFFSET]], -4
- ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr
- ; CHECK-NEXT: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 4
- ; CHECK-NEXT: %[[#SHADOW_PTR1:]] = getelementptr i8, ptr %[[#SHADOW_PTR0]], i64 1
- ; CHECK-NEXT: %[[#SHADOW:]] = load i8, ptr %[[#SHADOW_PTR0]], align 1
- ; CHECK-NEXT: %[[#SHADOW+1]] = load i8, ptr %[[#SHADOW_PTR1]], align 1
- ; CHECK-NEXT: %[[#AS:]] = or i8 %[[#SHADOW]], %[[#SHADOW+1]]
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#AS:]] = or i8 %[[#AS]], %[[#PS]]
- ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_LOAD_PTR-NEXT: %[[#AO:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#AO]]
-
- ; CHECK-NEXT: %a = load i16, ptr %p, align 2
- ; CHECK-NEXT: store i8 %[[#AS]], ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 %[[#AO]], ptr @__dfsan_retval_origin_tls, align 4
-
+; COMBINE_LOAD_PTR-LABEL: define i16 @load16(
+; COMBINE_LOAD_PTR-SAME: i1 [[I:%.*]], ptr [[P:%.*]]) {
+; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -4
+; COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP8]], align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP5]], i64 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = load i8, ptr [[TMP5]], align 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP12:%.*]] = load i8, ptr [[TMP10]], align 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP13:%.*]] = or i8 [[TMP11]], [[TMP12]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP14:%.*]] = or i8 [[TMP13]], [[TMP2]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP15:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i32 [[TMP1]], i32 [[TMP9]]
+; COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i16, ptr [[P]], align 2
+; COMBINE_LOAD_PTR-NEXT: store i8 [[TMP14]], ptr @__dfsan_retval_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: store i32 [[TMP16]], ptr @__dfsan_retval_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: ret i16 [[A]]
+;
+; NO_COMBINE_LOAD_PTR-LABEL: define i16 @load16(
+; NO_COMBINE_LOAD_PTR-SAME: i1 [[I:%.*]], ptr [[P:%.*]]) {
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = and i64 [[TMP4]], -4
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = inttoptr i64 [[TMP5]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP6]], align 4
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[TMP3]], i64 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = load i8, ptr [[TMP3]], align 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = load i8, ptr [[TMP8]], align 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = or i8 [[TMP9]], [[TMP10]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i16, ptr [[P]], align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i8 [[TMP11]], ptr @__dfsan_retval_tls, align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i32 [[TMP7]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_COMBINE_LOAD_PTR-NEXT: ret i16 [[A]]
+;
%a = load i16, ptr %p
ret i16 %a
}
define i32 @load32(ptr %p) {
- ; CHECK-LABEL: @load32.dfsan
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64
- ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]]
- ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]]
- ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr
- ; CHECK-NEXT: %[[#AO:]] = load i32, ptr %[[#ORIGIN_PTR]], align 4
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i[[#WSBITS:32]], ptr %[[#SHADOW_PTR]], align 1
- ; CHECK-NEXT: %[[#WIDE_SHADOW+1]] = lshr i[[#WSBITS]] %[[#WIDE_SHADOW]], 16
- ; CHECK-NEXT: %[[#WIDE_SHADOW+2]] = or i[[#WSBITS]] %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW+1]]
- ; CHECK-NEXT: %[[#WIDE_SHADOW+3]] = lshr i[[#WSBITS]] %[[#WIDE_SHADOW+2]], 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW+4]] = or i[[#WSBITS]] %[[#WIDE_SHADOW+2]], %[[#WIDE_SHADOW+3]]
- ; CHECK-NEXT: %[[#SHADOW:]] = trunc i[[#WSBITS]] %[[#WIDE_SHADOW+4]] to i8
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i8 %[[#SHADOW]], %[[#PS]]
- ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_LOAD_PTR-NEXT: %[[#AO:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#AO]]
-
- ; CHECK-NEXT: %a = load i32, ptr %p, align 4
- ; CHECK-NEXT: store i8 %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 %[[#AO]], ptr @__dfsan_retval_origin_tls, align 4
-
+; COMBINE_LOAD_PTR-LABEL: define i32 @load32(
+; COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = load i32, ptr [[TMP5]], align 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 16
+; COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP10]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP12:%.*]] = lshr i32 [[TMP11]], 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP13:%.*]] = or i32 [[TMP11]], [[TMP12]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP14:%.*]] = trunc i32 [[TMP13]] to i8
+; COMBINE_LOAD_PTR-NEXT: [[TMP15:%.*]] = or i8 [[TMP14]], [[TMP2]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP16:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP17:%.*]] = select i1 [[TMP16]], i32 [[TMP1]], i32 [[TMP8]]
+; COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; COMBINE_LOAD_PTR-NEXT: store i8 [[TMP15]], ptr @__dfsan_retval_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: store i32 [[TMP17]], ptr @__dfsan_retval_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: ret i32 [[A]]
+;
+; NO_COMBINE_LOAD_PTR-LABEL: define i32 @load32(
+; NO_COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 4
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = load i32, ptr [[TMP3]], align 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = lshr i32 [[TMP7]], 16
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = or i32 [[TMP7]], [[TMP8]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = lshr i32 [[TMP9]], 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = or i32 [[TMP9]], [[TMP10]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP12:%.*]] = trunc i32 [[TMP11]] to i8
+; NO_COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i32, ptr [[P]], align 4
+; NO_COMBINE_LOAD_PTR-NEXT: store i8 [[TMP12]], ptr @__dfsan_retval_tls, align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i32 [[TMP6]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_COMBINE_LOAD_PTR-NEXT: ret i32 [[A]]
+;
%a = load i32, ptr %p
ret i32 %a
}
define i64 @load64(ptr %p) {
- ; CHECK-LABEL: @load64.dfsan
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64
- ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]]
- ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]]
- ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN:]] = load i32, ptr %[[#ORIGIN_PTR]], align 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = load i64, ptr %[[#SHADOW_PTR]], align 1
- ; CHECK-NEXT: %[[#WIDE_SHADOW_LO:]] = shl i64 %[[#WIDE_SHADOW]], 32
- ; CHECK-NEXT: %[[#ORIGIN2_PTR:]] = getelementptr i32, ptr %[[#ORIGIN_PTR]], i64 1
- ; CHECK-NEXT: %[[#ORIGIN2:]] = load i32, ptr %[[#ORIGIN2_PTR]], align 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 32
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]]
- ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 16
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]]
- ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]]
- ; CHECK-NEXT: %[[#SHADOW:]] = trunc i64 %[[#WIDE_SHADOW]] to i8
- ; CHECK-NEXT: %[[#SHADOW_NZ:]] = icmp ne i64 %[[#WIDE_SHADOW_LO]], 0
- ; CHECK-NEXT: %[[#ORIGIN:]] = select i1 %[[#SHADOW_NZ]], i32 %[[#ORIGIN]], i32 %[[#ORIGIN2]]
- ; CHECK8-NEXT: %[[#SHADOW_NZ:]] = icmp ne i64 %[[#WIDE_SHADOW_LO]], 0
- ; CHECK8-NEXT: %[[#ORIGIN:]] = select i1 %[[#SHADOW_NZ]], i32 %[[#ORIGIN]], i32 %[[#ORIGIN2]]
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i8 %[[#SHADOW]], %[[#PS]]
- ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_LOAD_PTR-NEXT: %[[#ORIGIN:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN]]
-
- ; CHECK-NEXT: %a = load i64, ptr %p, align 8
- ; CHECK-NEXT: store i8 %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4
-
+; COMBINE_LOAD_PTR-LABEL: define i64 @load64(
+; COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = shl i64 [[TMP9]], 32
+; COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP7]], i64 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP9]], 32
+; COMBINE_LOAD_PTR-NEXT: [[TMP14:%.*]] = or i64 [[TMP9]], [[TMP13]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP14]], 16
+; COMBINE_LOAD_PTR-NEXT: [[TMP16:%.*]] = or i64 [[TMP14]], [[TMP15]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP17:%.*]] = lshr i64 [[TMP16]], 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP18:%.*]] = or i64 [[TMP16]], [[TMP17]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP19:%.*]] = trunc i64 [[TMP18]] to i8
+; COMBINE_LOAD_PTR-NEXT: [[TMP20:%.*]] = icmp ne i64 [[TMP10]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP21:%.*]] = select i1 [[TMP20]], i32 [[TMP8]], i32 [[TMP12]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP22:%.*]] = or i8 [[TMP19]], [[TMP2]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP23:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP24:%.*]] = select i1 [[TMP23]], i32 [[TMP1]], i32 [[TMP21]]
+; COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i64, ptr [[P]], align 8
+; COMBINE_LOAD_PTR-NEXT: store i8 [[TMP22]], ptr @__dfsan_retval_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: store i32 [[TMP24]], ptr @__dfsan_retval_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: ret i64 [[A]]
+;
+; NO_COMBINE_LOAD_PTR-LABEL: define i64 @load64(
+; NO_COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP3]], align 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i64 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = lshr i64 [[TMP7]], 32
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP12:%.*]] = or i64 [[TMP7]], [[TMP11]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP13:%.*]] = lshr i64 [[TMP12]], 16
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP14:%.*]] = or i64 [[TMP12]], [[TMP13]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP14]], 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP16:%.*]] = or i64 [[TMP14]], [[TMP15]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP17:%.*]] = trunc i64 [[TMP16]] to i8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP18:%.*]] = icmp ne i64 [[TMP8]], 0
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP19:%.*]] = select i1 [[TMP18]], i32 [[TMP6]], i32 [[TMP10]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i64, ptr [[P]], align 8
+; NO_COMBINE_LOAD_PTR-NEXT: store i8 [[TMP17]], ptr @__dfsan_retval_tls, align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i32 [[TMP19]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_COMBINE_LOAD_PTR-NEXT: ret i64 [[A]]
+;
%a = load i64, ptr %p
ret i64 %a
}
define i64 @load64_align2(ptr %p) {
- ; CHECK-LABEL: @load64_align2.dfsan
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#LABEL_ORIGIN:]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr %p, i64 8)
- ; CHECK-NEXT: %[[#LABEL_ORIGIN+1]] = lshr i64 %[[#LABEL_ORIGIN]], 32
- ; CHECK-NEXT: %[[#LABEL:]] = trunc i64 %[[#LABEL_ORIGIN+1]] to i8
- ; CHECK-NEXT: %[[#ORIGIN:]] = trunc i64 %[[#LABEL_ORIGIN]] to i32
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#LABEL:]] = or i8 %[[#LABEL]], %[[#PS]]
- ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_LOAD_PTR-NEXT: %[[#ORIGIN:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN]]
-
- ; CHECK-NEXT: %a = load i64, ptr %p, align 2
- ; CHECK-NEXT: store i8 %[[#LABEL]], ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4
-
+; COMBINE_LOAD_PTR-LABEL: define i64 @load64_align2(
+; COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr [[P]], i64 8)
+; COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 32
+; COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
+; COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP3]] to i32
+; COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = or i8 [[TMP5]], [[TMP2]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 [[TMP1]], i32 [[TMP6]]
+; COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i64, ptr [[P]], align 2
+; COMBINE_LOAD_PTR-NEXT: store i8 [[TMP7]], ptr @__dfsan_retval_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: store i32 [[TMP9]], ptr @__dfsan_retval_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: ret i64 [[A]]
+;
+; NO_COMBINE_LOAD_PTR-LABEL: define i64 @load64_align2(
+; NO_COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr [[P]], i64 8)
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 32
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP1]] to i32
+; NO_COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i64, ptr [[P]], align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i32 [[TMP4]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_COMBINE_LOAD_PTR-NEXT: ret i64 [[A]]
+;
%a = load i64, ptr %p, align 2
ret i64 %a
}
define i128 @load128(ptr %p) {
- ; CHECK-LABEL: @load128.dfsan
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#INTP:]] = ptrtoint ptr %p to i64
- ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#MASK]]
- ; CHECK-NEXT: %[[#SHADOW_PTR:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = add i64 %[[#SHADOW_OFFSET]], [[#ORIGIN_BASE]]
- ; CHECK-NEXT: %[[#ORIGIN1_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN1:]] = load i32, ptr %[[#ORIGIN1_PTR]], align 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW1:]] = load i64, ptr %[[#SHADOW_PTR]], align 1
- ; CHECK-NEXT: %[[#WIDE_SHADOW1_LO:]] = shl i64 %[[#WIDE_SHADOW1]], 32
- ; CHECK-NEXT: %[[#ORIGIN2_PTR:]] = getelementptr i32, ptr %[[#ORIGIN1_PTR]], i64 1
- ; CHECK-NEXT: %[[#ORIGIN2:]] = load i32, ptr %[[#ORIGIN2_PTR]], align 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW2_PTR:]] = getelementptr i64, ptr %[[#SHADOW_PTR]], i64 1
- ; CHECK-NEXT: %[[#WIDE_SHADOW2:]] = load i64, ptr %[[#WIDE_SHADOW2_PTR]], align 1
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW1]], %[[#WIDE_SHADOW2]]
- ; CHECK-NEXT: %[[#ORIGIN3_PTR:]] = getelementptr i32, ptr %[[#ORIGIN2_PTR]], i64 1
- ; CHECK-NEXT: %[[#ORIGIN3:]] = load i32, ptr %[[#ORIGIN3_PTR]], align 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW2_LO:]] = shl i64 %[[#WIDE_SHADOW2]], 32
- ; CHECK-NEXT: %[[#ORIGIN4_PTR:]] = getelementptr i32, ptr %[[#ORIGIN3_PTR]], i64 1
- ; CHECK-NEXT: %[[#ORIGIN4:]] = load i32, ptr %[[#ORIGIN4_PTR]], align 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 32
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]]
- ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 16
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]]
- ; CHECK-NEXT: %[[#WIDE_SHADOW_SHIFTED:]] = lshr i64 %[[#WIDE_SHADOW]], 8
- ; CHECK-NEXT: %[[#WIDE_SHADOW:]] = or i64 %[[#WIDE_SHADOW]], %[[#WIDE_SHADOW_SHIFTED]]
- ; CHECK-NEXT: %[[#SHADOW:]] = trunc i64 %[[#WIDE_SHADOW]] to i8
- ; CHECK-NEXT: %[[#SHADOW1_LO_NZ:]] = icmp ne i64 %[[#WIDE_SHADOW1_LO]], 0
- ; CHECK-NEXT: %[[#ORIGIN12:]] = select i1 %[[#SHADOW1_LO_NZ]], i32 %[[#ORIGIN1]], i32 %[[#ORIGIN2]]
- ; CHECK-NEXT: %[[#SHADOW2_NZ:]] = icmp ne i64 %[[#WIDE_SHADOW2]], 0
- ; CHECK-NEXT: %[[#ORIGIN124:]] = select i1 %[[#SHADOW2_NZ]], i32 %[[#ORIGIN4]], i32 %[[#ORIGIN12]]
- ; CHECK-NEXT: %[[#SHADOW2_LO_NZ:]] = icmp ne i64 %[[#WIDE_SHADOW2_LO]], 0
- ; CHECK-NEXT: %[[#ORIGIN:]] = select i1 %[[#SHADOW2_LO_NZ]], i32 %[[#ORIGIN3]], i32 %[[#ORIGIN124]]
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#SHADOW:]] = or i8 %[[#SHADOW]], %[[#PS]]
- ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_LOAD_PTR-NEXT: %[[#ORIGIN:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN]]
-
- ; CHECK-NEXT: %a = load i128, ptr %p, align 8
- ; CHECK-NEXT: store i8 %[[#SHADOW]], ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4
-
+; COMBINE_LOAD_PTR-LABEL: define i128 @load128(
+; COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
+; COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = load i32, ptr [[TMP7]], align 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = load i64, ptr [[TMP5]], align 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = shl i64 [[TMP9]], 32
+; COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = getelementptr i32, ptr [[TMP7]], i64 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP12:%.*]] = load i32, ptr [[TMP11]], align 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP13:%.*]] = getelementptr i64, ptr [[TMP5]], i64 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP14:%.*]] = load i64, ptr [[TMP13]], align 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP15:%.*]] = or i64 [[TMP9]], [[TMP14]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[TMP11]], i64 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP16]], align 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP18:%.*]] = shl i64 [[TMP14]], 32
+; COMBINE_LOAD_PTR-NEXT: [[TMP19:%.*]] = getelementptr i32, ptr [[TMP16]], i64 1
+; COMBINE_LOAD_PTR-NEXT: [[TMP20:%.*]] = load i32, ptr [[TMP19]], align 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP15]], 32
+; COMBINE_LOAD_PTR-NEXT: [[TMP22:%.*]] = or i64 [[TMP15]], [[TMP21]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 16
+; COMBINE_LOAD_PTR-NEXT: [[TMP24:%.*]] = or i64 [[TMP22]], [[TMP23]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP25:%.*]] = lshr i64 [[TMP24]], 8
+; COMBINE_LOAD_PTR-NEXT: [[TMP26:%.*]] = or i64 [[TMP24]], [[TMP25]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP27:%.*]] = trunc i64 [[TMP26]] to i8
+; COMBINE_LOAD_PTR-NEXT: [[TMP28:%.*]] = icmp ne i64 [[TMP10]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i32 [[TMP8]], i32 [[TMP12]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP30:%.*]] = icmp ne i64 [[TMP14]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP31:%.*]] = select i1 [[TMP30]], i32 [[TMP20]], i32 [[TMP29]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP32:%.*]] = icmp ne i64 [[TMP18]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP33:%.*]] = select i1 [[TMP32]], i32 [[TMP17]], i32 [[TMP31]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP34:%.*]] = or i8 [[TMP27]], [[TMP2]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP35:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP36:%.*]] = select i1 [[TMP35]], i32 [[TMP1]], i32 [[TMP33]]
+; COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i128, ptr [[P]], align 8
+; COMBINE_LOAD_PTR-NEXT: store i8 [[TMP34]], ptr @__dfsan_retval_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: store i32 [[TMP36]], ptr @__dfsan_retval_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: ret i128 [[A]]
+;
+; NO_COMBINE_LOAD_PTR-LABEL: define i128 @load128(
+; NO_COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = add i64 [[TMP2]], 17592186044416
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = load i32, ptr [[TMP5]], align 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = load i64, ptr [[TMP3]], align 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = shl i64 [[TMP7]], 32
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[TMP5]], i64 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP10:%.*]] = load i32, ptr [[TMP9]], align 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP11:%.*]] = getelementptr i64, ptr [[TMP3]], i64 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP12:%.*]] = load i64, ptr [[TMP11]], align 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP13:%.*]] = or i64 [[TMP7]], [[TMP12]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[TMP9]], i64 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP15:%.*]] = load i32, ptr [[TMP14]], align 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP16:%.*]] = shl i64 [[TMP12]], 32
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[TMP14]], i64 1
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP17]], align 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP19:%.*]] = lshr i64 [[TMP13]], 32
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP20:%.*]] = or i64 [[TMP13]], [[TMP19]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP21:%.*]] = lshr i64 [[TMP20]], 16
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP22:%.*]] = or i64 [[TMP20]], [[TMP21]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP24:%.*]] = or i64 [[TMP22]], [[TMP23]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP25:%.*]] = trunc i64 [[TMP24]] to i8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP26:%.*]] = icmp ne i64 [[TMP8]], 0
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP27:%.*]] = select i1 [[TMP26]], i32 [[TMP6]], i32 [[TMP10]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP28:%.*]] = icmp ne i64 [[TMP12]], 0
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP29:%.*]] = select i1 [[TMP28]], i32 [[TMP18]], i32 [[TMP27]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP30:%.*]] = icmp ne i64 [[TMP16]], 0
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP31:%.*]] = select i1 [[TMP30]], i32 [[TMP15]], i32 [[TMP29]]
+; NO_COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i128, ptr [[P]], align 8
+; NO_COMBINE_LOAD_PTR-NEXT: store i8 [[TMP25]], ptr @__dfsan_retval_tls, align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i32 [[TMP31]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_COMBINE_LOAD_PTR-NEXT: ret i128 [[A]]
+;
%a = load i128, ptr %p
ret i128 %a
}
define i17 @load17(ptr %p) {
- ; CHECK-LABEL: @load17.dfsan
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_LOAD_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#LABEL_ORIGIN:]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr %p, i64 3)
- ; CHECK-NEXT: %[[#LABEL_ORIGIN_H32:]] = lshr i64 %[[#LABEL_ORIGIN]], 32
- ; CHECK-NEXT: %[[#LABEL:]] = trunc i64 %[[#LABEL_ORIGIN_H32]] to i8
- ; CHECK-NEXT: %[[#ORIGIN:]] = trunc i64 %[[#LABEL_ORIGIN]] to i32
-
- ; COMBINE_LOAD_PTR-NEXT: %[[#LABEL:]] = or i8 %[[#LABEL]], %[[#PS]]
- ; COMBINE_LOAD_PTR-NEXT: %[[#NZ:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_LOAD_PTR-NEXT: %[[#ORIGIN:]] = select i1 %[[#NZ]], i32 %[[#PO]], i32 %[[#ORIGIN]]
-
- ; CHECK-NEXT: %a = load i17, ptr %p, align 4
- ; CHECK-NEXT: store i8 %[[#LABEL]], ptr @__dfsan_retval_tls, align [[ALIGN]]
- ; CHECK-NEXT: store i32 %[[#ORIGIN]], ptr @__dfsan_retval_origin_tls, align 4
-
+; COMBINE_LOAD_PTR-LABEL: define i17 @load17(
+; COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr [[P]], i64 3)
+; COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = lshr i64 [[TMP3]], 32
+; COMBINE_LOAD_PTR-NEXT: [[TMP5:%.*]] = trunc i64 [[TMP4]] to i8
+; COMBINE_LOAD_PTR-NEXT: [[TMP6:%.*]] = trunc i64 [[TMP3]] to i32
+; COMBINE_LOAD_PTR-NEXT: [[TMP7:%.*]] = or i8 [[TMP5]], [[TMP2]]
+; COMBINE_LOAD_PTR-NEXT: [[TMP8:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_LOAD_PTR-NEXT: [[TMP9:%.*]] = select i1 [[TMP8]], i32 [[TMP1]], i32 [[TMP6]]
+; COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i17, ptr [[P]], align 4
+; COMBINE_LOAD_PTR-NEXT: store i8 [[TMP7]], ptr @__dfsan_retval_tls, align 2
+; COMBINE_LOAD_PTR-NEXT: store i32 [[TMP9]], ptr @__dfsan_retval_origin_tls, align 4
+; COMBINE_LOAD_PTR-NEXT: ret i17 [[A]]
+;
+; NO_COMBINE_LOAD_PTR-LABEL: define i17 @load17(
+; NO_COMBINE_LOAD_PTR-SAME: ptr [[P:%.*]]) {
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP1:%.*]] = call zeroext i64 @__dfsan_load_label_and_origin(ptr [[P]], i64 3)
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP2:%.*]] = lshr i64 [[TMP1]], 32
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP3:%.*]] = trunc i64 [[TMP2]] to i8
+; NO_COMBINE_LOAD_PTR-NEXT: [[TMP4:%.*]] = trunc i64 [[TMP1]] to i32
+; NO_COMBINE_LOAD_PTR-NEXT: [[A:%.*]] = load i17, ptr [[P]], align 4
+; NO_COMBINE_LOAD_PTR-NEXT: store i8 [[TMP3]], ptr @__dfsan_retval_tls, align 2
+; NO_COMBINE_LOAD_PTR-NEXT: store i32 [[TMP4]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_COMBINE_LOAD_PTR-NEXT: ret i17 [[A]]
+;
%a = load i17, ptr %p, align 4
ret i17 %a
}
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
index 2839897684bfb..1eb32f4ed361a 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_select.ll
@@ -1,69 +1,110 @@
-; RUN: opt < %s -passes=dfsan -dfsan-track-select-control-flow=1 -dfsan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,TRACK_CONTROL_FLOW
-; RUN: opt < %s -passes=dfsan -dfsan-track-select-control-flow=0 -dfsan-track-origins=1 -S | FileCheck %s --check-prefixes=CHECK,NO_TRACK_CONTROL_FLOW
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=dfsan -dfsan-track-select-control-flow=1 -dfsan-track-origins=1 -dfsan-add-global-name-suffix=0 -S | FileCheck %s --check-prefixes=TRACK_CONTROL_FLOW
+; RUN: opt < %s -passes=dfsan -dfsan-track-select-control-flow=0 -dfsan-track-origins=1 -dfsan-add-global-name-suffix=0 -S | FileCheck %s --check-prefixes=NO_TRACK_CONTROL_FLOW
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
-; CHECK: @__dfsan_arg_tls = external thread_local(initialexec) global [[TLS_ARR:\[100 x i64\]]]
-; CHECK: @__dfsan_retval_tls = external thread_local(initialexec) global [[TLS_ARR]]
define i8 @select8(i1 %c, i8 %t, i8 %f) {
- ; TRACK_CONTROL_FLOW: @select8.dfsan
- ; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
- ; TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
- ; TRACK_CONTROL_FLOW: [[TFO:%.*]] = select i1 %c, i32 [[TO]], i32 [[FO]]
- ; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i8 [[CS]], 0
- ; TRACK_CONTROL_FLOW: [[CTFO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[TFO]]
- ; TRACK_CONTROL_FLOW: store i32 [[CTFO]], ptr @__dfsan_retval_origin_tls, align 4
-
- ; NO_TRACK_CONTROL_FLOW: @select8.dfsan
- ; NO_TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
- ; NO_TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; NO_TRACK_CONTROL_FLOW: [[TFO:%.*]] = select i1 %c, i32 [[TO]], i32 [[FO]]
- ; NO_TRACK_CONTROL_FLOW: store i32 [[TFO]], ptr @__dfsan_retval_origin_tls, align 4
-
+; TRACK_CONTROL_FLOW-LABEL: define i8 @select8(
+; TRACK_CONTROL_FLOW-SAME: i1 [[C:%.*]], i8 [[T:%.*]], i8 [[F:%.*]]) {
+; TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
+; TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; TRACK_CONTROL_FLOW-NEXT: [[TMP6:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; TRACK_CONTROL_FLOW-NEXT: [[TMP7:%.*]] = select i1 [[C]], i8 [[TMP5]], i8 [[TMP4]]
+; TRACK_CONTROL_FLOW-NEXT: [[TMP8:%.*]] = select i1 [[C]], i32 [[TMP3]], i32 [[TMP2]]
+; TRACK_CONTROL_FLOW-NEXT: [[TMP9:%.*]] = or i8 [[TMP6]], [[TMP7]]
+; TRACK_CONTROL_FLOW-NEXT: [[TMP10:%.*]] = icmp ne i8 [[TMP6]], 0
+; TRACK_CONTROL_FLOW-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i32 [[TMP1]], i32 [[TMP8]]
+; TRACK_CONTROL_FLOW-NEXT: [[A:%.*]] = select i1 [[C]], i8 [[T]], i8 [[F]]
+; TRACK_CONTROL_FLOW-NEXT: store i8 [[TMP9]], ptr @__dfsan_retval_tls, align 2
+; TRACK_CONTROL_FLOW-NEXT: store i32 [[TMP11]], ptr @__dfsan_retval_origin_tls, align 4
+; TRACK_CONTROL_FLOW-NEXT: ret i8 [[A]]
+;
+; NO_TRACK_CONTROL_FLOW-LABEL: define i8 @select8(
+; NO_TRACK_CONTROL_FLOW-SAME: i1 [[C:%.*]], i8 [[T:%.*]], i8 [[F:%.*]]) {
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP6:%.*]] = select i1 [[C]], i8 [[TMP4]], i8 [[TMP3]]
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP7:%.*]] = select i1 [[C]], i32 [[TMP2]], i32 [[TMP1]]
+; NO_TRACK_CONTROL_FLOW-NEXT: [[A:%.*]] = select i1 [[C]], i8 [[T]], i8 [[F]]
+; NO_TRACK_CONTROL_FLOW-NEXT: store i8 [[TMP6]], ptr @__dfsan_retval_tls, align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: store i32 [[TMP7]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: ret i8 [[A]]
+;
%a = select i1 %c, i8 %t, i8 %f
ret i8 %a
}
define i8 @select8e(i1 %c, i8 %tf) {
- ; TRACK_CONTROL_FLOW: @select8e.dfsan
- ; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; TRACK_CONTROL_FLOW: [[TFO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
- ; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i8 [[CS]], 0
- ; TRACK_CONTROL_FLOW: [[CTFO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[TFO]]
- ; TRACK_CONTROL_FLOW: store i32 [[CTFO]], ptr @__dfsan_retval_origin_tls, align 4
-
- ; NO_TRACK_CONTROL_FLOW: @select8e.dfsan
- ; NO_TRACK_CONTROL_FLOW: [[TFO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; NO_TRACK_CONTROL_FLOW: store i32 [[TFO]], ptr @__dfsan_retval_origin_tls, align 4
-
-%a = select i1 %c, i8 %tf, i8 %tf
+; TRACK_CONTROL_FLOW-LABEL: define i8 @select8e(
+; TRACK_CONTROL_FLOW-SAME: i1 [[C:%.*]], i8 [[TF:%.*]]) {
+; TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP3]]
+; TRACK_CONTROL_FLOW-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP4]], 0
+; TRACK_CONTROL_FLOW-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP1]], i32 [[TMP2]]
+; TRACK_CONTROL_FLOW-NEXT: [[A:%.*]] = select i1 [[C]], i8 [[TF]], i8 [[TF]]
+; TRACK_CONTROL_FLOW-NEXT: store i8 [[TMP5]], ptr @__dfsan_retval_tls, align 2
+; TRACK_CONTROL_FLOW-NEXT: store i32 [[TMP7]], ptr @__dfsan_retval_origin_tls, align 4
+; TRACK_CONTROL_FLOW-NEXT: ret i8 [[A]]
+;
+; NO_TRACK_CONTROL_FLOW-LABEL: define i8 @select8e(
+; NO_TRACK_CONTROL_FLOW-SAME: i1 [[C:%.*]], i8 [[TF:%.*]]) {
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: [[A:%.*]] = select i1 [[C]], i8 [[TF]], i8 [[TF]]
+; NO_TRACK_CONTROL_FLOW-NEXT: store i8 [[TMP2]], ptr @__dfsan_retval_tls, align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: store i32 [[TMP1]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: ret i8 [[A]]
+;
+ %a = select i1 %c, i8 %tf, i8 %tf
ret i8 %a
}
define <4 x i8> @select8v(<4 x i1> %c, <4 x i8> %t, <4 x i8> %f) {
- ; TRACK_CONTROL_FLOW: @select8v.dfsan
- ; TRACK_CONTROL_FLOW: [[CO:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
- ; TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; TRACK_CONTROL_FLOW: [[FS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
- ; TRACK_CONTROL_FLOW: [[CS:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
- ; TRACK_CONTROL_FLOW: [[FS_NE:%.*]] = icmp ne i8 [[FS]], 0
- ; TRACK_CONTROL_FLOW: [[FTO:%.*]] = select i1 [[FS_NE]], i32 [[FO]], i32 [[TO]]
- ; TRACK_CONTROL_FLOW: [[CS_NE:%.*]] = icmp ne i8 [[CS]], 0
- ; TRACK_CONTROL_FLOW: [[CFTO:%.*]] = select i1 [[CS_NE]], i32 [[CO]], i32 [[FTO]]
- ; TRACK_CONTROL_FLOW: store i32 [[CFTO]], ptr @__dfsan_retval_origin_tls, align 4
-
- ; NO_TRACK_CONTROL_FLOW: @select8v.dfsan
- ; NO_TRACK_CONTROL_FLOW: [[FO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
- ; NO_TRACK_CONTROL_FLOW: [[TO:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; NO_TRACK_CONTROL_FLOW: [[FS:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
- ; NO_TRACK_CONTROL_FLOW: [[FS_NE:%.*]] = icmp ne i8 [[FS]], 0
- ; NO_TRACK_CONTROL_FLOW: [[FTO:%.*]] = select i1 [[FS_NE]], i32 [[FO]], i32 [[TO]]
- ; NO_TRACK_CONTROL_FLOW: store i32 [[FTO]], ptr @__dfsan_retval_origin_tls, align 4
-
+; TRACK_CONTROL_FLOW-LABEL: define <4 x i8> @select8v(
+; TRACK_CONTROL_FLOW-SAME: <4 x i1> [[C:%.*]], <4 x i8> [[T:%.*]], <4 x i8> [[F:%.*]]) {
+; TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
+; TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; TRACK_CONTROL_FLOW-NEXT: [[TMP6:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; TRACK_CONTROL_FLOW-NEXT: [[TMP7:%.*]] = or i8 [[TMP5]], [[TMP4]]
+; TRACK_CONTROL_FLOW-NEXT: [[TMP8:%.*]] = or i8 [[TMP6]], [[TMP7]]
+; TRACK_CONTROL_FLOW-NEXT: [[TMP9:%.*]] = icmp ne i8 [[TMP4]], 0
+; TRACK_CONTROL_FLOW-NEXT: [[TMP10:%.*]] = select i1 [[TMP9]], i32 [[TMP2]], i32 [[TMP3]]
+; TRACK_CONTROL_FLOW-NEXT: [[TMP11:%.*]] = icmp ne i8 [[TMP6]], 0
+; TRACK_CONTROL_FLOW-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i32 [[TMP1]], i32 [[TMP10]]
+; TRACK_CONTROL_FLOW-NEXT: [[A:%.*]] = select <4 x i1> [[C]], <4 x i8> [[T]], <4 x i8> [[F]]
+; TRACK_CONTROL_FLOW-NEXT: store i8 [[TMP8]], ptr @__dfsan_retval_tls, align 2
+; TRACK_CONTROL_FLOW-NEXT: store i32 [[TMP12]], ptr @__dfsan_retval_origin_tls, align 4
+; TRACK_CONTROL_FLOW-NEXT: ret <4 x i8> [[A]]
+;
+; NO_TRACK_CONTROL_FLOW-LABEL: define <4 x i8> @select8v(
+; NO_TRACK_CONTROL_FLOW-SAME: <4 x i1> [[C:%.*]], <4 x i8> [[T:%.*]], <4 x i8> [[F:%.*]]) {
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 2), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP2:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP3:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 4), align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP5:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP6:%.*]] = or i8 [[TMP4]], [[TMP3]]
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP7:%.*]] = icmp ne i8 [[TMP3]], 0
+; NO_TRACK_CONTROL_FLOW-NEXT: [[TMP8:%.*]] = select i1 [[TMP7]], i32 [[TMP1]], i32 [[TMP2]]
+; NO_TRACK_CONTROL_FLOW-NEXT: [[A:%.*]] = select <4 x i1> [[C]], <4 x i8> [[T]], <4 x i8> [[F]]
+; NO_TRACK_CONTROL_FLOW-NEXT: store i8 [[TMP6]], ptr @__dfsan_retval_tls, align 2
+; NO_TRACK_CONTROL_FLOW-NEXT: store i32 [[TMP8]], ptr @__dfsan_retval_origin_tls, align 4
+; NO_TRACK_CONTROL_FLOW-NEXT: ret <4 x i8> [[A]]
+;
%a = select <4 x i1> %c, <4 x i8> %t, <4 x i8> %f
ret <4 x i8> %a
}
diff --git a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
index 55b0a012a32af..8f54408b5e831 100644
--- a/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
+++ b/llvm/test/Instrumentation/DataFlowSanitizer/origin_store.ll
@@ -1,28 +1,36 @@
-; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -S | FileCheck %s
-; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-combine-pointer-labels-on-store -S | FileCheck %s --check-prefixes=CHECK,COMBINE_STORE_PTR
+; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 6
+; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-add-global-name-suffix=0 -S | FileCheck %s --check-prefixes=CHECK,NO_COMBINE_STORE_PTR
+; RUN: opt < %s -passes=dfsan -dfsan-track-origins=1 -dfsan-combine-pointer-labels-on-store -dfsan-add-global-name-suffix=0 -S | FileCheck %s --check-prefixes=CHECK,COMBINE_STORE_PTR
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128"
target triple = "x86_64-unknown-linux-gnu"
define void @store_zero_to_non_escaped_alloca() {
- ; CHECK-LABEL: @store_zero_to_non_escaped_alloca.dfsan
- ; CHECK-NEXT: [[A:%.*]] = alloca i8, align 1
- ; CHECK-NEXT: %_dfsa = alloca i32, align 4
- ; CHECK-NEXT: %p = alloca i16, align 2
- ; CHECK-NEXT: store i8 0, ptr [[A]], align 1
- ; CHECK-NEXT: store i16 1, ptr %p, align 2
- ; CHECK-NEXT: ret void
-
+; CHECK-LABEL: define void @store_zero_to_non_escaped_alloca() {
+; CHECK-NEXT: [[TMP1:%.*]] = alloca i8, align 1
+; CHECK-NEXT: [[_DFSA:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[P:%.*]] = alloca i16, align 2
+; CHECK-NEXT: store i8 0, ptr [[TMP1]], align 1
+; CHECK-NEXT: store i16 1, ptr [[P]], align 2
+; CHECK-NEXT: ret void
+;
%p = alloca i16
store i16 1, ptr %p
ret void
}
define void @store_nonzero_to_non_escaped_alloca(i16 %a) {
- ; CHECK-LABEL: @store_nonzero_to_non_escaped_alloca.dfsan
- ; CHECK: %[[#AO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; CHECK: %_dfsa = alloca i32, align 4
- ; CHECK: store i32 %[[#AO]], ptr %_dfsa, align 4
-
+; CHECK-LABEL: define void @store_nonzero_to_non_escaped_alloca(
+; CHECK-SAME: i16 [[A:%.*]]) {
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; CHECK-NEXT: [[TMP3:%.*]] = alloca i8, align 1
+; CHECK-NEXT: [[_DFSA:%.*]] = alloca i32, align 4
+; CHECK-NEXT: [[P:%.*]] = alloca i16, align 2
+; CHECK-NEXT: store i8 [[TMP2]], ptr [[TMP3]], align 1
+; CHECK-NEXT: store i32 [[TMP1]], ptr [[_DFSA]], align 4
+; CHECK-NEXT: store i16 [[A]], ptr [[P]], align 2
+; CHECK-NEXT: ret void
+;
%p = alloca i16
store i16 %a, ptr %p
ret void
@@ -31,12 +39,17 @@ define void @store_nonzero_to_non_escaped_alloca(i16 %a) {
declare void @foo(ptr %p)
define void @store_zero_to_escaped_alloca() {
- ; CHECK-LABEL: @store_zero_to_escaped_alloca.dfsan
- ; CHECK: store i16 0, ptr {{.*}}, align 1
- ; CHECK-NEXT: store i16 1, ptr %p, align 2
- ; CHECK-NEXT: store i8 0, ptr @__dfsan_arg_tls, align [[ALIGN:2]]
- ; CHECK-NEXT: call void @foo.dfsan(ptr %p)
-
+; CHECK-LABEL: define void @store_zero_to_escaped_alloca() {
+; CHECK-NEXT: [[P:%.*]] = alloca i16, align 2
+; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[P]] to i64
+; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080
+; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr
+; CHECK-NEXT: store i16 0, ptr [[TMP3]], align 1
+; CHECK-NEXT: store i16 1, ptr [[P]], align 2
+; CHECK-NEXT: store i8 0, ptr @__dfsan_arg_tls, align 2
+; CHECK-NEXT: call void @foo(ptr [[P]])
+; CHECK-NEXT: ret void
+;
%p = alloca i16
store i16 1, ptr %p
call void @foo(ptr %p)
@@ -44,24 +57,33 @@ define void @store_zero_to_escaped_alloca() {
}
define void @store_nonzero_to_escaped_alloca(i16 %a) {
- ; CHECK-LABEL: @store_nonzero_to_escaped_alloca.dfsan
- ; CHECK-NEXT: %[[#AO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; CHECK-NEXT: %[[#AS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
- ; CHECK: %[[#INTP:]] = ptrtoint ptr %p to i64
- ; CHECK-NEXT: %[[#SHADOW_OFFSET:]] = xor i64 %[[#INTP]], [[#%.10d,MASK:]]
- ; CHECK-NEXT: %[[#SHADOW_PTR0:]] = inttoptr i64 %[[#SHADOW_OFFSET]] to ptr
- ; CHECK-NEXT: %[[#ORIGIN_OFFSET:]] = add i64 %[[#SHADOW_OFFSET]], [[#%.10d,ORIGIN_BASE:]]
- ; CHECK-NEXT: %[[#ORIGIN_ADDR:]] = and i64 %[[#ORIGIN_OFFSET]], -4
- ; CHECK-NEXT: %[[#ORIGIN_PTR:]] = inttoptr i64 %[[#ORIGIN_ADDR]] to ptr
- ; CHECK: %_dfscmp = icmp ne i8 %[[#AS]], 0
- ; CHECK-NEXT: br i1 %_dfscmp, label %[[L1:.*]], label %[[L2:.*]],
- ; CHECK: [[L1]]:
- ; CHECK-NEXT: %[[#NO:]] = call i32 @__dfsan_chain_origin(i32 %[[#AO]])
- ; CHECK-NEXT: store i32 %[[#NO]], ptr %[[#ORIGIN_PTR]], align 4
- ; CHECK-NEXT: br label %[[L2]]
- ; CHECK: [[L2]]:
- ; CHECK-NEXT: store i16 %a, ptr %p, align 2
-
+; CHECK-LABEL: define void @store_nonzero_to_escaped_alloca(
+; CHECK-SAME: i16 [[A:%.*]]) {
+; CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; CHECK-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; CHECK-NEXT: [[P:%.*]] = alloca i16, align 2
+; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -4
+; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
+; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP5]], i32 0
+; CHECK-NEXT: store i8 [[TMP2]], ptr [[TMP9]], align 1
+; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP5]], i32 1
+; CHECK-NEXT: store i8 [[TMP2]], ptr [[TMP10]], align 1
+; CHECK-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP2]], 0
+; CHECK-NEXT: br i1 [[_DFSCMP]], label %[[BB11:.*]], label %[[BB13:.*]], !prof [[PROF1:![0-9]+]]
+; CHECK: [[BB11]]:
+; CHECK-NEXT: [[TMP12:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP1]])
+; CHECK-NEXT: store i32 [[TMP12]], ptr [[TMP8]], align 4
+; CHECK-NEXT: br label %[[BB13]]
+; CHECK: [[BB13]]:
+; CHECK-NEXT: store i16 [[A]], ptr [[P]], align 2
+; CHECK-NEXT: store i8 0, ptr @__dfsan_arg_tls, align 2
+; CHECK-NEXT: call void @foo(ptr [[P]])
+; CHECK-NEXT: ret void
+;
%p = alloca i16
store i16 %a, ptr %p
call void @foo(ptr %p)
@@ -69,87 +91,248 @@ define void @store_nonzero_to_escaped_alloca(i16 %a) {
}
define void @store64_align8(ptr %p, i64 %a) {
- ; CHECK-LABEL: @store64_align8.dfsan
-
- ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#AO:]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; CHECK-NEXT: %[[#AS:]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align [[ALIGN]]
-
- ; COMBINE_STORE_PTR-NEXT: %[[#AS:]] = or i8 %[[#AS]], %[[#PS]]
- ; COMBINE_STORE_PTR-NEXT: %[[#NE:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_STORE_PTR-NEXT: %[[#AO:]] = select i1 %[[#NE]], i32 %[[#PO]], i32 %[[#AO]]
-
- ; CHECK: %_dfscmp = icmp ne i8 %[[#AS]], 0
- ; CHECK-NEXT: br i1 %_dfscmp, label %[[L1:.*]], label %[[L2:.*]],
- ; CHECK: [[L1]]:
- ; CHECK-NEXT: %[[#NO:]] = call i32 @__dfsan_chain_origin(i32 %[[#AO]])
- ; CHECK-NEXT: %[[#NO_ZEXT:]] = zext i32 %[[#NO]] to i64
- ; CHECK-NEXT: %[[#NO_SHL:]] = shl i64 %[[#NO_ZEXT]], 32
- ; CHECK-NEXT: %[[#NO2:]] = or i64 %[[#NO_ZEXT]], %[[#NO_SHL]]
- ; CHECK-NEXT: store i64 %[[#NO2]], ptr {{.*}}, align 8
- ; CHECK-NEXT: br label %[[L2]]
- ; CHECK: [[L2]]:
- ; CHECK-NEXT: store i64 %a, ptr %p, align 8
-
+; NO_COMBINE_STORE_PTR-LABEL: define void @store64_align8(
+; NO_COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i64 [[A:%.*]]) {
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP8:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i32 0
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP8]], i8 [[TMP2]], i32 1
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP10:%.*]] = insertelement <8 x i8> [[TMP9]], i8 [[TMP2]], i32 2
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP11:%.*]] = insertelement <8 x i8> [[TMP10]], i8 [[TMP2]], i32 3
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP12:%.*]] = insertelement <8 x i8> [[TMP11]], i8 [[TMP2]], i32 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP13:%.*]] = insertelement <8 x i8> [[TMP12]], i8 [[TMP2]], i32 5
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP14:%.*]] = insertelement <8 x i8> [[TMP13]], i8 [[TMP2]], i32 6
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> [[TMP14]], i8 [[TMP2]], i32 7
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP16:%.*]] = getelementptr <8 x i8>, ptr [[TMP5]], i32 0
+; NO_COMBINE_STORE_PTR-NEXT: store <8 x i8> [[TMP15]], ptr [[TMP16]], align 1
+; NO_COMBINE_STORE_PTR-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP2]], 0
+; NO_COMBINE_STORE_PTR-NEXT: br i1 [[_DFSCMP]], label %[[BB17:.*]], label %[[BB22:.*]], !prof [[PROF1]]
+; NO_COMBINE_STORE_PTR: [[BB17]]:
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP18:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP1]])
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP19:%.*]] = zext i32 [[TMP18]] to i64
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP20:%.*]] = shl i64 [[TMP19]], 32
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP21:%.*]] = or i64 [[TMP19]], [[TMP20]]
+; NO_COMBINE_STORE_PTR-NEXT: store i64 [[TMP21]], ptr [[TMP7]], align 8
+; NO_COMBINE_STORE_PTR-NEXT: br label %[[BB22]]
+; NO_COMBINE_STORE_PTR: [[BB22]]:
+; NO_COMBINE_STORE_PTR-NEXT: store i64 [[A]], ptr [[P]], align 8
+; NO_COMBINE_STORE_PTR-NEXT: ret void
+;
+; COMBINE_STORE_PTR-LABEL: define void @store64_align8(
+; COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i64 [[A:%.*]]) {
+; COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP2]]
+; COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_STORE_PTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP1]], i32 [[TMP3]]
+; COMBINE_STORE_PTR-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
+; COMBINE_STORE_PTR-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 87960930222080
+; COMBINE_STORE_PTR-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr
+; COMBINE_STORE_PTR-NEXT: [[TMP11:%.*]] = add i64 [[TMP9]], 17592186044416
+; COMBINE_STORE_PTR-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr
+; COMBINE_STORE_PTR-NEXT: [[TMP13:%.*]] = insertelement <8 x i8> poison, i8 [[TMP5]], i32 0
+; COMBINE_STORE_PTR-NEXT: [[TMP14:%.*]] = insertelement <8 x i8> [[TMP13]], i8 [[TMP5]], i32 1
+; COMBINE_STORE_PTR-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> [[TMP14]], i8 [[TMP5]], i32 2
+; COMBINE_STORE_PTR-NEXT: [[TMP16:%.*]] = insertelement <8 x i8> [[TMP15]], i8 [[TMP5]], i32 3
+; COMBINE_STORE_PTR-NEXT: [[TMP17:%.*]] = insertelement <8 x i8> [[TMP16]], i8 [[TMP5]], i32 4
+; COMBINE_STORE_PTR-NEXT: [[TMP18:%.*]] = insertelement <8 x i8> [[TMP17]], i8 [[TMP5]], i32 5
+; COMBINE_STORE_PTR-NEXT: [[TMP19:%.*]] = insertelement <8 x i8> [[TMP18]], i8 [[TMP5]], i32 6
+; COMBINE_STORE_PTR-NEXT: [[TMP20:%.*]] = insertelement <8 x i8> [[TMP19]], i8 [[TMP5]], i32 7
+; COMBINE_STORE_PTR-NEXT: [[TMP21:%.*]] = getelementptr <8 x i8>, ptr [[TMP10]], i32 0
+; COMBINE_STORE_PTR-NEXT: store <8 x i8> [[TMP20]], ptr [[TMP21]], align 1
+; COMBINE_STORE_PTR-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP5]], 0
+; COMBINE_STORE_PTR-NEXT: br i1 [[_DFSCMP]], label %[[BB22:.*]], label %[[BB27:.*]], !prof [[PROF1]]
+; COMBINE_STORE_PTR: [[BB22]]:
+; COMBINE_STORE_PTR-NEXT: [[TMP23:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP7]])
+; COMBINE_STORE_PTR-NEXT: [[TMP24:%.*]] = zext i32 [[TMP23]] to i64
+; COMBINE_STORE_PTR-NEXT: [[TMP25:%.*]] = shl i64 [[TMP24]], 32
+; COMBINE_STORE_PTR-NEXT: [[TMP26:%.*]] = or i64 [[TMP24]], [[TMP25]]
+; COMBINE_STORE_PTR-NEXT: store i64 [[TMP26]], ptr [[TMP12]], align 8
+; COMBINE_STORE_PTR-NEXT: br label %[[BB27]]
+; COMBINE_STORE_PTR: [[BB27]]:
+; COMBINE_STORE_PTR-NEXT: store i64 [[A]], ptr [[P]], align 8
+; COMBINE_STORE_PTR-NEXT: ret void
+;
store i64 %a, ptr %p
ret void
}
define void @store64_align2(ptr %p, i64 %a) {
- ; CHECK-LABEL: @store64_align2.dfsan
-
- ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#AO:]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; CHECK-NEXT: %[[#AS:]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align [[ALIGN]]
-
- ; COMBINE_STORE_PTR-NEXT: %[[#AS:]] = or i8 %[[#AS]], %[[#PS]]
- ; COMBINE_STORE_PTR-NEXT: %[[#NE:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_STORE_PTR-NEXT: %[[#AO:]] = select i1 %[[#NE]], i32 %[[#PO]], i32 %[[#AO]]
-
- ; CHECK: %_dfscmp = icmp ne i8 %[[#AS]], 0
- ; CHECK-NEXT: br i1 %_dfscmp, label %[[L1:.*]], label %[[L2:.*]],
- ; CHECK: [[L1]]:
- ; CHECK-NEXT: %[[#NO:]] = call i32 @__dfsan_chain_origin(i32 %[[#AO]])
- ; CHECK-NEXT: store i32 %[[#NO]], ptr %[[#O_PTR0:]], align 4
- ; CHECK-NEXT: %[[#O_PTR1:]] = getelementptr i32, ptr %[[#O_PTR0]], i32 1
- ; CHECK-NEXT: store i32 %[[#NO]], ptr %[[#O_PTR1]], align 4
- ; CHECK: [[L2]]:
- ; CHECK-NEXT: store i64 %a, ptr %p, align 2
-
+; NO_COMBINE_STORE_PTR-LABEL: define void @store64_align2(
+; NO_COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i64 [[A:%.*]]) {
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP7:%.*]] = and i64 [[TMP6]], -4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i32 0
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP10:%.*]] = insertelement <8 x i8> [[TMP9]], i8 [[TMP2]], i32 1
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP11:%.*]] = insertelement <8 x i8> [[TMP10]], i8 [[TMP2]], i32 2
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP12:%.*]] = insertelement <8 x i8> [[TMP11]], i8 [[TMP2]], i32 3
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP13:%.*]] = insertelement <8 x i8> [[TMP12]], i8 [[TMP2]], i32 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP14:%.*]] = insertelement <8 x i8> [[TMP13]], i8 [[TMP2]], i32 5
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> [[TMP14]], i8 [[TMP2]], i32 6
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP16:%.*]] = insertelement <8 x i8> [[TMP15]], i8 [[TMP2]], i32 7
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP17:%.*]] = getelementptr <8 x i8>, ptr [[TMP5]], i32 0
+; NO_COMBINE_STORE_PTR-NEXT: store <8 x i8> [[TMP16]], ptr [[TMP17]], align 1
+; NO_COMBINE_STORE_PTR-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP2]], 0
+; NO_COMBINE_STORE_PTR-NEXT: br i1 [[_DFSCMP]], label %[[BB18:.*]], label %[[BB21:.*]], !prof [[PROF1]]
+; NO_COMBINE_STORE_PTR: [[BB18]]:
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP19:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP1]])
+; NO_COMBINE_STORE_PTR-NEXT: store i32 [[TMP19]], ptr [[TMP8]], align 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[TMP8]], i32 1
+; NO_COMBINE_STORE_PTR-NEXT: store i32 [[TMP19]], ptr [[TMP20]], align 4
+; NO_COMBINE_STORE_PTR-NEXT: br label %[[BB21]]
+; NO_COMBINE_STORE_PTR: [[BB21]]:
+; NO_COMBINE_STORE_PTR-NEXT: store i64 [[A]], ptr [[P]], align 2
+; NO_COMBINE_STORE_PTR-NEXT: ret void
+;
+; COMBINE_STORE_PTR-LABEL: define void @store64_align2(
+; COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i64 [[A:%.*]]) {
+; COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP2]]
+; COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_STORE_PTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP1]], i32 [[TMP3]]
+; COMBINE_STORE_PTR-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
+; COMBINE_STORE_PTR-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 87960930222080
+; COMBINE_STORE_PTR-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr
+; COMBINE_STORE_PTR-NEXT: [[TMP11:%.*]] = add i64 [[TMP9]], 17592186044416
+; COMBINE_STORE_PTR-NEXT: [[TMP12:%.*]] = and i64 [[TMP11]], -4
+; COMBINE_STORE_PTR-NEXT: [[TMP13:%.*]] = inttoptr i64 [[TMP12]] to ptr
+; COMBINE_STORE_PTR-NEXT: [[TMP14:%.*]] = insertelement <8 x i8> poison, i8 [[TMP5]], i32 0
+; COMBINE_STORE_PTR-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> [[TMP14]], i8 [[TMP5]], i32 1
+; COMBINE_STORE_PTR-NEXT: [[TMP16:%.*]] = insertelement <8 x i8> [[TMP15]], i8 [[TMP5]], i32 2
+; COMBINE_STORE_PTR-NEXT: [[TMP17:%.*]] = insertelement <8 x i8> [[TMP16]], i8 [[TMP5]], i32 3
+; COMBINE_STORE_PTR-NEXT: [[TMP18:%.*]] = insertelement <8 x i8> [[TMP17]], i8 [[TMP5]], i32 4
+; COMBINE_STORE_PTR-NEXT: [[TMP19:%.*]] = insertelement <8 x i8> [[TMP18]], i8 [[TMP5]], i32 5
+; COMBINE_STORE_PTR-NEXT: [[TMP20:%.*]] = insertelement <8 x i8> [[TMP19]], i8 [[TMP5]], i32 6
+; COMBINE_STORE_PTR-NEXT: [[TMP21:%.*]] = insertelement <8 x i8> [[TMP20]], i8 [[TMP5]], i32 7
+; COMBINE_STORE_PTR-NEXT: [[TMP22:%.*]] = getelementptr <8 x i8>, ptr [[TMP10]], i32 0
+; COMBINE_STORE_PTR-NEXT: store <8 x i8> [[TMP21]], ptr [[TMP22]], align 1
+; COMBINE_STORE_PTR-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP5]], 0
+; COMBINE_STORE_PTR-NEXT: br i1 [[_DFSCMP]], label %[[BB23:.*]], label %[[BB26:.*]], !prof [[PROF1]]
+; COMBINE_STORE_PTR: [[BB23]]:
+; COMBINE_STORE_PTR-NEXT: [[TMP24:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP7]])
+; COMBINE_STORE_PTR-NEXT: store i32 [[TMP24]], ptr [[TMP13]], align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[TMP13]], i32 1
+; COMBINE_STORE_PTR-NEXT: store i32 [[TMP24]], ptr [[TMP25]], align 4
+; COMBINE_STORE_PTR-NEXT: br label %[[BB26]]
+; COMBINE_STORE_PTR: [[BB26]]:
+; COMBINE_STORE_PTR-NEXT: store i64 [[A]], ptr [[P]], align 2
+; COMBINE_STORE_PTR-NEXT: ret void
+;
store i64 %a, ptr %p, align 2
ret void
}
define void @store96_align8(ptr %p, i96 %a) {
- ; CHECK-LABEL: @store96_align8.dfsan
-
- ; COMBINE_STORE_PTR-NEXT: %[[#PO:]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
- ; COMBINE_STORE_PTR-NEXT: %[[#PS:]] = load i8, ptr @__dfsan_arg_tls, align [[ALIGN]]
-
- ; CHECK-NEXT: %[[#AO:]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
- ; CHECK-NEXT: %[[#AS:]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align [[ALIGN]]
-
- ; COMBINE_STORE_PTR-NEXT: %[[#AS:]] = or i8 %[[#AS]], %[[#PS]]
- ; COMBINE_STORE_PTR-NEXT: %[[#NE:]] = icmp ne i8 %[[#PS]], 0
- ; COMBINE_STORE_PTR-NEXT: %[[#AO:]] = select i1 %[[#NE]], i32 %[[#PO]], i32 %[[#AO]]
-
- ; CHECK: %_dfscmp = icmp ne i8 %[[#AS]], 0
- ; CHECK-NEXT: br i1 %_dfscmp, label %[[L1:.*]], label %[[L2:.*]],
- ; CHECK: [[L1]]:
- ; CHECK-NEXT: %[[#NO:]] = call i32 @__dfsan_chain_origin(i32 %[[#AO]])
- ; CHECK-NEXT: %[[#NO_ZEXT:]] = zext i32 %[[#NO]] to i64
- ; CHECK-NEXT: %[[#NO_SHL:]] = shl i64 %[[#NO_ZEXT]], 32
- ; CHECK-NEXT: %[[#NO2:]] = or i64 %[[#NO_ZEXT]], %[[#NO_SHL]]
- ; CHECK-NEXT: store i64 %[[#NO2]], ptr %[[#O_PTR0:]], align 8
- ; CHECK-NEXT: %[[#O_PTR1:]] = getelementptr i32, ptr %[[#O_PTR0]], i32 2
- ; CHECK-NEXT: store i32 %[[#NO]], ptr %[[#O_PTR1]], align 8
- ; CHECK: [[L2]]:
- ; CHECK-NEXT: store i96 %a, ptr %p, align 8
-
+; NO_COMBINE_STORE_PTR-LABEL: define void @store96_align8(
+; NO_COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i96 [[A:%.*]]) {
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[P]] to i64
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = add i64 [[TMP4]], 17592186044416
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP8:%.*]] = insertelement <8 x i8> poison, i8 [[TMP2]], i32 0
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP9:%.*]] = insertelement <8 x i8> [[TMP8]], i8 [[TMP2]], i32 1
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP10:%.*]] = insertelement <8 x i8> [[TMP9]], i8 [[TMP2]], i32 2
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP11:%.*]] = insertelement <8 x i8> [[TMP10]], i8 [[TMP2]], i32 3
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP12:%.*]] = insertelement <8 x i8> [[TMP11]], i8 [[TMP2]], i32 4
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP13:%.*]] = insertelement <8 x i8> [[TMP12]], i8 [[TMP2]], i32 5
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP14:%.*]] = insertelement <8 x i8> [[TMP13]], i8 [[TMP2]], i32 6
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> [[TMP14]], i8 [[TMP2]], i32 7
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP16:%.*]] = getelementptr <8 x i8>, ptr [[TMP5]], i32 0
+; NO_COMBINE_STORE_PTR-NEXT: store <8 x i8> [[TMP15]], ptr [[TMP16]], align 1
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[TMP5]], i32 8
+; NO_COMBINE_STORE_PTR-NEXT: store i8 [[TMP2]], ptr [[TMP17]], align 1
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[TMP5]], i32 9
+; NO_COMBINE_STORE_PTR-NEXT: store i8 [[TMP2]], ptr [[TMP18]], align 1
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP5]], i32 10
+; NO_COMBINE_STORE_PTR-NEXT: store i8 [[TMP2]], ptr [[TMP19]], align 1
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP5]], i32 11
+; NO_COMBINE_STORE_PTR-NEXT: store i8 [[TMP2]], ptr [[TMP20]], align 1
+; NO_COMBINE_STORE_PTR-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP2]], 0
+; NO_COMBINE_STORE_PTR-NEXT: br i1 [[_DFSCMP]], label %[[BB21:.*]], label %[[BB27:.*]], !prof [[PROF1]]
+; NO_COMBINE_STORE_PTR: [[BB21]]:
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP22:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP1]])
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP23:%.*]] = zext i32 [[TMP22]] to i64
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP24:%.*]] = shl i64 [[TMP23]], 32
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP25:%.*]] = or i64 [[TMP23]], [[TMP24]]
+; NO_COMBINE_STORE_PTR-NEXT: store i64 [[TMP25]], ptr [[TMP7]], align 8
+; NO_COMBINE_STORE_PTR-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[TMP7]], i32 2
+; NO_COMBINE_STORE_PTR-NEXT: store i32 [[TMP22]], ptr [[TMP26]], align 8
+; NO_COMBINE_STORE_PTR-NEXT: br label %[[BB27]]
+; NO_COMBINE_STORE_PTR: [[BB27]]:
+; NO_COMBINE_STORE_PTR-NEXT: store i96 [[A]], ptr [[P]], align 8
+; NO_COMBINE_STORE_PTR-NEXT: ret void
+;
+; COMBINE_STORE_PTR-LABEL: define void @store96_align8(
+; COMBINE_STORE_PTR-SAME: ptr [[P:%.*]], i96 [[A:%.*]]) {
+; COMBINE_STORE_PTR-NEXT: [[TMP1:%.*]] = load i32, ptr @__dfsan_arg_origin_tls, align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP2:%.*]] = load i8, ptr @__dfsan_arg_tls, align 2
+; COMBINE_STORE_PTR-NEXT: [[TMP3:%.*]] = load i32, ptr getelementptr inbounds ([200 x i32], ptr @__dfsan_arg_origin_tls, i64 0, i64 1), align 4
+; COMBINE_STORE_PTR-NEXT: [[TMP4:%.*]] = load i8, ptr getelementptr (i8, ptr @__dfsan_arg_tls, i64 2), align 2
+; COMBINE_STORE_PTR-NEXT: [[TMP5:%.*]] = or i8 [[TMP4]], [[TMP2]]
+; COMBINE_STORE_PTR-NEXT: [[TMP6:%.*]] = icmp ne i8 [[TMP2]], 0
+; COMBINE_STORE_PTR-NEXT: [[TMP7:%.*]] = select i1 [[TMP6]], i32 [[TMP1]], i32 [[TMP3]]
+; COMBINE_STORE_PTR-NEXT: [[TMP8:%.*]] = ptrtoint ptr [[P]] to i64
+; COMBINE_STORE_PTR-NEXT: [[TMP9:%.*]] = xor i64 [[TMP8]], 87960930222080
+; COMBINE_STORE_PTR-NEXT: [[TMP10:%.*]] = inttoptr i64 [[TMP9]] to ptr
+; COMBINE_STORE_PTR-NEXT: [[TMP11:%.*]] = add i64 [[TMP9]], 17592186044416
+; COMBINE_STORE_PTR-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr
+; COMBINE_STORE_PTR-NEXT: [[TMP13:%.*]] = insertelement <8 x i8> poison, i8 [[TMP5]], i32 0
+; COMBINE_STORE_PTR-NEXT: [[TMP14:%.*]] = insertelement <8 x i8> [[TMP13]], i8 [[TMP5]], i32 1
+; COMBINE_STORE_PTR-NEXT: [[TMP15:%.*]] = insertelement <8 x i8> [[TMP14]], i8 [[TMP5]], i32 2
+; COMBINE_STORE_PTR-NEXT: [[TMP16:%.*]] = insertelement <8 x i8> [[TMP15]], i8 [[TMP5]], i32 3
+; COMBINE_STORE_PTR-NEXT: [[TMP17:%.*]] = insertelement <8 x i8> [[TMP16]], i8 [[TMP5]], i32 4
+; COMBINE_STORE_PTR-NEXT: [[TMP18:%.*]] = insertelement <8 x i8> [[TMP17]], i8 [[TMP5]], i32 5
+; COMBINE_STORE_PTR-NEXT: [[TMP19:%.*]] = insertelement <8 x i8> [[TMP18]], i8 [[TMP5]], i32 6
+; COMBINE_STORE_PTR-NEXT: [[TMP20:%.*]] = insertelement <8 x i8> [[TMP19]], i8 [[TMP5]], i32 7
+; COMBINE_STORE_PTR-NEXT: [[TMP21:%.*]] = getelementptr <8 x i8>, ptr [[TMP10]], i32 0
+; COMBINE_STORE_PTR-NEXT: store <8 x i8> [[TMP20]], ptr [[TMP21]], align 1
+; COMBINE_STORE_PTR-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[TMP10]], i32 8
+; COMBINE_STORE_PTR-NEXT: store i8 [[TMP5]], ptr [[TMP22]], align 1
+; COMBINE_STORE_PTR-NEXT: [[TMP23:%.*]] = getelementptr i8, ptr [[TMP10]], i32 9
+; COMBINE_STORE_PTR-NEXT: store i8 [[TMP5]], ptr [[TMP23]], align 1
+; COMBINE_STORE_PTR-NEXT: [[TMP24:%.*]] = getelementptr i8, ptr [[TMP10]], i32 10
+; COMBINE_STORE_PTR-NEXT: store i8 [[TMP5]], ptr [[TMP24]], align 1
+; COMBINE_STORE_PTR-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP10]], i32 11
+; COMBINE_STORE_PTR-NEXT: store i8 [[TMP5]], ptr [[TMP25]], align 1
+; COMBINE_STORE_PTR-NEXT: [[_DFSCMP:%.*]] = icmp ne i8 [[TMP5]], 0
+; COMBINE_STORE_PTR-NEXT: br i1 [[_DFSCMP]], label %[[BB26:.*]], label %[[BB32:.*]], !prof [[PROF1]]
+; COMBINE_STORE_PTR: [[BB26]]:
+; COMBINE_STORE_PTR-NEXT: [[TMP27:%.*]] = call i32 @__dfsan_chain_origin(i32 [[TMP7]])
+; COMBINE_STORE_PTR-NEXT: [[TMP28:%.*]] = zext i32 [[TMP27]] to i64
+; COMBINE_STORE_PTR-NEXT: [[TMP29:%.*]] = shl i64 [[TMP28]], 32
+; COMBINE_STORE_PTR-NEXT: [[TMP30:%.*]] = or i64 [[TMP28]], [[TMP29]]
+; COMBINE_STORE_PTR-NEXT: store i64 [[TMP30]], ptr [[TMP12]], align 8
+; COMBINE_STORE_PTR-NEXT: [[TMP31:%.*]] = getelementptr i32, ptr [[TMP12]], i32 2
+; COMBINE_STORE_PTR-NEXT: store i32 [[TMP27]], ptr [[TMP31]], align 8
+; COMBINE_STORE_PTR-NEXT: br label %[[BB32]]
+; COMBINE_STORE_PTR: [[BB32]]:
+; COMBINE_STORE_PTR-NEXT: store i96 [[A]], ptr [[P]], align 8
+; COMBINE_STORE_PTR-NEXT: ret void
+;
store i96 %a, ptr %p, align 8
ret void
}
+;.
+; NO_COMBINE_STORE_PTR: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}
+;.
+; COMBINE_STORE_PTR: [[PROF1]] = !{!"branch_weights", i32 1, i32 1048575}
+;.
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