[llvm] 41165fd - [DAG] SimplifyMultipleUseDemandedBits - simplify ISD::SCALAR_TO_VECTOR to ISD::POISON if we don't demand 0th element (#225530)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 02:21:24 PDT 2026
Author: Simon Pilgrim
Date: 2026-09-25T09:21:16Z
New Revision: 41165fd5d503b4297cb1033fdeb1688ce0863b68
URL: https://github.com/llvm/llvm-project/commit/41165fd5d503b4297cb1033fdeb1688ce0863b68
DIFF: https://github.com/llvm/llvm-project/commit/41165fd5d503b4297cb1033fdeb1688ce0863b68.diff
LOG: [DAG] SimplifyMultipleUseDemandedBits - simplify ISD::SCALAR_TO_VECTOR to ISD::POISON if we don't demand 0th element (#225530)
Equivalent fold to SimplifyDemandedBits/SimplifyDemandedVectorElts
Fixes a number of minor regressions from #217185
Added:
Modified:
llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
llvm/test/CodeGen/X86/bfloat.ll
llvm/test/CodeGen/X86/dag-topological-sort.ll
llvm/test/CodeGen/X86/load-partial-dot-product.ll
Removed:
################################################################################
diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 7c97dfb2c806a..f5402812659fe 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -822,6 +822,11 @@ SDValue TargetLowering::SimplifyMultipleUseDemandedBits(
break;
}
+ case ISD::SCALAR_TO_VECTOR: {
+ if (!VT.isScalableVector() && !DemandedElts[0])
+ return DAG.getPOISON(VT);
+ break;
+ }
case ISD::AND: {
LHSKnown = DAG.computeKnownBits(Op.getOperand(0), DemandedElts, Depth + 1);
RHSKnown = DAG.computeKnownBits(Op.getOperand(1), DemandedElts, Depth + 1);
diff --git a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
index abeb42213466b..908d1061a3962 100644
--- a/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
+++ b/llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll
@@ -1852,7 +1852,7 @@ define amdgpu_kernel void @load_v7i8_to_v7f32(ptr addrspace(1) noalias %out, ptr
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v2, vcc, 5, v0
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v1, vcc
-; VI-NEXT: v_add_u32_e32 v4, vcc, 4, v0
+; VI-NEXT: v_add_u32_e32 v4, vcc, 6, v0
; VI-NEXT: v_addc_u32_e32 v5, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v6, vcc, 1, v0
; VI-NEXT: v_addc_u32_e32 v7, vcc, 0, v1, vcc
@@ -1860,36 +1860,31 @@ define amdgpu_kernel void @load_v7i8_to_v7f32(ptr addrspace(1) noalias %out, ptr
; VI-NEXT: v_addc_u32_e32 v9, vcc, 0, v1, vcc
; VI-NEXT: v_add_u32_e32 v10, vcc, 3, v0
; VI-NEXT: v_addc_u32_e32 v11, vcc, 0, v1, vcc
-; VI-NEXT: v_add_u32_e32 v12, vcc, 6, v0
-; VI-NEXT: v_addc_u32_e32 v13, vcc, 0, v1, vcc
-; VI-NEXT: flat_load_ubyte v2, v[2:3]
-; VI-NEXT: flat_load_ubyte v4, v[4:5]
-; VI-NEXT: flat_load_ubyte v5, v[6:7]
-; VI-NEXT: flat_load_ubyte v7, v[8:9]
+; VI-NEXT: flat_load_ubyte v12, v[2:3]
+; VI-NEXT: flat_load_ubyte v2, v[8:9]
; VI-NEXT: flat_load_ubyte v3, v[10:11]
-; VI-NEXT: flat_load_ubyte v6, v[12:13]
-; VI-NEXT: flat_load_ubyte v0, v[0:1]
-; VI-NEXT: v_mov_b32_e32 v8, 0x3020504
+; VI-NEXT: flat_load_ubyte v4, v[4:5]
+; VI-NEXT: flat_load_ubyte v5, v[0:1]
+; VI-NEXT: flat_load_ubyte v6, v[6:7]
+; VI-NEXT: v_add_u32_e32 v0, vcc, 4, v0
+; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
+; VI-NEXT: flat_load_ubyte v7, v[0:1]
; VI-NEXT: s_mov_b32 s3, 0xf000
; VI-NEXT: s_mov_b32 s2, -1
-; VI-NEXT: s_waitcnt vmcnt(6)
-; VI-NEXT: v_lshlrev_b32_e32 v9, 8, v2
; VI-NEXT: s_waitcnt vmcnt(5)
-; VI-NEXT: v_or_b32_e32 v4, v9, v4
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v2
; VI-NEXT: s_waitcnt vmcnt(4)
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v5
-; VI-NEXT: s_waitcnt vmcnt(3)
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v2, v7
-; VI-NEXT: s_waitcnt vmcnt(2)
; VI-NEXT: v_cvt_f32_ubyte0_e32 v3, v3
-; VI-NEXT: v_perm_b32 v4, v4, s0, v8
+; VI-NEXT: s_waitcnt vmcnt(2)
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v5
+; VI-NEXT: s_waitcnt vmcnt(1)
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v1, v6
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v6, v4
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v5, v12
; VI-NEXT: s_waitcnt vmcnt(0)
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v6, v6
-; VI-NEXT: v_cvt_f32_ubyte1_e32 v5, v4
-; VI-NEXT: v_cvt_f32_ubyte0_e32 v4, v4
-; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
+; VI-NEXT: v_cvt_f32_ubyte0_e32 v4, v7
; VI-NEXT: buffer_store_dwordx3 v[4:6], off, s[0:3], 0 offset:16
+; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; VI-NEXT: s_endpgm
;
; GFX10-LABEL: load_v7i8_to_v7f32:
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
index 43a776703f4b9..86dfc6f37680e 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3bf16.v2bf16.ll
@@ -23,7 +23,6 @@ define void @v_shuffle_v3bf16_v2bf16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX900-NEXT: global_store_dword v0, v1, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -35,7 +34,6 @@ define void @v_shuffle_v3bf16_v2bf16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX90A-NEXT: global_store_dword v0, v1, s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -47,7 +45,6 @@ define void @v_shuffle_v3bf16_v2bf16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_short v0, v0, s[0:1] offset:4
; GFX942-NEXT: global_store_dword v0, v1, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1416,7 +1413,6 @@ define void @v_shuffle_v3bf16_v2bf16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX900-NEXT: global_store_dword v0, v1, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1428,7 +1424,6 @@ define void @v_shuffle_v3bf16_v2bf16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX90A-NEXT: global_store_dword v0, v1, s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1440,7 +1435,6 @@ define void @v_shuffle_v3bf16_v2bf16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_short v0, v0, s[0:1] offset:4
; GFX942-NEXT: global_store_dword v0, v1, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
index 5967eedc20ebd..6aa9657fd06f3 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3f16.v2f16.ll
@@ -23,7 +23,6 @@ define void @v_shuffle_v3f16_v2f16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX900-NEXT: global_store_dword v0, v1, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -35,7 +34,6 @@ define void @v_shuffle_v3f16_v2f16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX90A-NEXT: global_store_dword v0, v1, s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -47,7 +45,6 @@ define void @v_shuffle_v3f16_v2f16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_short v0, v0, s[0:1] offset:4
; GFX942-NEXT: global_store_dword v0, v1, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1416,7 +1413,6 @@ define void @v_shuffle_v3f16_v2f16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX900-NEXT: global_store_dword v0, v1, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1428,7 +1424,6 @@ define void @v_shuffle_v3f16_v2f16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX90A-NEXT: global_store_dword v0, v1, s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1440,7 +1435,6 @@ define void @v_shuffle_v3f16_v2f16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_short v0, v0, s[0:1] offset:4
; GFX942-NEXT: global_store_dword v0, v1, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
index 25ccbdd52c92c..bcfe492695da6 100644
--- a/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
+++ b/llvm/test/CodeGen/AMDGPU/shufflevector.v3i16.v2i16.ll
@@ -23,7 +23,6 @@ define void @v_shuffle_v3i16_v2i16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX900-NEXT: global_store_dword v0, v1, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -35,7 +34,6 @@ define void @v_shuffle_v3i16_v2i16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX90A-NEXT: global_store_dword v0, v1, s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -47,7 +45,6 @@ define void @v_shuffle_v3i16_v2i16__0_u_u(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_short v0, v0, s[0:1] offset:4
; GFX942-NEXT: global_store_dword v0, v1, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
@@ -1409,7 +1406,6 @@ define void @v_shuffle_v3i16_v2i16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX900-NEXT: ;;#ASMSTART
; GFX900-NEXT: ; def v1
; GFX900-NEXT: ;;#ASMEND
-; GFX900-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX900-NEXT: global_store_dword v0, v1, s[16:17]
; GFX900-NEXT: s_waitcnt vmcnt(0)
; GFX900-NEXT: s_setpc_b64 s[30:31]
@@ -1421,7 +1417,6 @@ define void @v_shuffle_v3i16_v2i16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX90A-NEXT: ;;#ASMSTART
; GFX90A-NEXT: ; def v1
; GFX90A-NEXT: ;;#ASMEND
-; GFX90A-NEXT: global_store_short v0, v0, s[16:17] offset:4
; GFX90A-NEXT: global_store_dword v0, v1, s[16:17]
; GFX90A-NEXT: s_waitcnt vmcnt(0)
; GFX90A-NEXT: s_setpc_b64 s[30:31]
@@ -1433,7 +1428,6 @@ define void @v_shuffle_v3i16_v2i16__0_2_2(ptr addrspace(1) inreg %ptr) {
; GFX942-NEXT: ;;#ASMSTART
; GFX942-NEXT: ; def v1
; GFX942-NEXT: ;;#ASMEND
-; GFX942-NEXT: global_store_short v0, v0, s[0:1] offset:4
; GFX942-NEXT: global_store_dword v0, v1, s[0:1]
; GFX942-NEXT: s_waitcnt vmcnt(0)
; GFX942-NEXT: s_setpc_b64 s[30:31]
diff --git a/llvm/test/CodeGen/X86/bfloat.ll b/llvm/test/CodeGen/X86/bfloat.ll
index 1d5e65afec89c..4a234a5e80608 100644
--- a/llvm/test/CodeGen/X86/bfloat.ll
+++ b/llvm/test/CodeGen/X86/bfloat.ll
@@ -2006,8 +2006,6 @@ define void @PR92471(ptr %0, ptr %1) nounwind {
; SSE2-NEXT: movq {{.*#+}} xmm0 = mem[0],zero
; SSE2-NEXT: movd {{.*#+}} xmm1 = mem[0],zero,zero,zero
; SSE2-NEXT: pinsrw $2, 12(%rdi), %xmm1
-; SSE2-NEXT: pextrw $7, %xmm0, %eax
-; SSE2-NEXT: pinsrw $3, %eax, %xmm1
; SSE2-NEXT: pxor %xmm2, %xmm2
; SSE2-NEXT: pxor %xmm3, %xmm3
; SSE2-NEXT: punpcklwd {{.*#+}} xmm3 = xmm3[0],xmm1[0],xmm3[1],xmm1[1],xmm3[2],xmm1[2],xmm3[3],xmm1[3]
diff --git a/llvm/test/CodeGen/X86/dag-topological-sort.ll b/llvm/test/CodeGen/X86/dag-topological-sort.ll
index 8686ae12037eb..e9c55e276fc96 100644
--- a/llvm/test/CodeGen/X86/dag-topological-sort.ll
+++ b/llvm/test/CodeGen/X86/dag-topological-sort.ll
@@ -50,7 +50,6 @@ define <4 x float> @load_float4_float3_as_float2_float(ptr nocapture readonly de
; TOPOLOGICAL: # %bb.0:
; TOPOLOGICAL-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
; TOPOLOGICAL-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; TOPOLOGICAL-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
; TOPOLOGICAL-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
; TOPOLOGICAL-NEXT: retq
%2 = load <2 x float>, ptr %0, align 4
diff --git a/llvm/test/CodeGen/X86/load-partial-dot-product.ll b/llvm/test/CodeGen/X86/load-partial-dot-product.ll
index e74e7012942c1..711ab45c7df26 100644
--- a/llvm/test/CodeGen/X86/load-partial-dot-product.ll
+++ b/llvm/test/CodeGen/X86/load-partial-dot-product.ll
@@ -126,37 +126,33 @@ define float @dot3_float4_as_float3(ptr dereferenceable(16) %a0, ptr dereference
define float @dot3_float3(ptr dereferenceable(16) %a0, ptr dereferenceable(16) %a1) {
; SSE2-LABEL: dot3_float3:
; SSE2: # %bb.0:
-; SSE2-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSE2-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
-; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSE2-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
-; SSE2-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
-; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
-; SSE2-NEXT: mulps %xmm0, %xmm1
-; SSE2-NEXT: movaps %xmm1, %xmm0
-; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[1,1]
-; SSE2-NEXT: addss %xmm1, %xmm0
-; SSE2-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; SSE2-NEXT: addss %xmm1, %xmm0
+; SSE2-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
+; SSE2-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSE2-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
+; SSE2-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[0,2]
+; SSE2-NEXT: mulps %xmm1, %xmm2
+; SSE2-NEXT: movaps %xmm2, %xmm0
+; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm2[1,1]
+; SSE2-NEXT: addss %xmm2, %xmm0
+; SSE2-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
+; SSE2-NEXT: addss %xmm2, %xmm0
; SSE2-NEXT: retq
;
; SSSE3-LABEL: dot3_float3:
; SSSE3: # %bb.0:
-; SSSE3-NEXT: movsd {{.*#+}} xmm0 = mem[0],zero
-; SSSE3-NEXT: movss {{.*#+}} xmm1 = mem[0],zero,zero,zero
-; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,0],xmm0[3,0]
-; SSSE3-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[0,2]
+; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
; SSSE3-NEXT: movsd {{.*#+}} xmm1 = mem[0],zero
-; SSSE3-NEXT: movss {{.*#+}} xmm2 = mem[0],zero,zero,zero
-; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,0],xmm1[3,0]
-; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm2[0,2]
-; SSSE3-NEXT: mulps %xmm0, %xmm1
-; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm1[1,1,3,3]
-; SSSE3-NEXT: addss %xmm1, %xmm0
-; SSSE3-NEXT: movhlps {{.*#+}} xmm1 = xmm1[1,1]
-; SSSE3-NEXT: addss %xmm1, %xmm0
+; SSSE3-NEXT: shufps {{.*#+}} xmm1 = xmm1[0,1],xmm0[0,2]
+; SSSE3-NEXT: movss {{.*#+}} xmm0 = mem[0],zero,zero,zero
+; SSSE3-NEXT: movsd {{.*#+}} xmm2 = mem[0],zero
+; SSSE3-NEXT: shufps {{.*#+}} xmm2 = xmm2[0,1],xmm0[0,2]
+; SSSE3-NEXT: mulps %xmm1, %xmm2
+; SSSE3-NEXT: movshdup {{.*#+}} xmm0 = xmm2[1,1,3,3]
+; SSSE3-NEXT: addss %xmm2, %xmm0
+; SSSE3-NEXT: movhlps {{.*#+}} xmm2 = xmm2[1,1]
+; SSSE3-NEXT: addss %xmm2, %xmm0
; SSSE3-NEXT: retq
;
; SSE41-LABEL: dot3_float3:
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