[llvm] 74c5a64 - [RISCV] Remove getMaxLMULForFixedLengthVectors. NFC (#226111)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 01:35:18 PDT 2026
Author: Luke Lau
Date: 2026-09-25T09:34:57+01:00
New Revision: 74c5a6421b6bb260ef09e6d5f941970ae55629ce
URL: https://github.com/llvm/llvm-project/commit/74c5a6421b6bb260ef09e6d5f941970ae55629ce
DIFF: https://github.com/llvm/llvm-project/commit/74c5a6421b6bb260ef09e6d5f941970ae55629ce.diff
LOG: [RISCV] Remove getMaxLMULForFixedLengthVectors. NFC (#226111)
The value can no longer be overridden after
https://github.com/llvm/llvm-project/pull/207312. Now there's nothing
specific about it to fixed vectors, so just inline it.
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.cpp
llvm/lib/Target/RISCV/RISCVSubtarget.h
llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 6f757ffb4a67e..c1618f79bd83d 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -3392,7 +3392,7 @@ static bool useRVVForFixedLengthVectorVT(MVT VT,
unsigned LMul = divideCeil(VT.getSizeInBits(), MinVLen);
// Don't use RVV for types that don't fit.
- if (LMul > Subtarget.getMaxLMULForFixedLengthVectors())
+ if (LMul > 8)
return false;
// TODO: Perhaps an artificial restriction, but worth having whilst getting
@@ -20519,9 +20519,7 @@ combineVectorSizedSetCCEquality(EVT VT, SDValue X, SDValue Y, ISD::CondCode CC,
unsigned OpSize = OpVT.getSizeInBits();
// The size should be larger than XLen and smaller than the maximum vector
// size.
- if (OpSize <= Subtarget.getXLen() ||
- OpSize > Subtarget.getRealMinVLen() *
- Subtarget.getMaxLMULForFixedLengthVectors())
+ if (OpSize <= Subtarget.getXLen() || OpSize > Subtarget.getRealMinVLen() * 8)
return SDValue();
// Don't perform this combine if constructing the vector will be expensive.
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
index 02e9f1f412ab3..747e10152ddf6 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.cpp
@@ -261,12 +261,6 @@ unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
return RVVVectorBitsMin;
}
-unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
- assert(hasVInstructions() &&
- "Tried to get vector length without Zve or V extension support!");
- return 8;
-}
-
bool RISCVSubtarget::useRVVForFixedLengthVectors() const {
return hasVInstructions() &&
getMinRVVVectorSizeInBits() >= RISCV::RVVBitsPerBlock;
diff --git a/llvm/lib/Target/RISCV/RISCVSubtarget.h b/llvm/lib/Target/RISCV/RISCVSubtarget.h
index fcb4ea2b6635b..759de71827a77 100644
--- a/llvm/lib/Target/RISCV/RISCVSubtarget.h
+++ b/llvm/lib/Target/RISCV/RISCVSubtarget.h
@@ -390,7 +390,6 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo {
unsigned getMispredictionPenalty() const override;
unsigned getLoadLatency() const override;
- unsigned getMaxLMULForFixedLengthVectors() const;
bool useRVVForFixedLengthVectors() const;
bool enableSubRegLiveness() const override;
diff --git a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
index e1e12943d6742..f2d5eb2dc53a0 100644
--- a/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
+++ b/llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp
@@ -3770,7 +3770,7 @@ RISCVTTIImpl::enableMemCmpExpansion(bool OptSize, bool IsZeroCmp) const {
// The minimum size should be `XLen / 8 + 1`, and the maxinum size should be
// `VLenB * MaxLMUL` so that it fits in a single register group.
unsigned MinSize = ST->getXLen() / 8 + 1;
- unsigned MaxSize = VLenB * ST->getMaxLMULForFixedLengthVectors();
+ unsigned MaxSize = VLenB * 8;
for (unsigned Size = MinSize; Size <= MaxSize; Size++)
Options.LoadSizes.insert(Options.LoadSizes.begin(), Size);
}
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