[llvm] f131c8c - [AMDGPU] Use CFG in LIRP tests (#226260)
via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 01:32:45 PDT 2026
Author: ilia-cher
Date: 2026-09-25T09:32:34+01:00
New Revision: f131c8c21397e19c439070070348c17cc3ca2112
URL: https://github.com/llvm/llvm-project/commit/f131c8c21397e19c439070070348c17cc3ca2112
DIFF: https://github.com/llvm/llvm-project/commit/f131c8c21397e19c439070070348c17cc3ca2112.diff
LOG: [AMDGPU] Use CFG in LIRP tests (#226260)
LIRP tests (llvm/test/CodeGen/AMDGPU/lirp.mir) use live intervals with
gaps and redefinitions.
With added -verify-machineinstrs, current test examples trigger machine
code check failure ("Multiple connected components in live interval").
This PR updates the tests to use CFG (loops with loop-carried vregs)
similar to the real world use cases, to fix the verification, and also
simplifies the tests a bit (using implifit defs and kills).
Test:
```
ninja -C build
ninja -C build check-llvm
./build/bin/llvm-lit -v llvm/test/CodeGen/AMDGPU/lirp.mir
```
Added:
Modified:
llvm/test/CodeGen/AMDGPU/lirp.mir
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/lirp.mir b/llvm/test/CodeGen/AMDGPU/lirp.mir
index 5879546b5c451..4fb70160d69c6 100644
--- a/llvm/test/CodeGen/AMDGPU/lirp.mir
+++ b/llvm/test/CodeGen/AMDGPU/lirp.mir
@@ -1,11 +1,11 @@
-# RUN: llc -mtriple=amdgpu12.50 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -amdgpu-lirp-reschedule=true -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
-# RUN: llc -mtriple=amdgpu12.50 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -amdgpu-lirp-reschedule=false -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s --check-prefix=DISABLE
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -amdgpu-lirp-reschedule=true -verify-misched -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s
+# RUN: llc -mtriple=amdgpu12.50 -run-pass=machine-scheduler -amdgpu-sched-strategy=coexec -amdgpu-lirp-reschedule=false -verify-misched -debug-only=machine-scheduler %s -o - 2>&1 | FileCheck %s --check-prefix=DISABLE
# REQUIRES: asserts
# Test that the live interval pressure reschedule stage runs and detects a gap in pressure estimates:
#
# CHECK: Starting scheduling stage: Live Interval RP Reschedule
-# CHECK: LIRP: Region 0,{{.*}}InstantRP=2, LIRP=3
+# CHECK: LIRP: Region {{[0-9]+}},{{.*}}InstantRP=2, LIRP=3
# DISABLE-NOT: LIRP:
--- |
define void @lirp_estimate_test() { ret void }
@@ -20,58 +20,57 @@ tracksRegLiveness: true
isSSA: false
body: |
bb.0:
- liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3
- ; A (%0) has two segments with a gap
- ; B (%1) overlaps A seg1
- ; C (%2) overlaps A seg2
- ; B and C overlap in the gap
+ successors: %bb.1
+ %0:vgpr_32 = IMPLICIT_DEF ; A def (seg1)
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.1, %bb.2
+ ; A (%0) is live-in, used and redefined (seg2) below.
+ ; B (%1) overlaps A seg1, C (%2) overlaps A seg2.
+ ; B and C overlap in the gap.
;
; InstantRP: max 2 at any point
- ; LIRP: 3 because A, B, C all interfere with each other
+ ; LIRP: 3 (A, B, C interfere with each other)
+ %1:vgpr_32 = IMPLICIT_DEF ; B def
+ KILL %0 ; A dies (seg1)
+ %2:vgpr_32 = IMPLICIT_DEF ; C def
+ KILL %1 ; B dies
+ %0:vgpr_32 = IMPLICIT_DEF ; A redef (seg2)
+ KILL %2 ; C dies
+ S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+ S_BRANCH %bb.2
- %0:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec ; A seg1
- %1:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec ; B def
- BUFFER_STORE_DWORD_OFFEN %0, $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, implicit $exec ; use A (seg1 ends)
- ; gap in A
- %2:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, implicit $exec ; C def (B and C overlap)
- BUFFER_STORE_DWORD_OFFEN %1, $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, implicit $exec ; use B (dies)
- ; end of gap
- %0:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 20, 0, 0, implicit $exec ; A seg2
- BUFFER_STORE_DWORD_OFFEN %0, $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 24, 0, 0, implicit $exec ; use A (seg2 dies)
- BUFFER_STORE_DWORD_OFFEN %2, $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 28, 0, 0, implicit $exec ; use C (dies)
+ bb.2:
S_ENDPGM 0
...
-# CHECK: LIRP: Region 0,{{.*}}InstantRP=1, LIRP=1
+# CHECK: LIRP: Region {{[0-9]+}},{{.*}}InstantRP=1, LIRP=1
---
name: lirp_slot_reuse_test
tracksRegLiveness: true
isSSA: false
body: |
bb.0:
- liveins: $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3
; %0 and %1 have disjoint live ranges, so RA can reuse the same slot.
; InstantRP: max 1
; LIRP: 1
-
- %0:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 0, 0, 0, implicit $exec
- BUFFER_STORE_DWORD_OFFEN %0, $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec ; %0 dies
- %1:vgpr_32 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, implicit $exec
- BUFFER_STORE_DWORD_OFFEN %1, $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, implicit $exec ; %1 dies
+ %0:vgpr_32 = IMPLICIT_DEF
+ KILL %0 ; %0 dies
+ %1:vgpr_32 = IMPLICIT_DEF
+ KILL %1 ; %1 dies
S_ENDPGM 0
...
# Test that the stage changes the schedule:
#
# CHECK-LABEL: name: lirp_reschedule
-# CHECK: %13:vreg_256_align2 = IMPLICIT_DEF
-# Free baseline pressure registers:
-# CHECK-NEXT: KILL %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13
-# CHECK-NEXT: %14:vreg_512_align2 = IMPLICIT_DEF
+# CHECK: KILL %14
+# CHECK-NEXT: %15:vreg_512_align2 = IMPLICIT_DEF
#
# DISABLE-LABEL: name: lirp_reschedule
-# DISABLE: %13:vreg_256_align2 = IMPLICIT_DEF
-# DISABLE-NEXT: %14:vreg_512_align2 = IMPLICIT_DEF
+# DISABLE: %15:vreg_512_align2 = IMPLICIT_DEF
+# DISABLE-NEXT: KILL %14
---
name: lirp_reschedule
tracksRegLiveness: true
@@ -80,7 +79,8 @@ machineFunctionInfo:
occupancy: 4
body: |
bb.0:
- ; 216 VGPRs of baseline pressure, live across the whole region.
+ successors: %bb.1
+ ; 216 VGPRs of baseline pressure, live across the loop.
%0:vreg_512_align2 = IMPLICIT_DEF
%1:vreg_512_align2 = IMPLICIT_DEF
%2:vreg_512_align2 = IMPLICIT_DEF
@@ -96,16 +96,23 @@ body: |
%12:vreg_512_align2 = IMPLICIT_DEF
%13:vreg_256_align2 = IMPLICIT_DEF
- ; Redefinition-gap:
- ; %14, %15 and %16 pairwise interfere, only two are live at once.
%14:vreg_512_align2 = IMPLICIT_DEF
+ S_BRANCH %bb.1
+
+ bb.1:
+ successors: %bb.1, %bb.2
+ ; %14, %15 and %16 pairwise interfere, only two are live at once.
+ ; %14 is live-in, used and redefined below.
%15:vreg_512_align2 = IMPLICIT_DEF
KILL %14
%16:vreg_512_align2 = IMPLICIT_DEF
KILL %15
%14:vreg_512_align2 = IMPLICIT_DEF
- KILL %14, %16
+ KILL %16
+ S_CBRANCH_SCC1 %bb.1, implicit undef $scc
+ S_BRANCH %bb.2
- KILL %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13
+ bb.2:
+ KILL %0, %1, %2, %3, %4, %5, %6, %7, %8, %9, %10, %11, %12, %13, %14
S_ENDPGM 0
...
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