[llvm] [TableGen] Assign LaneBitmask bits in a less surprising order (PR #225809)
Jay Foad via llvm-commits
llvm-commits at lists.llvm.org
Fri Sep 25 00:55:30 PDT 2026
https://github.com/jayfoad updated https://github.com/llvm/llvm-project/pull/225809
>From 355df09b4b36cbb3184699c57037a59c8e8f5b6d Mon Sep 17 00:00:00 2001
From: Jay Foad <jay.foad at amd.com>
Date: Fri, 28 Aug 2026 11:49:46 +0100
Subject: [PATCH] [TableGen] Assign LaneBitmask bits in a less surprising order
TableGen assigned LaneBitmask bits in alphabetical order of subreg idx
names, which made for surprising assignments like:
sub0_lo16 0b0010
sub0_hi16 0b0001
sub1_lo16 0b1000
sub1_hi16 0b0100
Assigning them in order in which the subreg idxs were declared gives a
more natural order (or lets you choose a more natural order by editting
the td file) like:
sub0_lo16 0b0001
sub0_hi16 0b0010
sub1_lo16 0b0100
sub1_hi16 0b1000
According to discussion on #218644 this can affect the way that
DetectDeadLanes handles illegal REG_SEQUENCE instructions whose operand
widths do not match the width of the corresponding subreg. This seems to
be the cause of the cascading codegen diffs in
test/CodeGen/AMDGPU/frem.ll.
AArch64 needed patching to reject coalescing to the SVE register class
QQ when SVE support is disabled. Without this
test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll failed with:
llc: lib/Target/AArch64/AArch64InstrInfo.cpp:6549: virtual void llvm::AArch64InstrInfo::storeRegToStackSlot(MachineBasicBlock &, MachineBasicBlock::iterator, Register, bool, int, const TargetRegisterClass *, Register, MachineInstr::MIFlag) const: Assertion `Subtarget.isSVEorStreamingSVEAvailable() && "Unexpected register store without SVE store instructions"' failed.
---
.../Target/AArch64/AArch64RegisterInfo.cpp | 24 +
llvm/lib/Target/AMDGPU/SIFoldOperands.cpp | 14 +-
llvm/lib/Target/Hexagon/HexagonBitTracker.cpp | 4 +-
.../AArch64/arm64-neon-vector-list-spill.ll | 95 +-
.../CodeGen/AArch64/interleaved-accesses.ll | 38 +-
...gister-coalesce-update-subranges-remat.mir | 12 +-
llvm/test/CodeGen/AArch64/vldn_shuffle.ll | 92 +-
.../inst-select-extract-vector-elt.mir | 4 +-
.../inst-select-insert-vector-elt.mir | 24 +-
.../branch-folding-implicit-def-subreg.ll | 4 +-
llvm/test/CodeGen/AMDGPU/frem.ll | 2592 ++++++++++-------
.../AMDGPU/indirect-addressing-term.ll | 2 +-
.../Hexagon/livephysregs-lane-masks.mir | 4 +-
.../CodeGen/Hexagon/regalloc-bad-undef.mir | 4 +-
.../Hexagon/verify-liveness-at-def.mir | 6 +-
.../test/CodeGen/PowerPC/subreg-lanemasks.mir | 10 +-
llvm/test/TableGen/ArtificialSubregs.td | 60 +-
llvm/test/TableGen/ConcatenatedSubregs.td | 14 +-
.../GlobalISelEmitter/nested-subregs.td | 2 +-
llvm/test/TableGen/SubRegsAndAliases.td | 6 +-
llvm/test/TableGen/dag-isel-subregs.td | 2 +-
.../Inputs/amdgpu_isel.ll.expected | 10 +-
.../TableGen/Common/CodeGenRegisters.cpp | 10 +-
23 files changed, 1776 insertions(+), 1257 deletions(-)
diff --git a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
index 7f22038c206b79..cc820865d43b6b 100644
--- a/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
+++ b/llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp
@@ -1449,6 +1449,21 @@ unsigned AArch64RegisterInfo::getLocalAddressRegister(
return getFrameRegister(MF);
}
+/// Return true if \p RC is one of the SVE register classes that can only be
+/// spilled and reloaded using SVE instructions. This must be kept in sync with
+/// the classes handled by AArch64InstrInfo::storeRegToStackSlot() and
+/// loadRegFromStackSlot().
+static bool isSVERegClass(const TargetRegisterClass *RC) {
+ return AArch64::ZPRRegClass.hasSubClassEq(RC) ||
+ AArch64::ZPR2RegClass.hasSubClassEq(RC) ||
+ AArch64::ZPR3RegClass.hasSubClassEq(RC) ||
+ AArch64::ZPR4RegClass.hasSubClassEq(RC) ||
+ AArch64::ZPR2StridedOrContiguousRegClass.hasSubClassEq(RC) ||
+ AArch64::ZPR4StridedOrContiguousRegClass.hasSubClassEq(RC) ||
+ AArch64::PPRRegClass.hasSubClassEq(RC) ||
+ AArch64::PPR2RegClass.hasSubClassEq(RC);
+}
+
/// SrcRC and DstRC will be morphed into NewRC if this returns true
bool AArch64RegisterInfo::shouldCoalesce(
MachineInstr *MI, const TargetRegisterClass *SrcRC, unsigned SubReg,
@@ -1457,6 +1472,15 @@ bool AArch64RegisterInfo::shouldCoalesce(
MachineFunction &MF = *MI->getMF();
MachineRegisterInfo &MRI = MF.getRegInfo();
+ // The SVE Z register tuples overlap the NEON Q and D tuples, so both ZPR2 and
+ // QQ (for example) are valid answers when the coalescer asks for a register
+ // class covering a pair of D registers. If it picks an SVE class on a
+ // subtarget without SVE then the register allocator has no way to spill or
+ // reload the result, so reject the coalesce and leave the copy alone.
+ if (NewRC && isSVERegClass(NewRC) &&
+ !MF.getSubtarget<AArch64Subtarget>().isSVEorStreamingSVEAvailable())
+ return false;
+
if (MI->isSubregToReg() && MRI.subRegLivenessEnabled() &&
!MF.getSubtarget<AArch64Subtarget>().enableSRLTSubregToRegMitigation())
return false;
diff --git a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
index 23d9610f4295e1..0c96ec2e87cddf 100644
--- a/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
+++ b/llvm/lib/Target/AMDGPU/SIFoldOperands.cpp
@@ -1514,21 +1514,21 @@ bool SIFoldOperandsImpl::foldOperand(
//
// Excerpt from AMDGPUGenRegisterInfoEnums.inc
// NoSubRegister, //0
- // hi16, // 1
- // lo16, // 2
+ // lo16, // 1
+ // hi16, // 2
// sub0, // 3
+ // sub1, // 4
// ...
- // sub1, // 11
- // sub1_hi16, // 12
- // sub1_lo16, // 13
- static_assert(AMDGPU::sub1_hi16 == 12, "Subregister layout has changed");
+ // sub1_lo16, // 35
+ // sub1_hi16, // 36
+ static_assert(AMDGPU::sub1_hi16 == 36, "Subregister layout has changed");
if (Size == 2 && TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) &&
TRI->isSGPRReg(*MRI, UseReg)) {
// Produce the 32 bit subregister index to which the 16-bit subregister
// is aligned.
if (SubRegIdx > AMDGPU::sub1) {
LaneBitmask M = TRI->getSubRegIndexLaneMask(SubRegIdx);
- M |= M.getLane(M.getHighestLane() - 1);
+ M |= M.getLane(M.getHighestLane() + 1);
SmallVector<unsigned, 4> Indexes;
TRI->getCoveringSubRegIndexes(TRI->getRegClassForReg(*MRI, UseReg), M,
Indexes);
diff --git a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
index 360880a7afb19c..45a2fdd4d73a25 100644
--- a/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
+++ b/llvm/lib/Target/Hexagon/HexagonBitTracker.cpp
@@ -86,7 +86,7 @@ BT::BitMask HexagonEvaluator::mask(Register Reg, unsigned Sub) const {
bool IsSubLo = (Sub == HRI.getHexagonSubRegIndex(RC, Hexagon::ps_sub_lo));
switch (ID) {
case Hexagon::DoubleRegsRegClassID:
- case Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID:
+ case Hexagon::DoubleRegs_with_isub_lo_in_IntRegsLow8RegClassID:
case Hexagon::HvxWRRegClassID:
case Hexagon::HvxVQRRegClassID:
return IsSubLo ? BT::BitMask(0, RW-1)
@@ -132,7 +132,7 @@ const TargetRegisterClass &HexagonEvaluator::composeWithSubRegIndex(
switch (RC.getID()) {
case Hexagon::DoubleRegsRegClassID:
- case Hexagon::DoubleRegs_with_isub_hi_in_IntRegsLow8RegClassID:
+ case Hexagon::DoubleRegs_with_isub_lo_in_IntRegsLow8RegClassID:
return Hexagon::IntRegsRegClass;
case Hexagon::HvxWRRegClassID:
return Hexagon::HvxVRRegClass;
diff --git a/llvm/test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll b/llvm/test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll
index aa68f951076e61..ff032f7620fcc7 100644
--- a/llvm/test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll
+++ b/llvm/test/CodeGen/AArch64/arm64-neon-vector-list-spill.ll
@@ -8,25 +8,21 @@
define i32 @spill.DPairReg(ptr %arg1, i32 %arg2) {
; CHECK-LABEL: spill.DPairReg:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ld2 { v0.2s, v1.2s }, [x0]
-; CHECK-NEXT: cbz w1, .LBB0_2
-; CHECK-NEXT: // %bb.1: // %if.end
-; CHECK-NEXT: mov w0, v0.s[1]
-; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB0_2: // %if.then
-; CHECK-NEXT: sub sp, sp, #48
-; CHECK-NEXT: stp x29, x30, [sp, #32] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 48
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: st1 { v0.2d, v1.2d }, [x8] // 32-byte Folded Spill
+; CHECK-NEXT: stp d9, d8, [sp, #-32]! // 16-byte Folded Spill
+; CHECK-NEXT: str x30, [sp, #16] // 8-byte Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 32
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: .cfi_offset b8, -24
+; CHECK-NEXT: .cfi_offset b9, -32
+; CHECK-NEXT: ld2 { v8.2s, v9.2s }, [x0]
+; CHECK-NEXT: cbnz w1, .LBB0_2
+; CHECK-NEXT: // %bb.1: // %if.then
; CHECK-NEXT: bl foo
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: ldp x29, x30, [sp, #32] // 16-byte Folded Reload
-; CHECK-NEXT: ld1 { v0.2d, v1.2d }, [x8] // 32-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #48
+; CHECK-NEXT: .LBB0_2: // %if.end
+; CHECK-NEXT: fmov d0, d8
+; CHECK-NEXT: ldr x30, [sp, #16] // 8-byte Reload
; CHECK-NEXT: mov w0, v0.s[1]
+; CHECK-NEXT: ldp d9, d8, [sp], #32 // 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
%vld = tail call { <2 x i32>, <2 x i32> } @llvm.aarch64.neon.ld2.v2i32.p0(ptr %arg1)
@@ -46,25 +42,24 @@ if.end:
define i16 @spill.DTripleReg(ptr %arg1, i32 %arg2) {
; CHECK-LABEL: spill.DTripleReg:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ld3 { v0.4h, v1.4h, v2.4h }, [x0]
-; CHECK-NEXT: cbz w1, .LBB1_2
-; CHECK-NEXT: // %bb.1: // %if.end
-; CHECK-NEXT: umov w0, v0.h[1]
-; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB1_2: // %if.then
-; CHECK-NEXT: sub sp, sp, #64
-; CHECK-NEXT: stp x29, x30, [sp, #48] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 64
+; CHECK-NEXT: str d10, [sp, #-32]! // 8-byte Folded Spill
+; CHECK-NEXT: stp d9, d8, [sp, #8] // 16-byte Folded Spill
+; CHECK-NEXT: str x30, [sp, #24] // 8-byte Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 32
; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: st1 { v0.2d, v1.2d, v2.2d }, [x8] // 48-byte Folded Spill
+; CHECK-NEXT: .cfi_offset b8, -16
+; CHECK-NEXT: .cfi_offset b9, -24
+; CHECK-NEXT: .cfi_offset b10, -32
+; CHECK-NEXT: ld3 { v8.4h, v9.4h, v10.4h }, [x0]
+; CHECK-NEXT: cbnz w1, .LBB1_2
+; CHECK-NEXT: // %bb.1: // %if.then
; CHECK-NEXT: bl foo
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: ldp x29, x30, [sp, #48] // 16-byte Folded Reload
-; CHECK-NEXT: ld1 { v0.2d, v1.2d, v2.2d }, [x8] // 48-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #64
+; CHECK-NEXT: .LBB1_2: // %if.end
+; CHECK-NEXT: fmov d0, d8
+; CHECK-NEXT: ldp d9, d8, [sp, #8] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x30, [sp, #24] // 8-byte Reload
; CHECK-NEXT: umov w0, v0.h[1]
+; CHECK-NEXT: ldr d10, [sp], #32 // 8-byte Folded Reload
; CHECK-NEXT: ret
entry:
%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld3.v4i16.p0(ptr %arg1)
@@ -84,25 +79,25 @@ if.end:
define i16 @spill.DQuadReg(ptr %arg1, i32 %arg2) {
; CHECK-LABEL: spill.DQuadReg:
; CHECK: // %bb.0: // %entry
-; CHECK-NEXT: ld4 { v0.4h, v1.4h, v2.4h, v3.4h }, [x0]
-; CHECK-NEXT: cbz w1, .LBB2_2
-; CHECK-NEXT: // %bb.1: // %if.end
-; CHECK-NEXT: umov w0, v0.h[0]
-; CHECK-NEXT: ret
-; CHECK-NEXT: .LBB2_2: // %if.then
-; CHECK-NEXT: sub sp, sp, #80
-; CHECK-NEXT: stp x29, x30, [sp, #64] // 16-byte Folded Spill
-; CHECK-NEXT: .cfi_def_cfa_offset 80
-; CHECK-NEXT: .cfi_offset w30, -8
-; CHECK-NEXT: .cfi_offset w29, -16
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: st1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x8] // 64-byte Folded Spill
+; CHECK-NEXT: stp d11, d10, [sp, #-48]! // 16-byte Folded Spill
+; CHECK-NEXT: stp d9, d8, [sp, #16] // 16-byte Folded Spill
+; CHECK-NEXT: str x30, [sp, #32] // 8-byte Spill
+; CHECK-NEXT: .cfi_def_cfa_offset 48
+; CHECK-NEXT: .cfi_offset w30, -16
+; CHECK-NEXT: .cfi_offset b8, -24
+; CHECK-NEXT: .cfi_offset b9, -32
+; CHECK-NEXT: .cfi_offset b10, -40
+; CHECK-NEXT: .cfi_offset b11, -48
+; CHECK-NEXT: ld4 { v8.4h, v9.4h, v10.4h, v11.4h }, [x0]
+; CHECK-NEXT: cbnz w1, .LBB2_2
+; CHECK-NEXT: // %bb.1: // %if.then
; CHECK-NEXT: bl foo
-; CHECK-NEXT: mov x8, sp
-; CHECK-NEXT: ldp x29, x30, [sp, #64] // 16-byte Folded Reload
-; CHECK-NEXT: ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x8] // 64-byte Folded Reload
-; CHECK-NEXT: add sp, sp, #80
+; CHECK-NEXT: .LBB2_2: // %if.end
+; CHECK-NEXT: fmov d0, d8
+; CHECK-NEXT: ldp d9, d8, [sp, #16] // 16-byte Folded Reload
+; CHECK-NEXT: ldr x30, [sp, #32] // 8-byte Reload
; CHECK-NEXT: umov w0, v0.h[0]
+; CHECK-NEXT: ldp d11, d10, [sp], #48 // 16-byte Folded Reload
; CHECK-NEXT: ret
entry:
%vld = tail call { <4 x i16>, <4 x i16>, <4 x i16>, <4 x i16> } @llvm.aarch64.neon.ld4.v4i16.p0(ptr %arg1)
diff --git a/llvm/test/CodeGen/AArch64/interleaved-accesses.ll b/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
index 2e52b3b3734849..14af346ee13a91 100644
--- a/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
+++ b/llvm/test/CodeGen/AArch64/interleaved-accesses.ll
@@ -906,8 +906,8 @@ define void @store_general_mask_factor4(ptr %ptr, <32 x i32> %v0, <32 x i32> %v1
; NEON-IAENABLED: // %bb.0:
; NEON-IAENABLED-NEXT: // kill: def $q4 killed $q4 def $q3_q4_q5_q6
; NEON-IAENABLED-NEXT: mov v6.16b, v2.16b
-; NEON-IAENABLED-NEXT: mov v3.16b, v1.16b
; NEON-IAENABLED-NEXT: ldr d5, [sp]
+; NEON-IAENABLED-NEXT: fmov d3, d1
; NEON-IAENABLED-NEXT: st4 { v3.2s, v4.2s, v5.2s, v6.2s }, [x0]
; NEON-IAENABLED-NEXT: ret
;
@@ -951,8 +951,8 @@ define void @store_general_mask_factor4_undefbeg(ptr %ptr, <32 x i32> %v0, <32 x
; NEON-IAENABLED: // %bb.0:
; NEON-IAENABLED-NEXT: // kill: def $q4 killed $q4 def $q3_q4_q5_q6
; NEON-IAENABLED-NEXT: mov v6.16b, v2.16b
-; NEON-IAENABLED-NEXT: mov v3.16b, v1.16b
; NEON-IAENABLED-NEXT: ldr d5, [sp]
+; NEON-IAENABLED-NEXT: fmov d3, d1
; NEON-IAENABLED-NEXT: st4 { v3.2s, v4.2s, v5.2s, v6.2s }, [x0]
; NEON-IAENABLED-NEXT: ret
;
@@ -999,8 +999,8 @@ define void @store_general_mask_factor4_undefend(ptr %ptr, <32 x i32> %v0, <32 x
; NEON-IAENABLED: // %bb.0:
; NEON-IAENABLED-NEXT: // kill: def $q4 killed $q4 def $q3_q4_q5_q6
; NEON-IAENABLED-NEXT: mov v6.16b, v2.16b
-; NEON-IAENABLED-NEXT: mov v3.16b, v1.16b
; NEON-IAENABLED-NEXT: ldr d5, [sp]
+; NEON-IAENABLED-NEXT: fmov d3, d1
; NEON-IAENABLED-NEXT: st4 { v3.2s, v4.2s, v5.2s, v6.2s }, [x0]
; NEON-IAENABLED-NEXT: ret
;
@@ -1043,8 +1043,8 @@ define void @store_general_mask_factor4_undefmid(ptr %ptr, <32 x i32> %v0, <32 x
; NEON-IAENABLED: // %bb.0:
; NEON-IAENABLED-NEXT: // kill: def $q4 killed $q4 def $q3_q4_q5_q6
; NEON-IAENABLED-NEXT: mov v6.16b, v2.16b
-; NEON-IAENABLED-NEXT: mov v3.16b, v1.16b
; NEON-IAENABLED-NEXT: ldr d5, [sp]
+; NEON-IAENABLED-NEXT: fmov d3, d1
; NEON-IAENABLED-NEXT: st4 { v3.2s, v4.2s, v5.2s, v6.2s }, [x0]
; NEON-IAENABLED-NEXT: ret
;
@@ -1083,11 +1083,12 @@ define void @store_general_mask_factor4_undefmid(ptr %ptr, <32 x i32> %v0, <32 x
define void @store_general_mask_factor4_undefmulti(ptr %ptr, <32 x i32> %v0, <32 x i32> %v1) {
; NEON-IAENABLED-LABEL: store_general_mask_factor4_undefmulti:
; NEON-IAENABLED: // %bb.0:
-; NEON-IAENABLED-NEXT: mov v5.16b, v2.16b
-; NEON-IAENABLED-NEXT: mov v2.16b, v1.16b
-; NEON-IAENABLED-NEXT: mov v3.16b, v0.16b
-; NEON-IAENABLED-NEXT: fmov d4, d3
-; NEON-IAENABLED-NEXT: st4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x0]
+; NEON-IAENABLED-NEXT: // kill: def $q2 killed $q2 killed $q31_q0_q1_q2 def $q31_q0_q1_q2
+; NEON-IAENABLED-NEXT: mov v3.16b, v1.16b
+; NEON-IAENABLED-NEXT: // kill: def $q0 killed $q0 killed $q31_q0_q1_q2 def $q31_q0_q1_q2
+; NEON-IAENABLED-NEXT: fmov d31, d3
+; NEON-IAENABLED-NEXT: fmov d1, d0
+; NEON-IAENABLED-NEXT: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [x0]
; NEON-IAENABLED-NEXT: ret
;
; NEON-IADISABLED-LABEL: store_general_mask_factor4_undefmulti:
@@ -2650,8 +2651,8 @@ define void @store_general_mask_factor4_intrinsic(ptr %ptr, <32 x i32> %v0, <32
; NEON: // %bb.0:
; NEON-NEXT: // kill: def $q4 killed $q4 def $q3_q4_q5_q6
; NEON-NEXT: mov v6.16b, v2.16b
-; NEON-NEXT: mov v3.16b, v1.16b
; NEON-NEXT: ldr d5, [sp]
+; NEON-NEXT: fmov d3, d1
; NEON-NEXT: st4 { v3.2s, v4.2s, v5.2s, v6.2s }, [x0]
; NEON-NEXT: ret
;
@@ -2687,8 +2688,8 @@ define void @store_general_mask_factor4_undefbeg_intrinsic(ptr %ptr, <32 x i32>
; NEON: // %bb.0:
; NEON-NEXT: // kill: def $q4 killed $q4 def $q3_q4_q5_q6
; NEON-NEXT: mov v6.16b, v2.16b
-; NEON-NEXT: mov v3.16b, v1.16b
; NEON-NEXT: ldr d5, [sp]
+; NEON-NEXT: fmov d3, d1
; NEON-NEXT: st4 { v3.2s, v4.2s, v5.2s, v6.2s }, [x0]
; NEON-NEXT: ret
;
@@ -2724,8 +2725,8 @@ define void @store_general_mask_factor4_undefend_intrinsic(ptr %ptr, <32 x i32>
; NEON: // %bb.0:
; NEON-NEXT: // kill: def $q4 killed $q4 def $q3_q4_q5_q6
; NEON-NEXT: mov v6.16b, v2.16b
-; NEON-NEXT: mov v3.16b, v1.16b
; NEON-NEXT: ldr d5, [sp]
+; NEON-NEXT: fmov d3, d1
; NEON-NEXT: st4 { v3.2s, v4.2s, v5.2s, v6.2s }, [x0]
; NEON-NEXT: ret
;
@@ -2761,8 +2762,8 @@ define void @store_general_mask_factor4_undefmid_intrinsic(ptr %ptr, <32 x i32>
; NEON: // %bb.0:
; NEON-NEXT: // kill: def $q4 killed $q4 def $q3_q4_q5_q6
; NEON-NEXT: mov v6.16b, v2.16b
-; NEON-NEXT: mov v3.16b, v1.16b
; NEON-NEXT: ldr d5, [sp]
+; NEON-NEXT: fmov d3, d1
; NEON-NEXT: st4 { v3.2s, v4.2s, v5.2s, v6.2s }, [x0]
; NEON-NEXT: ret
;
@@ -2796,11 +2797,12 @@ define void @store_general_mask_factor4_undefmid_intrinsic(ptr %ptr, <32 x i32>
define void @store_general_mask_factor4_undefmulti_intrinsic(ptr %ptr, <32 x i32> %v0, <32 x i32> %v1) {
; NEON-LABEL: store_general_mask_factor4_undefmulti_intrinsic:
; NEON: // %bb.0:
-; NEON-NEXT: mov v5.16b, v2.16b
-; NEON-NEXT: mov v2.16b, v1.16b
-; NEON-NEXT: mov v3.16b, v0.16b
-; NEON-NEXT: fmov d4, d3
-; NEON-NEXT: st4 { v2.2s, v3.2s, v4.2s, v5.2s }, [x0]
+; NEON-NEXT: // kill: def $q2 killed $q2 killed $q31_q0_q1_q2 def $q31_q0_q1_q2
+; NEON-NEXT: mov v3.16b, v1.16b
+; NEON-NEXT: // kill: def $q0 killed $q0 killed $q31_q0_q1_q2 def $q31_q0_q1_q2
+; NEON-NEXT: fmov d31, d3
+; NEON-NEXT: fmov d1, d0
+; NEON-NEXT: st4 { v31.2s, v0.2s, v1.2s, v2.2s }, [x0]
; NEON-NEXT: ret
;
; NO_NEON-LABEL: store_general_mask_factor4_undefmulti_intrinsic:
diff --git a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
index 2861933350d2ea..d2a1d98b51a737 100644
--- a/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
+++ b/llvm/test/CodeGen/AArch64/register-coalesce-update-subranges-remat.mir
@@ -7,8 +7,8 @@
# CHECK-DBG: ********** JOINING INTERVALS ***********
# CHECK-DBG: ********** INTERVALS **********
# CHECK-DBG: %0 [16r,32r:0) 0 at 16r weight:0.000000e+00
-# CHECK-DBG: %3 [48r,112r:0) 0 at 48r L0000000000000040 [48r,112r:0) 0 at 48r weight:0.000000e+00
-# CHECK-DBG: %4 [80r,112e:1)[112e,112d:0) 0 at 112e 1 at 80r L0000000000000080 [112e,112d:0) 0 at 112e L0000000000000040 [80r,112e:1)[112e,112d:0) 0 at 112e 1 at 80r weight:0.000000e+00
+# CHECK-DBG: %3 [48r,112r:0) 0 at 48r L0000000000000001 [48r,112r:0) 0 at 48r weight:0.000000e+00
+# CHECK-DBG: %4 [80r,112e:1)[112e,112d:0) 0 at 112e 1 at 80r L0000000000000200 [112e,112d:0) 0 at 112e L0000000000000001 [80r,112e:1)[112e,112d:0) 0 at 112e 1 at 80r weight:0.000000e+00
# CHECK-DBG: %5 [32r,112r:1)[112r,112d:0) 0 at 112r 1 at 32r weight:0.000000e+00
---
name: test
@@ -43,8 +43,8 @@ body: |
# CHECK-DBG: %1 [32r,48B:2)[48B,320r:0)[320r,368B:1) 0 at 48B-phi 1 at 320r 2 at 32r
# CHECK-DBG-SAME: weight:0.000000e+00
# CHECK-DBG: %3 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0 at 288r 1 at 240r 2 at 80r 3 at 304B-phi
-# CHECK-DBG-SAME: L0000000000000080 [288r,304B:0)[304B,320r:3) 0 at 288r 1 at x 2 at x 3 at 304B-phi
-# CHECK-DBG-SAME: L0000000000000040 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0 at 288r 1 at 240r 2 at 80r 3 at 304B-phi
+# CHECK-DBG-SAME: L0000000000000200 [288r,304B:0)[304B,320r:3) 0 at 288r 1 at x 2 at x 3 at 304B-phi
+# CHECK-DBG-SAME: L0000000000000001 [80r,160B:2)[240r,272B:1)[288r,304B:0)[304B,320r:3) 0 at 288r 1 at 240r 2 at 80r 3 at 304B-phi
# CHECK-DBG-SAME: weight:0.000000e+00
---
name: reproducer
@@ -89,8 +89,8 @@ body: |
# CHECK-DBG: %1 [32r,48B:2)[48B,304r:0)[304r,352B:1) 0 at 48B-phi 1 at 304r 2 at 32r
# CHECK-DBG-SAME: weight:0.000000e+00
# CHECK-DBG: %3 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0 at 272r 1 at 224r 2 at 80r 3 at 288B-phi
-# CHECK-DBG-SAME: L0000000000000080 [224r,256B:1)[272r,288B:0)[288B,304r:3) 0 at 272r 1 at 224r 2 at x 3 at 288B-phi
-# CHECK-DBG-SAME: L0000000000000040 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0 at 272r 1 at 224r 2 at 80r 3 at 288B-phi
+# CHECK-DBG-SAME: L0000000000000200 [224r,256B:1)[272r,288B:0)[288B,304r:3) 0 at 272r 1 at 224r 2 at x 3 at 288B-phi
+# CHECK-DBG-SAME: L0000000000000001 [80r,160B:2)[224r,256B:1)[272r,288B:0)[288B,304r:3) 0 at 272r 1 at 224r 2 at 80r 3 at 288B-phi
# CHECK-DBG-SAME: weight:0.000000e+00
---
name: reproducer2
diff --git a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
index 963c28aeba32b6..db33c02201183c 100644
--- a/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
+++ b/llvm/test/CodeGen/AArch64/vldn_shuffle.ll
@@ -517,18 +517,19 @@ define void @transpose_s16_8x8_simpler(ptr nocapture noundef %a) {
; CHECK-IAENABLED-NEXT: .cfi_startproc
; CHECK-IAENABLED-NEXT: // %bb.0: // %entry
; CHECK-IAENABLED-NEXT: ldp q0, q1, [x0]
-; CHECK-IAENABLED-NEXT: ldp q2, q3, [x0, #64]
-; CHECK-IAENABLED-NEXT: ldp q4, q5, [x0, #32]
+; CHECK-IAENABLED-NEXT: ldp q2, q3, [x0, #32]
+; CHECK-IAENABLED-NEXT: ldp q4, q5, [x0, #64]
; CHECK-IAENABLED-NEXT: ldp q6, q7, [x0, #96]
; CHECK-IAENABLED-NEXT: trn1 v0.8h, v0.8h, v1.8h
; CHECK-IAENABLED-NEXT: trn1 v1.8h, v2.8h, v3.8h
; CHECK-IAENABLED-NEXT: trn1 v2.8h, v4.8h, v5.8h
; CHECK-IAENABLED-NEXT: trn1 v3.8h, v6.8h, v7.8h
-; CHECK-IAENABLED-NEXT: trn1 v0.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: trn1 v1.4s, v2.4s, v3.4s
-; CHECK-IAENABLED-NEXT: zip2 v2.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x0]
-; CHECK-IAENABLED-NEXT: str q2, [x0, #64]
+; CHECK-IAENABLED-NEXT: trn1 v0.4s, v0.4s, v2.4s
+; CHECK-IAENABLED-NEXT: trn1 v2.4s, v1.4s, v3.4s
+; CHECK-IAENABLED-NEXT: zip2 v3.4s, v0.4s, v2.4s
+; CHECK-IAENABLED-NEXT: fmov d1, d0
+; CHECK-IAENABLED-NEXT: st2 { v1.2s, v2.2s }, [x0]
+; CHECK-IAENABLED-NEXT: str q3, [x0, #64]
; CHECK-IAENABLED-NEXT: ret
;
; CHECK-IADISABLED-LABEL: transpose_s16_8x8_simpler:
@@ -594,14 +595,15 @@ define void @transpose_s16_8x8_simpler2(ptr nocapture noundef %a) {
; CHECK-IAENABLED-NEXT: ldp q4, q5, [x0, #96]
; CHECK-IAENABLED-NEXT: trn1 v0.8h, v0.8h, v1.8h
; CHECK-IAENABLED-NEXT: zip1 v1.8h, v2.8h, v3.8h
+; CHECK-IAENABLED-NEXT: trn1 v2.8h, v4.8h, v5.8h
+; CHECK-IAENABLED-NEXT: trn1 v0.4s, v0.4s, v1.4s
+; CHECK-IAENABLED-NEXT: dup v1.4s, v2.s[2]
; CHECK-IAENABLED-NEXT: ldp q2, q3, [x0, #32]
-; CHECK-IAENABLED-NEXT: trn1 v4.8h, v4.8h, v5.8h
; CHECK-IAENABLED-NEXT: zip1 v3.8h, v2.8h, v3.8h
-; CHECK-IAENABLED-NEXT: trn1 v2.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: dup v0.4s, v4.s[2]
-; CHECK-IAENABLED-NEXT: zip2 v0.4s, v2.4s, v0.4s
+; CHECK-IAENABLED-NEXT: zip2 v1.4s, v0.4s, v1.4s
+; CHECK-IAENABLED-NEXT: fmov d2, d0
+; CHECK-IAENABLED-NEXT: str q1, [x0, #64]
; CHECK-IAENABLED-NEXT: st2 { v2.2s, v3.2s }, [x0]
-; CHECK-IAENABLED-NEXT: str q0, [x0, #64]
; CHECK-IAENABLED-NEXT: ret
;
; CHECK-IADISABLED-LABEL: transpose_s16_8x8_simpler2:
@@ -662,42 +664,46 @@ define void @transpose_s16_8x8(ptr nocapture noundef %0, ptr nocapture noundef %
; CHECK-IAENABLED: .Lfunc_begin9:
; CHECK-IAENABLED-NEXT: .cfi_startproc
; CHECK-IAENABLED-NEXT: // %bb.0:
-; CHECK-IAENABLED-NEXT: ldr q0, [x0]
-; CHECK-IAENABLED-NEXT: ldr q1, [x1]
-; CHECK-IAENABLED-NEXT: ldr q3, [x4]
-; CHECK-IAENABLED-NEXT: ldr q4, [x5]
-; CHECK-IAENABLED-NEXT: ldr q2, [x2]
-; CHECK-IAENABLED-NEXT: ldr q5, [x3]
-; CHECK-IAENABLED-NEXT: trn1 v16.8h, v0.8h, v1.8h
-; CHECK-IAENABLED-NEXT: trn2 v0.8h, v0.8h, v1.8h
+; CHECK-IAENABLED-NEXT: ldr q0, [x2]
+; CHECK-IAENABLED-NEXT: ldr q1, [x0]
+; CHECK-IAENABLED-NEXT: ldr q2, [x1]
+; CHECK-IAENABLED-NEXT: ldr q3, [x3]
+; CHECK-IAENABLED-NEXT: ldr q4, [x4]
+; CHECK-IAENABLED-NEXT: ldr q5, [x5]
+; CHECK-IAENABLED-NEXT: trn1 v16.8h, v1.8h, v2.8h
+; CHECK-IAENABLED-NEXT: trn2 v1.8h, v1.8h, v2.8h
; CHECK-IAENABLED-NEXT: ldr q6, [x6]
; CHECK-IAENABLED-NEXT: ldr q7, [x7]
-; CHECK-IAENABLED-NEXT: trn1 v17.8h, v3.8h, v4.8h
-; CHECK-IAENABLED-NEXT: trn2 v1.8h, v3.8h, v4.8h
-; CHECK-IAENABLED-NEXT: trn1 v18.8h, v2.8h, v5.8h
-; CHECK-IAENABLED-NEXT: trn2 v2.8h, v2.8h, v5.8h
+; CHECK-IAENABLED-NEXT: trn1 v17.8h, v0.8h, v3.8h
+; CHECK-IAENABLED-NEXT: trn1 v18.8h, v4.8h, v5.8h
+; CHECK-IAENABLED-NEXT: trn2 v0.8h, v0.8h, v3.8h
+; CHECK-IAENABLED-NEXT: trn2 v2.8h, v4.8h, v5.8h
; CHECK-IAENABLED-NEXT: trn1 v19.8h, v6.8h, v7.8h
; CHECK-IAENABLED-NEXT: trn2 v3.8h, v6.8h, v7.8h
-; CHECK-IAENABLED-NEXT: trn1 v4.4s, v16.4s, v17.4s
-; CHECK-IAENABLED-NEXT: trn1 v6.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: trn2 v16.4s, v16.4s, v17.4s
-; CHECK-IAENABLED-NEXT: trn2 v0.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: trn1 v5.4s, v18.4s, v19.4s
-; CHECK-IAENABLED-NEXT: trn1 v7.4s, v2.4s, v3.4s
-; CHECK-IAENABLED-NEXT: trn2 v17.4s, v18.4s, v19.4s
-; CHECK-IAENABLED-NEXT: trn2 v1.4s, v2.4s, v3.4s
-; CHECK-IAENABLED-NEXT: st2 { v4.2s, v5.2s }, [x0]
-; CHECK-IAENABLED-NEXT: zip2 v2.4s, v4.4s, v5.4s
-; CHECK-IAENABLED-NEXT: zip2 v3.4s, v6.4s, v7.4s
-; CHECK-IAENABLED-NEXT: zip2 v4.4s, v16.4s, v17.4s
-; CHECK-IAENABLED-NEXT: st2 { v6.2s, v7.2s }, [x1]
-; CHECK-IAENABLED-NEXT: st2 { v16.2s, v17.2s }, [x2]
-; CHECK-IAENABLED-NEXT: st2 { v0.2s, v1.2s }, [x3]
-; CHECK-IAENABLED-NEXT: zip2 v0.4s, v0.4s, v1.4s
-; CHECK-IAENABLED-NEXT: str q2, [x4]
-; CHECK-IAENABLED-NEXT: str q3, [x5]
+; CHECK-IAENABLED-NEXT: trn1 v4.4s, v16.4s, v18.4s
+; CHECK-IAENABLED-NEXT: trn2 v16.4s, v16.4s, v18.4s
+; CHECK-IAENABLED-NEXT: trn1 v7.4s, v1.4s, v2.4s
+; CHECK-IAENABLED-NEXT: trn2 v1.4s, v1.4s, v2.4s
+; CHECK-IAENABLED-NEXT: trn1 v6.4s, v17.4s, v19.4s
+; CHECK-IAENABLED-NEXT: trn1 v21.4s, v0.4s, v3.4s
+; CHECK-IAENABLED-NEXT: trn2 v18.4s, v17.4s, v19.4s
+; CHECK-IAENABLED-NEXT: trn2 v3.4s, v0.4s, v3.4s
+; CHECK-IAENABLED-NEXT: zip2 v19.4s, v4.4s, v6.4s
+; CHECK-IAENABLED-NEXT: fmov d5, d4
+; CHECK-IAENABLED-NEXT: zip2 v0.4s, v7.4s, v21.4s
+; CHECK-IAENABLED-NEXT: fmov d20, d7
+; CHECK-IAENABLED-NEXT: zip2 v4.4s, v16.4s, v18.4s
+; CHECK-IAENABLED-NEXT: fmov d17, d16
+; CHECK-IAENABLED-NEXT: st2 { v5.2s, v6.2s }, [x0]
+; CHECK-IAENABLED-NEXT: zip2 v5.4s, v1.4s, v3.4s
+; CHECK-IAENABLED-NEXT: fmov d2, d1
+; CHECK-IAENABLED-NEXT: st2 { v20.2s, v21.2s }, [x1]
+; CHECK-IAENABLED-NEXT: st2 { v17.2s, v18.2s }, [x2]
+; CHECK-IAENABLED-NEXT: st2 { v2.2s, v3.2s }, [x3]
+; CHECK-IAENABLED-NEXT: str q19, [x4]
+; CHECK-IAENABLED-NEXT: str q0, [x5]
; CHECK-IAENABLED-NEXT: str q4, [x6]
-; CHECK-IAENABLED-NEXT: str q0, [x7]
+; CHECK-IAENABLED-NEXT: str q5, [x7]
; CHECK-IAENABLED-NEXT: ret
;
; CHECK-IADISABLED-LABEL: transpose_s16_8x8:
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
index 2caf9a6fc6cdeb..fbd2a60236cfd5 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-extract-vector-elt.mir
@@ -785,7 +785,7 @@ body: |
; GPRIDX-NEXT: {{ $}}
; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
- ; GPRIDX-NEXT: [[V_INDIRECT_REG_READ_GPR_IDX_B32_V8_:%[0-9]+]]:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], 11, implicit-def $m0, implicit $m0, implicit $exec
+ ; GPRIDX-NEXT: [[V_INDIRECT_REG_READ_GPR_IDX_B32_V8_:%[0-9]+]]:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], 4, implicit-def $m0, implicit $m0, implicit $exec
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_READ_GPR_IDX_B32_V8_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:sgpr(s32) = COPY $sgpr8
@@ -855,7 +855,7 @@ body: |
; GPRIDX-NEXT: {{ $}}
; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
- ; GPRIDX-NEXT: [[V_INDIRECT_REG_READ_GPR_IDX_B32_V8_:%[0-9]+]]:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], 71, implicit-def $m0, implicit $m0, implicit $exec
+ ; GPRIDX-NEXT: [[V_INDIRECT_REG_READ_GPR_IDX_B32_V8_:%[0-9]+]]:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], 10, implicit-def $m0, implicit $m0, implicit $exec
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_READ_GPR_IDX_B32_V8_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:sgpr(s32) = COPY $sgpr8
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
index ca13894aeb7010..77c5099cdffeea 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-insert-vector-elt.mir
@@ -405,7 +405,7 @@ body: |
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
; MOVREL-NEXT: $m0 = COPY [[COPY2]]
- ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0
+ ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 97, implicit $m0
; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]]
;
; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v2s64
@@ -415,7 +415,7 @@ body: |
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr4_sgpr5
; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr6
; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
- ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 4, implicit $m0
+ ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_:%[0-9]+]]:sgpr_128 = S_INDIRECT_REG_WRITE_MOVREL_B64_V2 [[COPY]], [[COPY1]], 97, implicit $m0
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V2_]]
%0:sgpr(<2 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3
%1:sgpr(s64) = COPY $sgpr4_sgpr5
@@ -440,7 +440,7 @@ body: |
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
; MOVREL-NEXT: $m0 = COPY [[COPY2]]
- ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0
+ ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 97, implicit $m0
; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]]
;
; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v4s64
@@ -450,7 +450,7 @@ body: |
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr8_sgpr9
; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr10
; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
- ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 4, implicit $m0
+ ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B64_V4 [[COPY]], [[COPY1]], 97, implicit $m0
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V4_]]
%0:sgpr(<4 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s64) = COPY $sgpr8_sgpr9
@@ -475,7 +475,7 @@ body: |
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
; MOVREL-NEXT: $m0 = COPY [[COPY2]]
- ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0
+ ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 97, implicit $m0
; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]]
;
; GPRIDX-LABEL: name: insert_vector_elt_s_s64_v8s64
@@ -485,7 +485,7 @@ body: |
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr16_sgpr17
; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr18
; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
- ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 4, implicit $m0
+ ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_:%[0-9]+]]:sgpr_512 = S_INDIRECT_REG_WRITE_MOVREL_B64_V8 [[COPY]], [[COPY1]], 97, implicit $m0
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V8_]]
%0:sgpr(<8 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15
%1:sgpr(s64) = COPY $sgpr16_sgpr17
@@ -510,7 +510,7 @@ body: |
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
; MOVREL-NEXT: $m0 = COPY [[COPY2]]
- ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0
+ ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 97, implicit $m0
; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]]
;
; GPRIDX-LABEL: name: extract_vector_elt_s_s64_v16s64
@@ -520,7 +520,7 @@ body: |
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_64 = COPY $sgpr40_sgpr41
; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr42
; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
- ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 4, implicit $m0
+ ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_:%[0-9]+]]:sgpr_1024 = S_INDIRECT_REG_WRITE_MOVREL_B64_V16 [[COPY]], [[COPY1]], 97, implicit $m0
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B64_V16_]]
%0:sgpr(<16 x s64>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14_sgpr15_sgpr16_sgpr17_sgpr18_sgpr19_sgpr20_sgpr21_sgpr22_sgpr23_sgpr24_sgpr25_sgpr26_sgpr27_sgpr28_sgpr29_sgpr30_sgpr31
%1:sgpr(s64) = COPY $sgpr40_sgpr41
@@ -715,7 +715,7 @@ body: |
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
; MOVREL-NEXT: $m0 = COPY [[COPY2]]
- ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0, implicit $exec
+ ; MOVREL-NEXT: [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 4, implicit $m0, implicit $exec
; MOVREL-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
;
; GPRIDX-LABEL: name: insert_vector_elt_vvs_s32_v8s32_add_1
@@ -724,7 +724,7 @@ body: |
; GPRIDX-NEXT: [[COPY:%[0-9]+]]:vreg_256 = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr8
; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
- ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 11, implicit-def $m0, implicit $m0, implicit $exec
+ ; GPRIDX-NEXT: [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_:%[0-9]+]]:vreg_256 = V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8 [[COPY]], [[COPY1]], [[COPY2]], 4, implicit-def $m0, implicit $m0, implicit $exec
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[V_INDIRECT_REG_WRITE_GPR_IDX_B32_V8_]]
%0:vgpr(<8 x s32>) = COPY $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7
%1:vgpr(s32) = COPY $vgpr8
@@ -791,7 +791,7 @@ body: |
; MOVREL-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; MOVREL-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
; MOVREL-NEXT: $m0 = COPY [[COPY2]]
- ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0
+ ; MOVREL-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 4, implicit $m0
; MOVREL-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
;
; GPRIDX-LABEL: name: insert_vector_elt_s_s32_v8s32_add_1
@@ -801,7 +801,7 @@ body: |
; GPRIDX-NEXT: [[COPY1:%[0-9]+]]:sreg_32 = COPY $sgpr8
; GPRIDX-NEXT: [[COPY2:%[0-9]+]]:sreg_32 = COPY $sgpr9
; GPRIDX-NEXT: $m0 = COPY [[COPY2]]
- ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 11, implicit $m0
+ ; GPRIDX-NEXT: [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_:%[0-9]+]]:sgpr_256 = S_INDIRECT_REG_WRITE_MOVREL_B32_V8 [[COPY]], [[COPY1]], 4, implicit $m0
; GPRIDX-NEXT: S_ENDPGM 0, implicit [[S_INDIRECT_REG_WRITE_MOVREL_B32_V8_]]
%0:sgpr(<8 x s32>) = COPY $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7
%1:sgpr(s32) = COPY $sgpr8
diff --git a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
index 5752fde325d0cb..ffe385a6951b2f 100644
--- a/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
+++ b/llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
@@ -41,7 +41,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.2:
; GFX90A-NEXT: successors: %bb.3(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56, $sgpr57, $sgpr20_sgpr21_sgpr22, $sgpr22_sgpr23, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr4, $vgpr5
+ ; GFX90A-NEXT: liveins: $sgpr14, $sgpr16, $sgpr17, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr18_sgpr19, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr40_sgpr41, $sgpr56, $sgpr57, $sgpr22_sgpr23, $sgpr20_sgpr21_sgpr22, $sgpr26_sgpr27, $sgpr24_sgpr25_sgpr26, $vgpr4, $vgpr5
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $vgpr13 = IMPLICIT_DEF implicit-def $vgpr12
; GFX90A-NEXT: renamable $vgpr3 = IMPLICIT_DEF implicit-def $vgpr2
@@ -574,7 +574,7 @@ define amdgpu_kernel void @f1(ptr addrspace(1) %arg, ptr addrspace(1) %arg1, i64
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: bb.44:
; GFX90A-NEXT: successors: %bb.45(0x80000000)
- ; GFX90A-NEXT: liveins: $sgpr14, $vgpr57, $sgpr16, $sgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $vgpr41, $vgpr42, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $sgpr20_sgpr21_sgpr22, $vgpr62, $sgpr24_sgpr25_sgpr26, $sgpr26_sgpr27, $vgpr46, $vgpr56, $vgpr2, $vgpr4, $vgpr5, $vgpr45, $vgpr47, $vgpr43, $vgpr44, $vgpr58, $vgpr60, $vgpr63, $vgpr59, $vgpr61, $vgpr40
+ ; GFX90A-NEXT: liveins: $sgpr14, $vgpr57, $sgpr16, $sgpr17, $vgpr30, $vgpr31, $sgpr4_sgpr5, $sgpr6_sgpr7, $sgpr8, $sgpr9, $sgpr10_sgpr11, $sgpr12_sgpr13, $sgpr28_sgpr29, $sgpr30_sgpr31, $sgpr34_sgpr35, $sgpr36_sgpr37, $sgpr38_sgpr39, $sgpr40_sgpr41, $sgpr42_sgpr43, $sgpr44_sgpr45, $sgpr46_sgpr47, $sgpr48_sgpr49, $vgpr41, $vgpr42, $sgpr54_sgpr55, $sgpr58_sgpr59, $sgpr60_sgpr61, $vgpr62, $sgpr20_sgpr21_sgpr22, $sgpr26_sgpr27, $sgpr24_sgpr25_sgpr26, $vgpr46, $vgpr56, $vgpr2, $vgpr4, $vgpr5, $vgpr45, $vgpr47, $vgpr43, $vgpr44, $vgpr58, $vgpr60, $vgpr63, $vgpr59, $vgpr61, $vgpr40
; GFX90A-NEXT: {{ $}}
; GFX90A-NEXT: renamable $sgpr52_sgpr53 = COPY renamable $sgpr36_sgpr37
; GFX90A-NEXT: renamable $vgpr8_vgpr9 = IMPLICIT_DEF
diff --git a/llvm/test/CodeGen/AMDGPU/frem.ll b/llvm/test/CodeGen/AMDGPU/frem.ll
index 486d7c15150bc9..7e0ceb5baf4406 100644
--- a/llvm/test/CodeGen/AMDGPU/frem.ll
+++ b/llvm/test/CodeGen/AMDGPU/frem.ll
@@ -529,67 +529,70 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: s_clause 0x1
; GFX11-TRUE16-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-TRUE16-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v0, 0
; GFX11-TRUE16-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-TRUE16-NEXT: s_clause 0x1
-; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v1, s[2:3]
-; GFX11-TRUE16-NEXT: global_load_d16_hi_b16 v0, v1, s[4:5] offset:8
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v1, v0, s[2:3]
+; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v0, s[4:5] offset:8
+; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(1)
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v3, |v1.l|
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v1, |v0.l|
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.h|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v2, |v0.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v1, v2
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v3, v2
; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB0_2
; GFX11-TRUE16-NEXT: ; %bb.1: ; %frem.else
-; GFX11-TRUE16-NEXT: v_and_b16 v3.l, 0x8000, v0.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v1, v2
+; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v3, v2
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v3.l, v0.l, v3.l, vcc_lo
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v4.l, v1.l, v0.h, vcc_lo
; GFX11-TRUE16-NEXT: s_branch .LBB0_3
; GFX11-TRUE16-NEXT: .LBB0_2:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
; GFX11-TRUE16-NEXT: .LBB0_3: ; %Flow18
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v2
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v3
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v3, 11
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, v2
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v2
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v1
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_4) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v2
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v4, 1
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
-; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX11-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -597,29 +600,51 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX11-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX11-TRUE16-NEXT: v_fma_f32 v1, -v4, v2, v1
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v4, v3, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX11-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX11-TRUE16-NEXT: .LBB0_8: ; %Flow19
-; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.h
-; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
-; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v5, v3, v4
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v4.l, v2.l
+; GFX11-TRUE16-NEXT: .LBB0_9: ; %Flow19
+; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v0.l
+; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v1.l|
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v3.l, s2
-; GFX11-TRUE16-NEXT: global_store_b16 v1, v0, s[0:1]
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.l, 0x7e00, v4.l, s2
+; GFX11-TRUE16-NEXT: global_store_b16 v2, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
; GFX11-FAKE16-LABEL: frem_f16:
@@ -778,41 +803,42 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s0, s1, s0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -820,23 +846,46 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1150-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1150-TRUE16-NEXT: s_add_i32 s0, s0, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1150-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, s0
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX1150-TRUE16-NEXT: .LBB0_9: ; %Flow19
; GFX1150-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1150-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
@@ -1012,41 +1061,42 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_9
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s0
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s0
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s1
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s1
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v5
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v4
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s1, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s0, v2
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB0_8
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s0, s1, s0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -1054,26 +1104,49 @@ define amdgpu_kernel void @frem_f16(ptr addrspace(1) %out, ptr addrspace(1) %in1
; GFX1200-TRUE16-NEXT: .LBB0_6: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s0, s0, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s0, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
+; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, s0
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1200-TRUE16-NEXT: .LBB0_8: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB0_6
-; GFX1200-TRUE16-NEXT: .LBB0_7: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB0_8: ; %Flow19
+; GFX1200-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX1200-TRUE16-NEXT: .LBB0_9: ; %Flow19
; GFX1200-TRUE16-NEXT: v_dual_mov_b32 v3, 0 :: v_dual_and_b32 v0, 0x7fff, v0
; GFX1200-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
@@ -6045,42 +6118,43 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, v4
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v3
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, v3
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v3
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, v3
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v6, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v3
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v3
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v3, v4, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v4, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, v4, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v2
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -6088,104 +6162,147 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: v_fma_f32 v2, -v5, v3, v2
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v4, v3, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX11-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX11-TRUE16-NEXT: .LBB9_8:
+; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow55
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX11-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v5, v3, v4
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v3.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX11-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX11-TRUE16-NEXT: .LBB9_9:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v3, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v4, 16, v1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v7, |v3.l|
-; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v6, |v4.l|
+; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v5, |v4.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v6
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_10
-; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else
+; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v7, v5
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB9_11
+; GFX11-TRUE16-NEXT: ; %bb.10: ; %frem.else
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v3.l
-; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v6
+; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v7, v5
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v5.l, v3.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB9_11
-; GFX11-TRUE16-NEXT: .LBB9_10:
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v6.l, v3.l, v0.h, vcc_lo
+; GFX11-TRUE16-NEXT: s_branch .LBB9_12
+; GFX11-TRUE16-NEXT: .LBB9_11:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr6
+; GFX11-TRUE16-NEXT: .LBB9_12: ; %Flow53
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v7
; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v7
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v5, v7
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v6
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, v6
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_2) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v6, 11
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v5
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v6
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -1, v6
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v7, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v7, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, null, v6, v6, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v7, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v10, v9
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v6, 1.0
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v6, 1
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v5
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, null, v6, v6, 1.0
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, v9, v8
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, vcc_lo, 1.0, v6, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v9, v10, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v10
+; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v10, v11, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v7, v10
-; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v9, v11, v7
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v11
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v12, v8, v11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v10
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v9, v11, v7
+; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v10, v12, v8
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v12, v13, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v10, v12, v8
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v7, v7, v10, v11
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v7, v7, v6, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v8, v8, v11, v12
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v8, v8, v6, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX11-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v5, v7
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v7
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v10, v8
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v7, v6, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, v7, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX11-TRUE16-NEXT: ; %bb.16: ; %Flow
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v7, v10
+; GFX11-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v9, -10, v9
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v8, v7, v8
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v8, v8
-; GFX11-TRUE16-NEXT: v_fma_f32 v5, -v8, v6, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, v5, v6
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v8, vcc_lo
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v8, v6, v7
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v6, v7, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v7, v6, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, v5
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v3.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v5.l, v5
+; GFX11-TRUE16-NEXT: v_bfi_b32 v5, 0x7fff, v5, v6
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX11-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr5
-; GFX11-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v6.l, v5.l
+; GFX11-TRUE16-NEXT: .LBB9_18: ; %Flow54
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v1.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v1, 0
@@ -6195,7 +6312,7 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v3.l|
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, vcc_lo
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v5.l, s2
+; GFX11-TRUE16-NEXT: v_cndmask_b16 v0.h, 0x7e00, v6.l, s2
; GFX11-TRUE16-NEXT: global_store_b32 v1, v0, s[0:1]
; GFX11-TRUE16-NEXT: s_endpgm
;
@@ -6464,41 +6581,42 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_and_b32 s7, s7, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s5, s6, s5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -6506,107 +6624,154 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT: s_add_i32 s5, s5, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s5, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1150-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB9_8:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
+; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow55
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, s5
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX1150-TRUE16-NEXT: .LBB9_9:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1150-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
-; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s8, s7
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
+; GFX1150-TRUE16-NEXT: ; %bb.10: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
-; GFX1150-TRUE16-NEXT: s_mov_b32 s8, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB9_11
-; GFX1150-TRUE16-NEXT: .LBB9_10:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s8, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s9
+; GFX1150-TRUE16-NEXT: s_mov_b32 s9, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB9_12
+; GFX1150-TRUE16-NEXT: .LBB9_11:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s9, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX1150-TRUE16-NEXT: .LBB9_12: ; %Flow53
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v1
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s7, s6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX1150-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s7, s8, s7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, 11
-; GFX1150-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: s_add_i32 s7, s7, 11
+; GFX1150-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
-; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, v3
+; GFX1150-TRUE16-NEXT: s_add_i32 s7, s7, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s7, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX1150-TRUE16-NEXT: ; %bb.16: ; %Flow
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, s7
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX1150-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, s6
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
+; GFX1150-TRUE16-NEXT: .LBB9_18: ; %Flow54
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -6911,161 +7076,208 @@ define amdgpu_kernel void @frem_v2f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s7, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s7, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_9
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute19
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s5
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s5
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s6
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v3
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v2
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s5, v0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_7
-; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_8
+; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s5, s6, s5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, 11
; GFX1200-TRUE16-NEXT: .LBB9_6: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s5, s5, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s5, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
+; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow55
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, s5
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-TRUE16-NEXT: .LBB9_8: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, s4
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_6
-; GFX1200-TRUE16-NEXT: .LBB9_7: ; %frem.loop_exit28
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB9_8:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s4, 16
+; GFX1200-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX1200-TRUE16-NEXT: .LBB9_9:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s5, s3, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s4, s8, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s6, s5, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s4
+; GFX1200-TRUE16-NEXT: s_and_b32 s4, s6, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s5, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s6, s6
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s4
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s7, s7
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s7, s6
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_10
-; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s7, s6
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s8, s7
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB9_11
+; GFX1200-TRUE16-NEXT: ; %bb.10: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s8, s7
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s6
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s9
-; GFX1200-TRUE16-NEXT: s_mov_b32 s8, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB9_11
-; GFX1200-TRUE16-NEXT: .LBB9_10:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s8, -1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s6, v0.h, s9
+; GFX1200-TRUE16-NEXT: s_mov_b32 s9, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB9_12
+; GFX1200-TRUE16-NEXT: .LBB9_11:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s9, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB9_11: ; %Flow53
+; GFX1200-TRUE16-NEXT: .LBB9_12: ; %Flow53
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s8, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s8, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s8, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_16
-; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s7
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_18
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s7
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s8
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v4
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v3
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s7, v1
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v1
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_15
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s7, s6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB9_17
+; GFX1200-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s7, s8, s7
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, 11
-; GFX1200-TRUE16-NEXT: .LBB9_14: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s7, s7, 11
+; GFX1200-TRUE16-NEXT: .LBB9_15: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s7, s7, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s7, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_15
+; GFX1200-TRUE16-NEXT: ; %bb.16: ; %Flow
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, s7
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-TRUE16-NEXT: .LBB9_17: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v2.l, s6
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB9_14
-; GFX1200-TRUE16-NEXT: .LBB9_15: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB9_16: ; %Flow54
+; GFX1200-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
+; GFX1200-TRUE16-NEXT: .LBB9_18: ; %Flow54
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s3, 0
; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s3, -1, 0
@@ -9217,42 +9429,43 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
; GFX11-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, v6
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v6, v5
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, v5
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v5
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v4, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, v5
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v8, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v7
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v5
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v5
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v5, v6, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v6, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v8, null, v5, v5, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, v6, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v5, 1.0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v4
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, null, v5, v5, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v8, v4
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, v8, v7
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v7, vcc_lo, 1.0, v5, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v9, v10, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
-; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v10
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v7, v10
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
-; GFX11-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
+; GFX11-TRUE16-NEXT: v_fma_f32 v12, -v9, v11, v7
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v11, v12, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v9, v11, v7
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v5, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v7, v7, v10, v11
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v7, v7, v5, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
; GFX11-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -9260,22 +9473,42 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v4, v6
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v6
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v7, v7
-; GFX11-TRUE16-NEXT: v_fma_f32 v4, -v7, v5, v4
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v7, v4, v5
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v7, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v6, v9, v7
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v6, -v6, v5, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, v6, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v6, v6, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v6, 11
; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX11-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr4
-; GFX11-TRUE16-NEXT: .LBB10_8:
+; GFX11-TRUE16-NEXT: ; %bb.7: ; %Flow133
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v8, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v6, v9
+; GFX11-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -10, v8
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v6, v6, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v7, v6, v7
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v7, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v6, -v7, v5, v6
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v6
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v5, v6, v5
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v5, v6, v5, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v4, v5, v4
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v5.l, v0.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v4.l, v4
+; GFX11-TRUE16-NEXT: v_bfi_b32 v4, 0x7fff, v4, v5
+; GFX11-TRUE16-NEXT: .LBB10_9:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v5, 16, v0
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v6, 16, v2
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9283,160 +9516,202 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v8, |v6.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v9, v8
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_10
-; GFX11-TRUE16-NEXT: ; %bb.9: ; %frem.else53
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_11
+; GFX11-TRUE16-NEXT: ; %bb.10: ; %frem.else53
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v5.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v9, v8
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v7.l, v5.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_11
-; GFX11-TRUE16-NEXT: .LBB10_10:
+; GFX11-TRUE16-NEXT: s_branch .LBB10_12
+; GFX11-TRUE16-NEXT: .LBB10_11:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX11-TRUE16-NEXT: .LBB10_12: ; %Flow131
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX11-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v7, v9
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v9, v8
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v8
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v10, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v7, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v7, v8
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v11, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v10
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v8
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v8
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v9, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, null, v8, v8, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v10, v9, v10
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v12, v11
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v9, vcc_lo, 1.0, v8, 1.0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v7
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v12, null, v8, v8, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v7, -1, v7
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v13, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v11, v7
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v11, v10
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v8, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v11, v12, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v12, v13, v12
+; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v12, v13, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v13, v9, v12
-; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v11, v13, v9
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v13
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v10, v13
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v12
-; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v11, v13, v9
+; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v12, v14, v10
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v12, v14, v10
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v9, v9, v12, v13
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v10
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v9, v9, v8, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX11-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v10, v10, v13, v14
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v10, v10, v8, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX11-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v7, v9
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, v9
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v9, v12, v10
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v9, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v9, v8, v12
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, v9, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v9, v11, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v9, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX11-TRUE16-NEXT: ; %bb.16: ; %Flow129
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v11, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v9, v12
+; GFX11-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -10, v11
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v9, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v9, v10
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v10, v10
-; GFX11-TRUE16-NEXT: v_fma_f32 v7, -v10, v8, v7
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v7
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v10, v7, v8
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v7, v7, v10, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v7, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX11-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr7
-; GFX11-TRUE16-NEXT: .LBB10_16:
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v9, -v10, v8, v9
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v9
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v8, v9, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v9, v8, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v7, v8, v7
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v8.l, v5.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v7.l, v7
+; GFX11-TRUE16-NEXT: v_bfi_b32 v7, 0x7fff, v7, v8
+; GFX11-TRUE16-NEXT: .LBB10_18:
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v10, |v1.l|
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v9, |v3.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v10, v9
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_18
-; GFX11-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_20
+; GFX11-TRUE16-NEXT: ; %bb.19: ; %frem.else20
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v1.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v10, v9
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v8.l, v1.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_19
-; GFX11-TRUE16-NEXT: .LBB10_18:
+; GFX11-TRUE16-NEXT: s_branch .LBB10_21
+; GFX11-TRUE16-NEXT: .LBB10_20:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: .LBB10_19: ; %Flow127
+; GFX11-TRUE16-NEXT: .LBB10_21: ; %Flow127
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX11-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX11-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v8, v10
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v10, v9
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v9, v9
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v12, v9
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v8, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v8, v9
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v12, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v11
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v9
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, -1, v9
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v9, v10, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v10, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v12, null, v9, v9, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, v10, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v13, v12
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v10, vcc_lo, 1.0, v9, 1.0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v8
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v13, null, v9, v9, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v8, -1, v8
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v14, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v12, v8
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, v12, v11
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v11, vcc_lo, 1.0, v9, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v12, v13, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v13, v14, v13
+; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v13, v14, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v10, v13
-; GFX11-TRUE16-NEXT: v_fma_f32 v15, -v12, v14, v10
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v14
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v15, v11, v14
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v14, v15, v13
-; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v12, v14, v10
+; GFX11-TRUE16-NEXT: v_fma_f32 v16, -v13, v15, v11
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v15, v16, v14
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v13, v15, v11
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v10, v10, v13, v14
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v11
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v10, v10, v9, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX11-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v11, v11, v14, v15
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v11, v11, v9, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX11-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX11-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v8, v10
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v10
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v10, v13, v11
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v10, v10
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v10, v9, v13
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, v10, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v10, v10, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v10, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX11-TRUE16-NEXT: ; %bb.25: ; %Flow125
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v12, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v10, v13
+; GFX11-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v12, -10, v12
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v10, v10, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v11, v10, v11
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v11, v11
-; GFX11-TRUE16-NEXT: v_fma_f32 v8, -v11, v9, v8
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v8
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v11, v8, v9
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v8, v8, v11, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v8, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX11-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr8
-; GFX11-TRUE16-NEXT: .LBB10_24:
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v10, -v11, v9, v10
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v10
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v9, v10, v9
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v9, v10, v9, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v8, v9, v8
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v9.l, v1.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v8.l, v8
+; GFX11-TRUE16-NEXT: v_bfi_b32 v8, 0x7fff, v8, v9
+; GFX11-TRUE16-NEXT: .LBB10_27:
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v9, 16, v1
; GFX11-TRUE16-NEXT: v_lshrrev_b32_e32 v10, 16, v3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
@@ -9444,81 +9719,102 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX11-TRUE16-NEXT: v_cvt_f32_f16_e64 v12, |v10.l|
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_cmp_ngt_f32_e32 vcc_lo, v13, v12
-; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_26
-; GFX11-TRUE16-NEXT: ; %bb.25: ; %frem.else
+; GFX11-TRUE16-NEXT: s_cbranch_vccz .LBB10_29
+; GFX11-TRUE16-NEXT: ; %bb.28: ; %frem.else
; GFX11-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, v9.l
; GFX11-TRUE16-NEXT: v_cmp_eq_f32_e32 vcc_lo, v13, v12
; GFX11-TRUE16-NEXT: s_mov_b32 s2, 0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
; GFX11-TRUE16-NEXT: v_cndmask_b16 v11.l, v9.l, v0.h, vcc_lo
-; GFX11-TRUE16-NEXT: s_branch .LBB10_27
-; GFX11-TRUE16-NEXT: .LBB10_26:
+; GFX11-TRUE16-NEXT: s_branch .LBB10_30
+; GFX11-TRUE16-NEXT: .LBB10_29:
; GFX11-TRUE16-NEXT: s_mov_b32 s2, -1
; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: .LBB10_27: ; %Flow123
+; GFX11-TRUE16-NEXT: .LBB10_30: ; %Flow123
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_and_b32 s2, s2, exec_lo
; GFX11-TRUE16-NEXT: s_cselect_b32 s2, 1, 0
; GFX11-TRUE16-NEXT: s_cmp_lg_u32 s2, 1
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX11-TRUE16-NEXT: ; %bb.28: ; %frem.compute
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX11-TRUE16-NEXT: ; %bb.31: ; %frem.compute
; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v11, v13
-; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v13, v12
-; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v12, v12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_frexp_mant_f32_e32 v15, v12
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v14, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v13, v11, 11
+; GFX11-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v11, v12
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v15, 1
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s2, v14
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v12
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, -1, v12
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v12, v13, 1
-; GFX11-TRUE16-NEXT: v_not_b32_e32 v13, v15
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v15, null, v12, v12, 1.0
-; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v14, v13, v14
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(SKIP_4) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v16, v15
-; GFX11-TRUE16-NEXT: v_div_scale_f32 v13, vcc_lo, 1.0, v12, 1.0
+; GFX11-TRUE16-NEXT: v_readfirstlane_b32 s3, v11
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v16, null, v12, v12, 1.0
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v11, -1, v11
+; GFX11-TRUE16-NEXT: v_rcp_f32_e32 v17, v16
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_not_b32_e32 v15, v11
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, v15, v14
+; GFX11-TRUE16-NEXT: v_div_scale_f32 v14, vcc_lo, 1.0, v12, 1.0
; GFX11-TRUE16-NEXT: s_denorm_mode 15
; GFX11-TRUE16-NEXT: s_waitcnt_depctr depctr_va_vdst(0)
-; GFX11-TRUE16-NEXT: v_fma_f32 v17, -v15, v16, 1.0
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v16, v17, v16
+; GFX11-TRUE16-NEXT: v_fma_f32 v18, -v16, v17, 1.0
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v17, v13, v16
-; GFX11-TRUE16-NEXT: v_fma_f32 v18, -v15, v17, v13
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v17, v18, v17
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v18, v14, v17
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v17, v18, v16
-; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v15, v17, v13
+; GFX11-TRUE16-NEXT: v_fma_f32 v19, -v16, v18, v14
+; GFX11-TRUE16-NEXT: v_fmac_f32_e32 v18, v19, v17
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v14, -v16, v18, v14
; GFX11-TRUE16-NEXT: s_denorm_mode 12
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
-; GFX11-TRUE16-NEXT: v_div_fmas_f32 v13, v13, v16, v17
-; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v14
-; GFX11-TRUE16-NEXT: v_div_fixup_f32 v13, v13, v12, 1.0
-; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX11-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
+; GFX11-TRUE16-NEXT: v_div_fmas_f32 v14, v14, v17, v18
+; GFX11-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
+; GFX11-TRUE16-NEXT: v_div_fixup_f32 v14, v14, v12, 1.0
+; GFX11-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX11-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
; GFX11-TRUE16-NEXT: s_sub_i32 s2, s2, s3
; GFX11-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, 11
-; GFX11-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
+; GFX11-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX11-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v11, v13
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v16, v13
; GFX11-TRUE16-NEXT: s_add_i32 s2, s2, -11
; GFX11-TRUE16-NEXT: s_cmp_gt_i32 s2, 11
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v13, v16, v14
+; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v13, v13
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v13, v12, v16
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v15, v13, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v13, v13, v15, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v13, v13, 11
+; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX11-TRUE16-NEXT: ; %bb.34: ; %Flow
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v15, s2
+; GFX11-TRUE16-NEXT: v_mov_b32_e32 v13, v16
+; GFX11-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_add_nc_u32_e32 v15, -10, v15
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v13, v13, v15
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_mul_f32_e32 v14, v13, v14
; GFX11-TRUE16-NEXT: v_rndne_f32_e32 v14, v14
-; GFX11-TRUE16-NEXT: v_fma_f32 v11, -v14, v12, v11
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v11
-; GFX11-TRUE16-NEXT: v_add_f32_e32 v14, v11, v12
-; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v11, v11, v14, vcc_lo
-; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v11, 11
-; GFX11-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX11-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX11-TRUE16-NEXT: ; implicit-def: $vgpr11
-; GFX11-TRUE16-NEXT: .LBB10_32: ; %Flow124
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_fma_f32 v13, -v14, v12, v13
+; GFX11-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v13
+; GFX11-TRUE16-NEXT: v_add_f32_e32 v12, v13, v12
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cndmask_b32_e32 v12, v13, v12, vcc_lo
+; GFX11-TRUE16-NEXT: v_ldexp_f32 v11, v12, v11
+; GFX11-TRUE16-NEXT: v_mov_b16_e32 v12.l, v9.l
+; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX11-TRUE16-NEXT: v_cvt_f16_f32_e32 v11.l, v11
+; GFX11-TRUE16-NEXT: v_bfi_b32 v11, 0x7fff, v11, v12
+; GFX11-TRUE16-NEXT: .LBB10_36: ; %Flow124
; GFX11-TRUE16-NEXT: v_cmp_lg_f16_e32 vcc_lo, 0, v2.l
; GFX11-TRUE16-NEXT: v_cmp_nle_f16_e64 s2, 0x7c00, |v0.l|
; GFX11-TRUE16-NEXT: v_mov_b32_e32 v2, 0
@@ -10017,41 +10313,42 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: s_and_b32 s9, s9, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
; GFX1150-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
; GFX1150-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s6, s8, s6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
@@ -10059,273 +10356,368 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1150-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1150-TRUE16-NEXT: s_add_i32 s6, s6, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1150-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1150-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1150-TRUE16-NEXT: .LBB10_8:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
+; GFX1150-TRUE16-NEXT: ; %bb.7: ; %Flow133
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, s6
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1150-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v1.l, s5
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX1150-TRUE16-NEXT: .LBB10_9:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1150-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
-; GFX1150-TRUE16-NEXT: ; %bb.9: ; %frem.else53
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
+; GFX1150-TRUE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
-; GFX1150-TRUE16-NEXT: s_mov_b32 s10, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_11
-; GFX1150-TRUE16-NEXT: .LBB10_10:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s11
+; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_12
+; GFX1150-TRUE16-NEXT: .LBB10_11:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX1150-TRUE16-NEXT: .LBB10_12: ; %Flow131
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX1150-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v1
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX1150-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s8, s9, s8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX1150-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, 11
-; GFX1150-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
+; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
-; GFX1150-TRUE16-NEXT: s_add_i32 s8, s8, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s8, 11
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, v3
+; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1150-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX1150-TRUE16-NEXT: ; %bb.16: ; %Flow129
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, s9
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1150-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX1150-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1150-TRUE16-NEXT: .LBB10_16:
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v2.l, s8
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
+; GFX1150-TRUE16-NEXT: .LBB10_18:
; GFX1150-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1150-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s8
; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
-; GFX1150-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_20
+; GFX1150-TRUE16-NEXT: ; %bb.19: ; %frem.else20
; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
; GFX1150-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_19
-; GFX1150-TRUE16-NEXT: .LBB10_18:
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_21
+; GFX1150-TRUE16-NEXT: .LBB10_20:
; GFX1150-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB10_19: ; %Flow127
+; GFX1150-TRUE16-NEXT: .LBB10_21: ; %Flow127
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
; GFX1150-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1150-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1150-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s9, v2
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX1150-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX1150-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; GFX1150-TRUE16-NEXT: s_sub_i32 s9, s10, s9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, 11
-; GFX1150-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX1150-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1150-TRUE16-NEXT: s_add_i32 s9, s9, -11
; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1150-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1150-TRUE16-NEXT: ; %bb.25: ; %Flow125
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v6, s9
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1150-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX1150-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1150-TRUE16-NEXT: .LBB10_24:
-; GFX1150-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v3.l, s7
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX1150-TRUE16-NEXT: .LBB10_27:
+; GFX1150-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1150-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1150-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
-; GFX1150-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
-; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1150-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
+; GFX1150-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
+; GFX1150-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_3)
-; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
-; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
-; GFX1150-TRUE16-NEXT: ; %bb.25: ; %frem.else
-; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
-; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
+; GFX1150-TRUE16-NEXT: s_cmp_ngt_f32 s12, s11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc0 .LBB10_29
+; GFX1150-TRUE16-NEXT: ; %bb.28: ; %frem.else
+; GFX1150-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
+; GFX1150-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
-; GFX1150-TRUE16-NEXT: s_mov_b32 s12, 0
-; GFX1150-TRUE16-NEXT: s_branch .LBB10_27
-; GFX1150-TRUE16-NEXT: .LBB10_26:
-; GFX1150-TRUE16-NEXT: s_mov_b32 s12, -1
+; GFX1150-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s13
+; GFX1150-TRUE16-NEXT: s_mov_b32 s13, 0
+; GFX1150-TRUE16-NEXT: s_branch .LBB10_30
+; GFX1150-TRUE16-NEXT: .LBB10_29:
+; GFX1150-TRUE16-NEXT: s_mov_b32 s13, -1
; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: .LBB10_27: ; %Flow123
+; GFX1150-TRUE16-NEXT: .LBB10_30: ; %Flow123
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1150-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
-; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX1150-TRUE16-NEXT: ; %bb.28: ; %frem.compute
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
-; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
-; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: s_and_b32 s13, s13, exec_lo
+; GFX1150-TRUE16-NEXT: s_cselect_b32 s13, 1, 0
+; GFX1150-TRUE16-NEXT: s_cmp_lg_u32 s13, 1
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX1150-TRUE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
+; GFX1150-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1150-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_not_b32_e32 v6, v6
-; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1150-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v4, 1.0
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v3, 11
+; GFX1150-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s12, v6
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1150-TRUE16-NEXT: v_readfirstlane_b32 s11, v3
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1150-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_not_b32_e32 v7, v3
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
+; GFX1150-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1150-TRUE16-NEXT: s_denorm_mode 15
-; GFX1150-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
+; GFX1150-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
+; GFX1150-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1150-TRUE16-NEXT: s_denorm_mode 12
-; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX1150-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
-; GFX1150-TRUE16-NEXT: s_sub_i32 s10, s11, s10
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
+; GFX1150-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX1150-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1150-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX1150-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1150-TRUE16-NEXT: s_sub_i32 s11, s12, s11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, 11
-; GFX1150-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
+; GFX1150-TRUE16-NEXT: s_add_i32 s11, s11, 11
+; GFX1150-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX1150-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(SALU_CYCLE_1)
-; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
-; GFX1150-TRUE16-NEXT: s_add_i32 s10, s10, -11
-; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s10, 11
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v8, v5
+; GFX1150-TRUE16-NEXT: s_add_i32 s11, s11, -11
+; GFX1150-TRUE16-NEXT: s_cmp_gt_i32 s11, 11
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
-; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v5, v8, v6
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v3, v6, v4
-; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1150-TRUE16-NEXT: v_add_f32_e32 v6, v3, v4
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1150-TRUE16-NEXT: v_fma_f32 v5, v5, v4, v8
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v7, v5, v4
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX1150-TRUE16-NEXT: ; %bb.34: ; %Flow
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v7, s11
+; GFX1150-TRUE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX1150-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v5, v5, v7
; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
-; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1150-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX1150-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX1150-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1150-TRUE16-NEXT: .LBB10_32: ; %Flow124
+; GFX1150-TRUE16-NEXT: v_mul_f32_e32 v6, v5, v6
+; GFX1150-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
+; GFX1150-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v4
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1150-TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
+; GFX1150-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1150-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
+; GFX1150-TRUE16-NEXT: v_mov_b16_e32 v4.l, s10
+; GFX1150-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
+; GFX1150-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
+; GFX1150-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, v4
+; GFX1150-TRUE16-NEXT: .LBB10_36: ; %Flow124
; GFX1150-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1150-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1150-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
@@ -10878,41 +11270,42 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_cselect_b32 s9, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s9, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_8
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_9
; GFX1200-TRUE16-NEXT: ; %bb.4: ; %frem.compute85
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s6
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s8
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v0, s8
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v3
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v2
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, null, v1, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v3, v3
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v5, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, v3, v2
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, v1, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v0, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v0, s6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v1, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s6, v0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v0, -1, v0
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v0
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v1, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v5
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v4, v6, v2
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v2, v2, v5, v6
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v3
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v2, v2, v1, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v1, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_8
; GFX1200-TRUE16-NEXT: ; %bb.5: ; %frem.loop_body93.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s6, s8, s6
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -10920,119 +11313,165 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: .LBB10_6: ; %frem.loop_body93
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v0, v2
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s6, s6, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s6, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v2, v2
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v2, 0x80000000, v2
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v2, v2, v1, v5
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v2, v1
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v4, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
+; GFX1200-TRUE16-NEXT: ; %bb.7: ; %Flow133
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, s6
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v2, v5
+; GFX1200-TRUE16-NEXT: .LBB10_8: ; %frem.loop_exit94
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -10, v4
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v2, v3
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v0, v3, v1
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v3, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v0
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v0, v1
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v1, v2, v1
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v0, v0, v3, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v2, v1, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v1, v0
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v1.l, s5
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v0.l, v0
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v0, v0, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_6
-; GFX1200-TRUE16-NEXT: .LBB10_7: ; %frem.loop_exit94
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr0
-; GFX1200-TRUE16-NEXT: .LBB10_8:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s5, 16
+; GFX1200-TRUE16-NEXT: v_bfi_b32 v0, 0x7fff, v0, v1
+; GFX1200-TRUE16-NEXT: .LBB10_9:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s8, s5, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s6, s4, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s5, s10, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s8, s6, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s5
+; GFX1200-TRUE16-NEXT: s_and_b32 s5, s8, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s9, s6, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s8, s8
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s5
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s9, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s9, s8
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_10
-; GFX1200-TRUE16-NEXT: ; %bb.9: ; %frem.else53
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s9, s8
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_11
+; GFX1200-TRUE16-NEXT: ; %bb.10: ; %frem.else53
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s8
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s10, v0.h, s11
-; GFX1200-TRUE16-NEXT: s_mov_b32 s10, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_11
-; GFX1200-TRUE16-NEXT: .LBB10_10:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s10, -1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v1.l, s8, v0.h, s11
+; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_12
+; GFX1200-TRUE16-NEXT: .LBB10_11:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB10_11: ; %Flow131
+; GFX1200-TRUE16-NEXT: .LBB10_12: ; %Flow131
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s10, s10, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s10, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s10, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_16
-; GFX1200-TRUE16-NEXT: ; %bb.12: ; %frem.compute52
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s8
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s9
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s9
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_18
+; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.compute52
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s9
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v1, s10
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s8, v4
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, -1, v4
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v3
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, null, v2, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v4, v4
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v6, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v4, v4, v3
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v3, vcc_lo, 1.0, v2, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v1, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v1, s9
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v2, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v1
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v1, -1, v1
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v1
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v2, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v6, v7, v6
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v5, v7, v3
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v3, v3, v6, v7
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v4
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v3, v3, v2, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_15
-; GFX1200-TRUE16-NEXT: ; %bb.13: ; %frem.loop_body60.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s8, s9, s8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v2, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_17
+; GFX1200-TRUE16-NEXT: ; %bb.14: ; %frem.loop_body60.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, 11
-; GFX1200-TRUE16-NEXT: .LBB10_14: ; %frem.loop_body60
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
+; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_body60
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v1, v3
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s8, s8, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s8, 11
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v3, v6, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v3, v3
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v3, 0x80000000, v3
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v3, v3, v2, v6
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v3, v2
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v5, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_15
+; GFX1200-TRUE16-NEXT: ; %bb.16: ; %Flow129
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, s9
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v3, v6
+; GFX1200-TRUE16-NEXT: .LBB10_17: ; %frem.loop_exit61
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -10, v5
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v3, v4
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v1, v4, v2
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v4, v2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v1
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v1, v2
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v2, v3, v2
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v1, v1, v4, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v3, v2, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v2, v1
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v2.l, s8
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v1.l, v1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v1, v1, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_14
-; GFX1200-TRUE16-NEXT: .LBB10_15: ; %frem.loop_exit61
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr1
-; GFX1200-TRUE16-NEXT: .LBB10_16:
+; GFX1200-TRUE16-NEXT: v_bfi_b32 v1, 0x7fff, v1, v2
+; GFX1200-TRUE16-NEXT: .LBB10_18:
; GFX1200-TRUE16-NEXT: s_and_b32 s8, s7, 0x7fff
; GFX1200-TRUE16-NEXT: s_and_b32 s9, s2, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
@@ -11041,8 +11480,8 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s10, s9
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_18
-; GFX1200-TRUE16-NEXT: ; %bb.17: ; %frem.else20
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_20
+; GFX1200-TRUE16-NEXT: ; %bb.19: ; %frem.else20
; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s10, s9
; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s7
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, -1, 0
@@ -11050,172 +11489,219 @@ define amdgpu_kernel void @frem_v4f16(ptr addrspace(1) %out, ptr addrspace(1) %i
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_cndmask_b16 v2.l, s7, v0.h, s11
; GFX1200-TRUE16-NEXT: s_mov_b32 s11, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_19
-; GFX1200-TRUE16-NEXT: .LBB10_18:
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_21
+; GFX1200-TRUE16-NEXT: .LBB10_20:
; GFX1200-TRUE16-NEXT: s_mov_b32 s11, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB10_19: ; %Flow127
+; GFX1200-TRUE16-NEXT: .LBB10_21: ; %Flow127
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_and_b32 s11, s11, exec_lo
; GFX1200-TRUE16-NEXT: s_cselect_b32 s11, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s11, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
-; GFX1200-TRUE16-NEXT: ; %bb.20: ; %frem.compute19
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_27
+; GFX1200-TRUE16-NEXT: ; %bb.22: ; %frem.compute19
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s9
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s9
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v4, s10
; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v2, s10
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s10
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v5
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, -1, v5
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v4
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, null, v3, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v5, v5
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v7, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v5, v5, v4
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v4, vcc_lo, 1.0, v3, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v2, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v2, s9
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v3, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s9, v2
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v2, -1, v2
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v2
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v3, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v8, -v6, v7, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v7, v8, v7
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v8, v4, v7
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v6, v8, v4
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v4, -v6, v8, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
+; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v4, v4, v7, v8
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v5
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v4, v4, v3, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_23
-; GFX1200-TRUE16-NEXT: ; %bb.21: ; %frem.loop_body27.preheader
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v3, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_26
+; GFX1200-TRUE16-NEXT: ; %bb.23: ; %frem.loop_body27.preheader
; GFX1200-TRUE16-NEXT: s_sub_co_i32 s9, s10, s9
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, 11
-; GFX1200-TRUE16-NEXT: .LBB10_22: ; %frem.loop_body27
+; GFX1200-TRUE16-NEXT: .LBB10_24: ; %frem.loop_body27
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_add_co_i32 s9, s9, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s9, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v4, v7, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v4, v4
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v4, 0x80000000, v4
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v4, v4, v3, v7
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v4, v3
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v4, v6, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_24
+; GFX1200-TRUE16-NEXT: ; %bb.25: ; %Flow125
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v6, s9
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v4, v7
+; GFX1200-TRUE16-NEXT: .LBB10_26: ; %frem.loop_exit28
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -10, v6
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v4, v5
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v2, v5, v3
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v4, v5, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v2
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v5, v2, v3
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v4
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v3, v4, v3
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v2, v2, v5, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v4, v3, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v3, v2
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v3.l, s7
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v2.l, v2
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v2, v2, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_22
-; GFX1200-TRUE16-NEXT: .LBB10_23: ; %frem.loop_exit28
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr2
-; GFX1200-TRUE16-NEXT: .LBB10_24:
-; GFX1200-TRUE16-NEXT: s_lshr_b32 s12, s7, 16
+; GFX1200-TRUE16-NEXT: v_bfi_b32 v2, 0x7fff, v2, v3
+; GFX1200-TRUE16-NEXT: .LBB10_27:
+; GFX1200-TRUE16-NEXT: s_lshr_b32 s10, s7, 16
; GFX1200-TRUE16-NEXT: s_lshr_b32 s9, s2, 16
-; GFX1200-TRUE16-NEXT: s_and_b32 s7, s12, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s10, s9, 0x7fff
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s7
+; GFX1200-TRUE16-NEXT: s_and_b32 s7, s10, 0x7fff
+; GFX1200-TRUE16-NEXT: s_and_b32 s11, s9, 0x7fff
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s10, s10
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s12, s7
+; GFX1200-TRUE16-NEXT: s_cvt_f32_f16 s11, s11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(SALU_CYCLE_2)
-; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s11, s10
-; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_26
-; GFX1200-TRUE16-NEXT: ; %bb.25: ; %frem.else
-; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s11, s10
-; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s12
+; GFX1200-TRUE16-NEXT: s_cmp_ngt_f32 s12, s11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc0 .LBB10_29
+; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.else
+; GFX1200-TRUE16-NEXT: s_cmp_eq_f32 s12, s11
+; GFX1200-TRUE16-NEXT: v_and_b16 v0.h, 0x8000, s10
; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, -1, 0
-; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s12, v0.h, s13
-; GFX1200-TRUE16-NEXT: s_mov_b32 s12, 0
-; GFX1200-TRUE16-NEXT: s_branch .LBB10_27
-; GFX1200-TRUE16-NEXT: .LBB10_26:
-; GFX1200-TRUE16-NEXT: s_mov_b32 s12, -1
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instid1(SALU_CYCLE_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b16 v3.l, s10, v0.h, s13
+; GFX1200-TRUE16-NEXT: s_mov_b32 s13, 0
+; GFX1200-TRUE16-NEXT: s_branch .LBB10_30
+; GFX1200-TRUE16-NEXT: .LBB10_29:
+; GFX1200-TRUE16-NEXT: s_mov_b32 s13, -1
; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: .LBB10_27: ; %Flow123
+; GFX1200-TRUE16-NEXT: .LBB10_30: ; %Flow123
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_and_b32 s12, s12, exec_lo
-; GFX1200-TRUE16-NEXT: s_cselect_b32 s12, 1, 0
+; GFX1200-TRUE16-NEXT: s_and_b32 s13, s13, exec_lo
+; GFX1200-TRUE16-NEXT: s_cselect_b32 s13, 1, 0
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s12, 1
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_32
-; GFX1200-TRUE16-NEXT: ; %bb.28: ; %frem.compute
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s10
-; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v5, s11
-; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s11
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: s_cmp_lg_u32 s13, 1
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_36
+; GFX1200-TRUE16-NEXT: ; %bb.31: ; %frem.compute
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v4, s11
+; GFX1200-TRUE16-NEXT: v_frexp_mant_f32_e32 v3, s12
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v6, s12
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
; GFX1200-TRUE16-NEXT: v_ldexp_f32 v4, v4, 1
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s10, v6
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, -1, v6
-; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v5
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v7, null, v4, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_not_b32_e32 v6, v6
-; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v8, v7
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(TRANS32_DEP_1)
-; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v6, v6, v5
-; GFX1200-TRUE16-NEXT: v_div_scale_f32 v5, vcc_lo, 1.0, v4, 1.0
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v3, 11
+; GFX1200-TRUE16-NEXT: v_frexp_exp_i32_f32_e32 v3, s11
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s12, v6
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v8, null, v4, v4, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
+; GFX1200-TRUE16-NEXT: v_readfirstlane_b32 s11, v3
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v3, -1, v3
+; GFX1200-TRUE16-NEXT: v_rcp_f32_e32 v9, v8
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_not_b32_e32 v7, v3
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v7, v7, v6
+; GFX1200-TRUE16-NEXT: v_div_scale_f32 v6, vcc_lo, 1.0, v4, 1.0
; GFX1200-TRUE16-NEXT: s_denorm_mode 15
-; GFX1200-TRUE16-NEXT: v_fma_f32 v9, -v7, v8, 1.0
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(TRANS32_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v8, v9, 1.0
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v9
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v8, v9, v8
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v9, v5, v8
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v10, v6, v9
+; GFX1200-TRUE16-NEXT: v_fma_f32 v11, -v8, v10, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v10, -v7, v9, v5
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v9, v10, v8
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_fma_f32 v5, -v7, v9, v5
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v10, v11, v9
+; GFX1200-TRUE16-NEXT: v_fma_f32 v6, -v8, v10, v6
; GFX1200-TRUE16-NEXT: s_denorm_mode 12
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v5, v5, v8, v9
-; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v6
-; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2)
-; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v5, v5, v4, 1.0
-; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_31
-; GFX1200-TRUE16-NEXT: ; %bb.29: ; %frem.loop_body.preheader
-; GFX1200-TRUE16-NEXT: s_sub_co_i32 s10, s11, s10
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_div_fmas_f32 v6, v6, v9, v10
+; GFX1200-TRUE16-NEXT: v_cmp_gt_i32_e32 vcc_lo, 12, v7
+; GFX1200-TRUE16-NEXT: v_div_fixup_f32 v6, v6, v4, 1.0
+; GFX1200-TRUE16-NEXT: s_cbranch_vccnz .LBB10_35
+; GFX1200-TRUE16-NEXT: ; %bb.32: ; %frem.loop_body.preheader
+; GFX1200-TRUE16-NEXT: s_sub_co_i32 s11, s12, s11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, 11
-; GFX1200-TRUE16-NEXT: .LBB10_30: ; %frem.loop_body
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s11, s11, 11
+; GFX1200-TRUE16-NEXT: .LBB10_33: ; %frem.loop_body
; GFX1200-TRUE16-NEXT: ; =>This Inner Loop Header: Depth=1
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v3, v5
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v8, v5
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_add_co_i32 s10, s10, -11
+; GFX1200-TRUE16-NEXT: s_add_co_i32 s11, s11, -11
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_sa_sdst(0)
-; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s10, 11
+; GFX1200-TRUE16-NEXT: s_cmp_gt_i32 s11, 11
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v5, v8, v6
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v5, v5
+; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v5, 0x80000000, v5
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_fma_f32 v5, v5, v4, v8
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v7, v5, v4
+; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v5, v5, v7, vcc_lo
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v5, 11
+; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_33
+; GFX1200-TRUE16-NEXT: ; %bb.34: ; %Flow
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v7, s11
+; GFX1200-TRUE16-NEXT: v_mov_b32_e32 v5, v8
+; GFX1200-TRUE16-NEXT: .LBB10_35: ; %frem.loop_exit
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_add_nc_u32_e32 v7, -10, v7
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v5, v5, v7
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
+; GFX1200-TRUE16-NEXT: v_mul_f32_e32 v6, v5, v6
; GFX1200-TRUE16-NEXT: v_rndne_f32_e32 v6, v6
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX1200-TRUE16-NEXT: v_xor_b32_e32 v6, 0x80000000, v6
-; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v3, v6, v4
+; GFX1200-TRUE16-NEXT: v_fmac_f32_e32 v5, v6, v4
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_2) | instid1(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v3
-; GFX1200-TRUE16-NEXT: v_add_f32_e32 v6, v3, v4
+; GFX1200-TRUE16-NEXT: v_cmp_gt_f32_e32 vcc_lo, 0, v5
+; GFX1200-TRUE16-NEXT: v_add_f32_e32 v4, v5, v4
; GFX1200-TRUE16-NEXT: s_wait_alu depctr_va_vcc(0)
-; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v3, v3, v6, vcc_lo
+; GFX1200-TRUE16-NEXT: v_cndmask_b32_e32 v4, v5, v4, vcc_lo
+; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
+; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v4, v3
+; GFX1200-TRUE16-NEXT: v_mov_b16_e32 v4.l, s10
+; GFX1200-TRUE16-NEXT: v_cvt_f16_f32_e32 v3.l, v3
; GFX1200-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_1)
-; GFX1200-TRUE16-NEXT: v_ldexp_f32 v3, v3, 11
-; GFX1200-TRUE16-NEXT: s_cbranch_scc1 .LBB10_30
-; GFX1200-TRUE16-NEXT: .LBB10_31: ; %frem.loop_exit
-; GFX1200-TRUE16-NEXT: ; implicit-def: $vgpr3
-; GFX1200-TRUE16-NEXT: .LBB10_32: ; %Flow124
+; GFX1200-TRUE16-NEXT: v_bfi_b32 v3, 0x7fff, v3, v4
+; GFX1200-TRUE16-NEXT: .LBB10_36: ; %Flow124
; GFX1200-TRUE16-NEXT: s_cmp_lg_f16 s4, 0
; GFX1200-TRUE16-NEXT: s_cselect_b32 s4, -1, 0
; GFX1200-TRUE16-NEXT: s_cmp_nge_f16 s3, 0x7c00
diff --git a/llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll b/llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
index 37b2df465a6474..3ddeeaf68f469a 100644
--- a/llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
+++ b/llvm/test/CodeGen/AMDGPU/indirect-addressing-term.ll
@@ -85,7 +85,7 @@ define amdgpu_kernel void @extract_w_offset_vgpr(ptr addrspace(1) %out) {
; GCN-NEXT: renamable $sgpr2 = V_READFIRSTLANE_B32 [[COPY]](i32), implicit $exec
; GCN-NEXT: renamable $sgpr0_sgpr1 = V_CMP_EQ_U32_e64 $sgpr2, [[COPY]](i32), implicit $exec
; GCN-NEXT: renamable $sgpr0_sgpr1 = S_AND_SAVEEXEC_B64 killed renamable $sgpr0_sgpr1, implicit-def $exec, implicit-def dead $scc, implicit $exec
- ; GCN-NEXT: [[V_INDIRECT_REG_READ_GPR_IDX_B32_V16_:%[0-9]+]]:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V16 [[COPY17]], killed $sgpr2, 11, implicit-def $m0, implicit $m0, implicit $exec
+ ; GCN-NEXT: [[V_INDIRECT_REG_READ_GPR_IDX_B32_V16_:%[0-9]+]]:vgpr_32 = V_INDIRECT_REG_READ_GPR_IDX_B32_V16 [[COPY17]], killed $sgpr2, 4, implicit-def $m0, implicit $m0, implicit $exec
; GCN-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = COPY [[V_INDIRECT_REG_READ_GPR_IDX_B32_V16_]]
; GCN-NEXT: renamable $sgpr2_sgpr3 = COPY renamable $sgpr0_sgpr1
; GCN-NEXT: SI_SPILL_S64_SAVE killed $sgpr2_sgpr3, %stack.2, implicit $exec, implicit $sgpr32 :: (store (s64) into %stack.2, align 4, addrspace 5)
diff --git a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
index f37af9ad000c63..be5800db1dad1d 100644
--- a/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
+++ b/llvm/test/CodeGen/Hexagon/livephysregs-lane-masks.mir
@@ -24,11 +24,11 @@ body: |
J2_jumpt $p0, %bb.2, implicit-def $pc
bb.1:
- ; The lane mask $d0:0002 is equivalent to $r0. LivePhysRegs would ignore
+ ; The lane mask $d0:0001 is equivalent to $r0. LivePhysRegs would ignore
; it and treat it as the whole $d0, which is a pair $r1, $r0. The extra
; $r1 would cause an (undefined) implicit use to be added during
; if-conversion.
- liveins: $d0:0x00000002, $d15:0x00000001, $r16
+ liveins: $d0:0x00000001, $d15:0x00000002, $r16
successors: %bb.2
$r1 = L2_loadruh_io $r29, 6
S2_storeri_io killed $r16, 0, $r1
diff --git a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
index 04a19868b0671e..35af5f57f42968 100644
--- a/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
+++ b/llvm/test/CodeGen/Hexagon/regalloc-bad-undef.mir
@@ -155,7 +155,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.1.for.body:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.2(0x40000000)
- ; CHECK-NEXT: liveins: $d2:0x0000000000000002, $d8:0x0000000000000001, $d13, $r20
+ ; CHECK-NEXT: liveins: $d2:0x0000000000000001, $d8:0x0000000000000002, $d13, $r20
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: S2_storerd_io %stack.0, 0, renamable $d2 :: (store (s64) into %stack.0)
; CHECK-NEXT: ADJCALLSTACKDOWN 0, 0, implicit-def dead $r29, implicit-def dead $r30, implicit $r31, implicit $r30, implicit $r29
@@ -192,7 +192,7 @@ body: |
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: bb.2.if.end82:
; CHECK-NEXT: successors: %bb.3(0x40000000), %bb.1(0x40000000)
- ; CHECK-NEXT: liveins: $d2:0x0000000000000002, $d8:0x0000000000000001, $d13, $r20
+ ; CHECK-NEXT: liveins: $d2:0x0000000000000001, $d8:0x0000000000000002, $d13, $r20
; CHECK-NEXT: {{ $}}
; CHECK-NEXT: renamable $r20 = A2_addi killed renamable $r20, -1
; CHECK-NEXT: renamable $p0 = C2_cmpeqi renamable $r20, 0
diff --git a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
index 82e7fcc83f732b..af20a0e4b323ff 100644
--- a/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
+++ b/llvm/test/CodeGen/Hexagon/verify-liveness-at-def.mir
@@ -40,21 +40,21 @@ body: |
# CHECK-SUB: Bad machine code: Live range continues after dead def flag
# CHECK_SUB-NEXT: function: test_fail
# CHECK-SUB: v. register: %0
-# CHECK-SUB: lanemask: 0000000000000002
+# CHECK-SUB: lanemask: 0000000000000001
#
# CHECK-SUB-NOT: Bad machine code
#
# CHECK-SUB: Bad machine code: Live range continues after dead def flag
# CHECK-SUB-NEXT: function: test_fail
# CHECK-SUB: v. register: %1
-# CHECK-SUB: lanemask: 0000000000000002
+# CHECK-SUB: lanemask: 0000000000000001
#
# CHECK-SUB-NOT: Bad machine code
#
# CHECK-SUB: Bad machine code: Live range continues after dead def flag
# CHECK-SUB-NEXT: function: test_fail
# CHECK-SUB: v. register: %1
-# CHECK-SUB: lanemask: 0000000000000001
+# CHECK-SUB: lanemask: 0000000000000002
#
# CHECK-SUB: Bad machine code: Live range continues after dead def flag
# CHECK-SUB-NEXT: function: test_fail
diff --git a/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir b/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir
index c72939bb2a22c0..5acb8b6e2a4c35 100644
--- a/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir
+++ b/llvm/test/CodeGen/PowerPC/subreg-lanemasks.mir
@@ -5,17 +5,17 @@
# Keep track of all of the lanemasks for various subregisters.
#
-# CHECK: %3 [80r,80d:0) 0 at 80r L000000000000000C [80r,80d:0) 0 at 80r weight:0.000000e+00
+# CHECK: %3 [80r,80d:0) 0 at 80r L00000000000000C0 [80r,80d:0) 0 at 80r weight:0.000000e+00
# CHECK: %4 [96r,96d:0) 0 at 96r L0000000000003000 [96r,96d:0) 0 at 96r weight:0.000000e+00
-# CHECK: %5 [112r,112d:0) 0 at 112r L000000000000000C [112r,112d:0) 0 at 112r weight:0.000000e+00
+# CHECK: %5 [112r,112d:0) 0 at 112r L00000000000000C0 [112r,112d:0) 0 at 112r weight:0.000000e+00
# CHECK: %6 [128r,128d:0) 0 at 128r L0000000000003000 [128r,128d:0) 0 at 128r weight:0.000000e+00
-# CHECK: %7 [144r,144d:0) 0 at 144r L0000000000000004 [144r,144d:0) 0 at 144r weight:0.000000e+00
+# CHECK: %7 [144r,144d:0) 0 at 144r L0000000000000040 [144r,144d:0) 0 at 144r weight:0.000000e+00
# CHECK: %8 [160r,160d:0) 0 at 160r L0000000000001000 [160r,160d:0) 0 at 160r weight:0.000000e+00
-# CHECK: %9 [176r,176d:0) 0 at 176r L0000000000000004 [176r,176d:0) 0 at 176r weight:0.000000e+00
+# CHECK: %9 [176r,176d:0) 0 at 176r L0000000000000040 [176r,176d:0) 0 at 176r weight:0.000000e+00
# CHECK: %10 [192r,192d:0) 0 at 192r L0000000000001000 [192r,192d:0) 0 at 192r weight:0.000000e+00
# CHECK: %11 [208r,208d:0) 0 at 208r L0000000000004000 [208r,208d:0) 0 at 208r weight:0.000000e+00
# CHECK: %12 [224r,224d:0) 0 at 224r L0000000000010000 [224r,224d:0) 0 at 224r weight:0.000000e+00
-# CHECK: %13 [240r,240d:0) 0 at 240r L000000000000300C [240r,240d:0) 0 at 240r weight:0.000000e+00
+# CHECK: %13 [240r,240d:0) 0 at 240r L00000000000030C0 [240r,240d:0) 0 at 240r weight:0.000000e+00
# CHECK: %14 [256r,256d:0) 0 at 256r L000000000003C000 [256r,256d:0) 0 at 256r weight:0.000000e+00
diff --git a/llvm/test/TableGen/ArtificialSubregs.td b/llvm/test/TableGen/ArtificialSubregs.td
index 837c47f6269045..84ac3b82e9ca8c 100644
--- a/llvm/test/TableGen/ArtificialSubregs.td
+++ b/llvm/test/TableGen/ArtificialSubregs.td
@@ -104,7 +104,7 @@ def TestTarget : Target;
// CHECK: SuperClasses:
//
// CHECK-LABEL: RegisterClass DRegs:
-// CHECK: LaneMask: 0000000000000044
+// CHECK: LaneMask: 0000000000000003
// CHECK: HasDisjunctSubRegs: 1
// CHECK: CoveredBySubRegs: 1
// CHECK: Regs: D0 D1 D2
@@ -112,35 +112,35 @@ def TestTarget : Target;
// CHECK: SuperClasses:
//
// CHECK-LABEL: RegisterClass QRegs:
-// CHECK: LaneMask: 0000000000000045
+// CHECK: LaneMask: 0000000000000007
// CHECK: HasDisjunctSubRegs: 1
// CHECK: CoveredBySubRegs: 1
// CHECK: Regs: Q0 Q1 Q2
// CHECK: SubClasses: QRegs
// CHECK: SuperClasses:
//
+// CHECK-LABEL: SubRegIndex ssub:
+// CHECK-NEXT: LaneMask: 0000000000000001
+// CHECK-LABEL: SubRegIndex ssub_hi:
+// CHECK-NEXT: LaneMask: 0000000000000002
+// CHECK: Artificial: 1
// CHECK-LABEL: SubRegIndex dsub:
-// CHECK-NEXT: LaneMask: 0000000000000044
+// CHECK-NEXT: LaneMask: 0000000000000003
+// CHECK-LABEL: SubRegIndex dsub_hi:
+// CHECK-NEXT: LaneMask: 0000000000000004
+// CHECK: Artificial: 1
// CHECK-LABEL: SubRegIndex dsub0:
-// CHECK-NEXT: LaneMask: 0000000000000044
+// CHECK-NEXT: LaneMask: 0000000000000003
// CHECK-LABEL: SubRegIndex dsub1:
-// CHECK-NEXT: LaneMask: 0000000000000090
+// CHECK-NEXT: LaneMask: 00000000000000A0
// CHECK-LABEL: SubRegIndex dsub2:
-// CHECK-NEXT: LaneMask: 0000000000000120
-// CHECK-LABEL: SubRegIndex dsub_hi:
-// CHECK-NEXT: LaneMask: 0000000000000001
-// CHECK: Artificial: 1
-// CHECK-LABEL: SubRegIndex ssub:
-// CHECK-NEXT: LaneMask: 0000000000000004
+// CHECK-NEXT: LaneMask: 0000000000000140
// CHECK-LABEL: SubRegIndex ssub0:
-// CHECK-NEXT: LaneMask: 0000000000000008
-// CHECK-LABEL: SubRegIndex ssub1:
// CHECK-NEXT: LaneMask: 0000000000000010
-// CHECK-LABEL: SubRegIndex ssub2:
+// CHECK-LABEL: SubRegIndex ssub1:
// CHECK-NEXT: LaneMask: 0000000000000020
-// CHECK-LABEL: SubRegIndex ssub_hi:
+// CHECK-LABEL: SubRegIndex ssub2:
// CHECK-NEXT: LaneMask: 0000000000000040
-// CHECK: Artificial: 1
// CHECK-LABEL: SubRegIndex dsub1_then_ssub_hi:
// CHECK-NEXT: LaneMask: 0000000000000080
// CHECK: Artificial: 1
@@ -148,17 +148,17 @@ def TestTarget : Target;
// CHECK-NEXT: LaneMask: 0000000000000100
// CHECK: Artificial: 1
// CHECK-LABEL: SubRegIndex ssub_ssub1:
-// CHECK-NEXT: LaneMask: 0000000000000014
+// CHECK-NEXT: LaneMask: 0000000000000021
+// CHECK-LABEL: SubRegIndex ssub_ssub1_ssub2:
+// CHECK-NEXT: LaneMask: 0000000000000061
// CHECK-LABEL: SubRegIndex dsub0_dsub1:
-// CHECK-NEXT: LaneMask: 00000000000000D4
+// CHECK-NEXT: LaneMask: 00000000000000A3
// CHECK-LABEL: SubRegIndex dsub1_dsub2:
-// CHECK-NEXT: LaneMask: 00000000000001B0
-// CHECK-LABEL: SubRegIndex ssub_ssub1_ssub2:
-// CHECK-NEXT: LaneMask: 0000000000000034
+// CHECK-NEXT: LaneMask: 00000000000001E0
// CHECK-LABEL: SubRegIndex ssub1_ssub2:
-// CHECK-NEXT: LaneMask: 0000000000000030
+// CHECK-NEXT: LaneMask: 0000000000000060
// CHECK-LABEL: SubRegIndex ssub0_ssub1:
-// CHECK-NEXT: LaneMask: 0000000000000018
+// CHECK-NEXT: LaneMask: 0000000000000030
// CHECK-LABEL: Register D0:
// CHECK: CoveredBySubregs: 1
@@ -169,10 +169,10 @@ def TestTarget : Target;
// CHECK-LABEL: Register Q0:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 1
-// CHECK: SubReg dsub = D0
-// CHECK: SubReg dsub_hi = D0_HI
// CHECK: SubReg ssub = S0
// CHECK: SubReg ssub_hi = S0_HI
+// CHECK: SubReg dsub = D0
+// CHECK: SubReg dsub_hi = D0_HI
//
// CHECK-LABEL: Register S0:
// CHECK: CoveredBySubregs: 0
@@ -187,30 +187,30 @@ def TestTarget : Target;
// CHECK-LABEL: Register D0_D1:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 1
+// CHECK: SubReg ssub = S0
+// CHECK: SubReg ssub_hi = S0_HI
// CHECK: SubReg dsub0 = D0
// CHECK: SubReg dsub1 = D1
-// CHECK: SubReg ssub = S0
// CHECK: SubReg ssub1 = S1
-// CHECK: SubReg ssub_hi = S0_HI
// CHECK: SubReg dsub1_then_ssub_hi = S1_HI
// CHECK: SubReg ssub_ssub1 = S0_S1
//
// CHECK-LABEL: Register D0_D1_D2:
// CHECK: CoveredBySubregs: 1
// CHECK: HasDisjunctSubRegs: 1
+// CHECK: SubReg ssub = S0
+// CHECK: SubReg ssub_hi = S0_HI
// CHECK: SubReg dsub0 = D0
// CHECK: SubReg dsub1 = D1
// CHECK: SubReg dsub2 = D2
-// CHECK: SubReg ssub = S0
// CHECK: SubReg ssub1 = S1
// CHECK: SubReg ssub2 = S2
-// CHECK: SubReg ssub_hi = S0_HI
// CHECK: SubReg dsub1_then_ssub_hi = S1_HI
// CHECK: SubReg dsub2_then_ssub_hi = S2_HI
// CHECK: SubReg ssub_ssub1 = S0_S1
+// CHECK: SubReg ssub_ssub1_ssub2 = S0_S1_S2
// CHECK: SubReg dsub0_dsub1 = D0_D1
// CHECK: SubReg dsub1_dsub2 = D1_D2
-// CHECK: SubReg ssub_ssub1_ssub2 = S0_S1_S2
// CHECK: SubReg ssub1_ssub2 = S1_S2
//
// CHECK-LABEL: Register S0_S1:
diff --git a/llvm/test/TableGen/ConcatenatedSubregs.td b/llvm/test/TableGen/ConcatenatedSubregs.td
index cd65e753f1849b..1fa113e1b5bd57 100644
--- a/llvm/test/TableGen/ConcatenatedSubregs.td
+++ b/llvm/test/TableGen/ConcatenatedSubregs.td
@@ -89,12 +89,12 @@ def TestTarget : Target;
// CHECK: Regs: D0 D1 D2 D3 D4 D5 D6 D7 S1_S2 S3_S4 S5_S6 S7_S8 S9_S10 S11_S12 S13_S14
// CHECK-LABEL: RegisterClass DRegs:
-// CHECK-LABEL: SubRegIndex ssub1:
-// CHECK: Offset: 16
-// CHECK: Size: 16
// CHECK-LABEL: SubRegIndex sub0:
// CHECK-LABEL: SubRegIndex sub1:
// CHECK-LABEL: SubRegIndex sub2:
+// CHECK-LABEL: SubRegIndex ssub1:
+// CHECK: Offset: 16
+// CHECK: Size: 16
// Check inferred indexes:
// CHECK-LABEL: SubRegIndex ssub1_ssub2:
// CHECK: Offset: 16
@@ -113,26 +113,26 @@ def TestTarget : Target;
// CHECK-LABEL: Register S9_S10_S11_S12_S13:
// CHECK: HasDisjunctSubRegs: 1
+// CHECK-NEXT: SubReg sub0 = S9_S10
+// CHECK-NEXT: SubReg sub1 = S11_S12
// CHECK-NEXT: SubReg ssub0 = S9
// CHECK-NEXT: SubReg ssub1 = S10
// CHECK-NEXT: SubReg ssub2 = S11
// CHECK-NEXT: SubReg ssub3 = S12
// CHECK-NEXT: SubReg ssub4 = S13
-// CHECK-NEXT: SubReg sub0 = S9_S10
-// CHECK-NEXT: SubReg sub1 = S11_S12
// CHECK-NEXT: SubReg ssub1_ssub2 = D5
// CHECK-NEXT: SubReg ssub3_ssub4 = D6
// CHECK-NEXT: SubReg ssub1_ssub2_ssub3_ssub4 = D5_D6
// CHECK-LABEL: Register S10_S11_S12_S13_S14:
// CHECK: HasDisjunctSubRegs: 1
+// CHECK-NEXT: SubReg sub0 = D5
+// CHECK-NEXT: SubReg sub1 = D6
// CHECK-NEXT: SubReg ssub0 = S10
// CHECK-NEXT: SubReg ssub1 = S11
// CHECK-NEXT: SubReg ssub2 = S12
// CHECK-NEXT: SubReg ssub3 = S13
// CHECK-NEXT: SubReg ssub4 = S14
-// CHECK-NEXT: SubReg sub0 = D5
-// CHECK-NEXT: SubReg sub1 = D6
// CHECK-NEXT: SubReg ssub1_ssub2 = S11_S12
// CHECK-NEXT: SubReg ssub3_ssub4 = S13_S14
// CHECK-NEXT: SubReg ssub0_ssub1_ssub2_ssub3 = D5_D6
diff --git a/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td b/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
index 2513161eec24f0..442d25edfe4834 100644
--- a/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
+++ b/llvm/test/TableGen/GlobalISelEmitter/nested-subregs.td
@@ -47,7 +47,7 @@ def A0 : RegisterClass<"MyTarget", [i32], 32, (add a0)>;
// CHECK-NEXT: GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(static_cast<uint16_t>(RegState::Define)),
// CHECK-NEXT: GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1,
// CHECK-NEXT: GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src
-// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/3,
+// CHECK-NEXT: GIR_AddImm8, /*InsnID*/1, /*Imm*/1,
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(MyTarget::A0RegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(MyTarget::A0RegClassID),
// CHECK-NEXT: GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/2, GIMT_Encode2(MyTarget::A0bRegClassID),
diff --git a/llvm/test/TableGen/SubRegsAndAliases.td b/llvm/test/TableGen/SubRegsAndAliases.td
index bd062a7ab6f53c..dfe0c1793b6f2c 100644
--- a/llvm/test/TableGen/SubRegsAndAliases.td
+++ b/llvm/test/TableGen/SubRegsAndAliases.td
@@ -36,8 +36,8 @@ def C : Register<""> {
def TestRC : RegisterClass<"Test", [i64], 0, (add A, B)>;
// CHECK-LABEL: Register A:
-// CHECK: SubReg hi = Ahi
// CHECK: SubReg lo = Alo
+// CHECK: SubReg hi = Ahi
// CHECK: RegUnit 0
// CHECK: RegUnit 1
@@ -48,8 +48,8 @@ def TestRC : RegisterClass<"Test", [i64], 0, (add A, B)>;
// CHECK: RegUnit 0
// CHECK-LABEL: Register B:
-// CHECK: SubReg hi = Bhi
// CHECK: SubReg lo = Blo
+// CHECK: SubReg hi = Bhi
// CHECK: RegUnit 2
// CHECK: RegUnit 3
// CHECK: RegUnit 4
@@ -63,8 +63,8 @@ def TestRC : RegisterClass<"Test", [i64], 0, (add A, B)>;
// CHECK: RegUnit 3
// CHECK-LABEL: Register C:
-// CHECK: SubReg hi = Chi
// CHECK: SubReg lo = Clo
+// CHECK: SubReg hi = Chi
// CHECK: RegUnit 5
// CHECK: RegUnit 6
// CHECK: RegUnit 7
diff --git a/llvm/test/TableGen/dag-isel-subregs.td b/llvm/test/TableGen/dag-isel-subregs.td
index e0e94e033a9b22..dd7384409e2e19 100644
--- a/llvm/test/TableGen/dag-isel-subregs.td
+++ b/llvm/test/TableGen/dag-isel-subregs.td
@@ -9,6 +9,6 @@ def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 0))),
(EXTRACT_SUBREG GPR_1024:$src, sub0_sub1)>;
// CHECK: OPC_CheckChild1Integer, 15,
-// CHECK: OPC_EmitIntegerI32, 5|128,1/*133*/,
+// CHECK: OPC_EmitIntegerI32, sub30_sub31,
def : Pat<(v2i32 (extract_subvector v32i32:$src, (i32 15))),
(EXTRACT_SUBREG GPR_1024:$src, sub30_sub31)>;
diff --git a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
index ba42798c5c9bea..56b8c00514b8d5 100644
--- a/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
+++ b/llvm/test/tools/UpdateTestChecks/update_llc_test_checks/Inputs/amdgpu_isel.ll.expected
@@ -3,18 +3,18 @@
define i64 @i64_test(i64 %i) nounwind readnone {
; CHECK-LABEL: i64_test:
-; CHECK: SelectionDAG has 26 nodes:
+; CHECK: SelectionDAG has 25 nodes:
; CHECK-NEXT: t0: ch,glue = EntryToken
; CHECK-NEXT: t2: i32,ch = CopyFromReg # D:1 t0, Register:i32 %8
; CHECK-NEXT: t4: i32,ch = CopyFromReg # D:1 t0, Register:i32 %9
-; CHECK-NEXT: t51: i64 = REG_SEQUENCE # D:1 TargetConstant:i32<67>, t2, TargetConstant:i32<3>, t4, TargetConstant:i32<11>
+; CHECK-NEXT: t50: i64 = REG_SEQUENCE # D:1 TargetConstant:i32<67>, t2, TargetConstant:i32<3>, t4, TargetConstant:i32<4>
; CHECK-NEXT: t27: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc, align 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
; CHECK-NEXT: t30: i32,ch = BUFFER_LOAD_DWORD_OFFEN<Mem:(dereferenceable load (s32) from %ir.loc + 4, basealign 8, addrspace 5)> TargetFrameIndex:i32<0>, Register:v4i32 $sgpr0_sgpr1_sgpr2_sgpr3, TargetConstant:i32<0>, TargetConstant:i32<4>, TargetConstant:i32<0>, TargetConstant:i1<0>, t0
-; CHECK-NEXT: t33: v2i32 = REG_SEQUENCE # D:1 TargetConstant:i32<37>, t27, TargetConstant:i32<3>, t30, TargetConstant:i32<11>
-; CHECK-NEXT: t10: i64 = V_ADD_U64_PSEUDO # D:1 t51, t33
+; CHECK-NEXT: t33: v2i32 = REG_SEQUENCE # D:1 TargetConstant:i32<37>, t27, TargetConstant:i32<3>, t30, TargetConstant:i32<4>
+; CHECK-NEXT: t10: i64 = V_ADD_U64_PSEUDO # D:1 t50, t33
; CHECK-NEXT: t24: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<3>
; CHECK-NEXT: t17: ch,glue = CopyToReg # D:1 t0, Register:i32 $vgpr0, t24
-; CHECK-NEXT: t39: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<11>
+; CHECK-NEXT: t39: i32 = EXTRACT_SUBREG # D:1 t10, TargetConstant:i32<4>
; CHECK-NEXT: t19: ch,glue = CopyToReg # D:1 t17, Register:i32 $vgpr1, t39, t17:1
; CHECK-NEXT: t20: ch = SI_RETURN Register:i32 $vgpr0, Register:i32 $vgpr1, t19, t19:1
; CHECK-EMPTY:
diff --git a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
index 10a5a16feef787..cc9e51bc3328d3 100644
--- a/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
+++ b/llvm/utils/TableGen/Common/CodeGenRegisters.cpp
@@ -1230,9 +1230,15 @@ CodeGenRegBank::CodeGenRegBank(const RecordKeeper &Records,
Sets.addExpander("RegisterTuples",
std::make_unique<TupleExpander>(SynthDefs));
- // Read in the user-defined (named) sub-register indices.
+ // Read in the user-defined (named) sub-register indices. Do this in the order
+ // they were declared instead of alphabetical order, so that the order in
+ // which bits are chosen for the LaneBitmasks is more controllable and less
+ // surprising.
// More indices will be synthesized later.
- for (const Record *SRI : Records.getAllDerivedDefinitions("SubRegIndex"))
+ std::vector<const Record *> SRIs(
+ Records.getAllDerivedDefinitions("SubRegIndex"));
+ llvm::sort(SRIs, LessRecordByID());
+ for (const Record *SRI : SRIs)
getSubRegIdx(SRI);
// Build composite maps from ComposedOf fields.
for (auto &Idx : SubRegIndices)
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