[llvm] [AMDGPU] Limit DVGPR entry function max VGPRs to block size (PR #226242)

[Diana Picus via llvm-commits]

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@@ -1409,6 +1409,22 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
         MF.getFunction(), "local memory", MFI->getLDSSize(),
         STM.getAddressableLocalMemorySize(), DS_Error));
   }
+
+  // Catches the paths the register allocator budget cannot constrain: explicit
+  // physical registers in inline asm and wave dispatch VGPR arguments.
+  if (MFI->isDynamicVGPREnabled() &&
+      AMDGPU::isEntryFunctionCC(F.getCallingConv())) {
+    unsigned BlockSize = MFI->getDynamicVGPRBlockSize();
+    uint64_t NumVgpr;
+    if (TryGetMCExprValue(ProgInfo.NumVGPRsForWavesPerEU, NumVgpr) &&
+        NumVgpr > BlockSize) {
+      LLVMContext &Ctx = F.getContext();
+      Ctx.diagnose(DiagnosticInfoResourceLimit(
+          F, "dynamic VGPR entry point vector registers", NumVgpr, BlockSize,
+          DS_Error, DK_ResourceLimit));
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rovka wrote:

Should this be a warning instead? We have an intrinsic for S_ALLOC_VGPR, so it would be possible for the entry function to start with just one block but then increase its allocation. (That's probably not very robust right now, but we shouldn't hinder experimentation too much). Alternatively we could track during ISel if we saw the intrinsic, and only error out if we didn't.

https://github.com/llvm/llvm-project/pull/226242