[llvm] [AMDGPU] Limit DVGPR entry function max VGPRs to block size (PR #226242)

[Diana Picus via llvm-commits]

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@@ -1409,6 +1409,22 @@ void AMDGPUAsmPrinter::getSIProgramInfo(SIProgramInfo &ProgInfo,
         MF.getFunction(), "local memory", MFI->getLDSSize(),
         STM.getAddressableLocalMemorySize(), DS_Error));
   }
+
+  // Catches the paths the register allocator budget cannot constrain: explicit
+  // physical registers in inline asm and wave dispatch VGPR arguments.
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rovka wrote:

I think this comment needs a bit more context, along the lines of "When dynamic VGPRs are enabled, entry functions are launched with a single VGPR block. The register allocator enforces this constraint, but we also need to catch explicit physical registers in inline asm and wave dispatch VGPR arguments".

https://github.com/llvm/llvm-project/pull/226242