[clang] [llvm] [RISCV] Add processor definition and scheduling information for GR765 (PR #225638)

[Daniel Cederman via llvm-commits]

doac wrote:

> LGTM w/ one minor comment.
> 
> Also just curious: if the core doesn't support the P extension, why does the website say "Packed-SIMD Vector extension on each processor core"?

Thanks! It refers to the SIMD within a register (SWAR) extension that is there for both the SPARC and RISC-V version of GR765. I will forward internally that it is easy to mistake it for the P extension in this context.


https://github.com/llvm/llvm-project/pull/225638